TI TAS5611PHDR

TAS5611A
www.ti.com
SLAS709 – JUNE 2010
125W STEREO/250W MONO PurePath™ HD ANALOG-INPUT POWER STAGE
Check for Samples: TAS5611A
FEATURES
APPLICATIONS
•
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23
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PurePath™ HD Enabled Integrated Feedback
Provides:
– Signal Bandwidth up to 80kHz for High
Frequency Content From HD Sources
– Ultralow 0.03% THD at 1W into 4Ω
– Flat THD at all Frequencies for Natural
Sound
– 80dB PSRR (BTL, No Input Signal)
– >100dB (A weighted) SNR
– Click and Pop Free Startup
Pin compatible with TAS5630, TAS5615 and
TAS5613
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
– Mono Parallel Bridge Tied Load (PBTL)
– Stereo Bridge Tied Load (BTL)
– 2.1 Single Ended Stereo Pair and Bridge
Tied Load Subwoofer
Total Output Power at 10%THD+N
– 250W in Mono PBTL Configuration into 2Ω
– 125W per Channel in Stereo BTL
Configuration into 4Ω
Total Output Power in BTL configuration at
1%THD+N
– 130W Stereo into 3Ω
– 105W Stereo into 4Ω
– 70W Stereo into 6Ω
– 55W Stereo into 8Ω
>90% Efficient Power Stage With 60-mΩ
Output MOSFETs
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
EMI Compliant When Used With
Recommended System Design
Two Thermally Enhanced Package Options:
– PHD (64-Pin QFP)
– DKD (44-Pin PSOP3)
Home Theater Systems
AV Receivers
DVD/Blu-ray Receivers
Mini Combo System
Active Speakers and Subwoofers
DESCRIPTION
The TAS5611A is a high performance analog input
Class D amplifier with integrated closed loop
feedback technology (known as PurePath™ HD) with
the ability to drive up to 125W (1) Stereo into 4 to 8 Ω
Speakers from a single 32.5V supply.
PurePath™ HD technology enables traditional
AB-Amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class D
amplifiers.
Unlike traditional Class D amplifiers, the distortion
curve only increases once the output levels move into
clipping. PurePath™ HD Power PAD™
PurePath™ HD technology enables lower idle losses
making the device even more efficient.
TOTAL HARMONIC DISTORTION+NOISE
VS
OUTPUT POWER
10
4Ohm (6kHz)
THD+N - Total
tal Harmonic Distortion - %
1
4Ohm (1kHz)
1
0,1
0,01
TC = 75 C
CONFIG = BTL
0,001
0,01
1
100
PO - Output Power - W
(1)
Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
heatslug and the heat sink should be used to achieve high
output power levels.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath, Power PAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TAS5611A
SLAS709 – JUNE 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5611A is available in two thermally enhanced packages:
• 64-Pin QFP (PHD) Power Package
• 44-Pin PSOP3 package (DKD)
The package types contain heat slugs that are located on the top side of the device for convenient thermal
coupling to the heat sink.
DKD PACKAGE
(TOP VIEW)
PR
EV
IE
W
44 pins PACKAGE
(TOP VIEW)
CT
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IOSD
OTW
READY
M1
M2
M3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
OD
U
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
PSU_REF
VDD
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
PR
64-pins QFP package
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OTW2
CLIP
READY
M1
M2
M3
GND
GND
GVDD_C
GVDD_D
BST_D
OUT_D
OUT_D
PVDD_D
PVDD_D
GND_D
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IOSD
OTW1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDD
PSU_REF
NC
NC
NC
NC
GND
GND
GVDD_B
GVDD_A
BST_A
OUT_A
OUT_A
PVDD_A
PVDD_A
GND_A
PHD PACKAGE
(TOP VIEW)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
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SLAS709 – JUNE 2010
MODE SELECTION PINS
MODE PINS
ANALOG INPUT
OUTPUT
CONFIGURATION
0
Differential
2 × BTL
AD mode
1
—
—
Reserved
0
Differential
2 × BTL
BD mode
1 × BTL +2 ×SE
4 × SE
M3
M2
M1
0
0
0
0
0
1
0
1
1
Differential Single
Ended
1
0
0
Single Ended
DESCRIPTION
BD mode, BTL Differential
AD mode
INPUT_C
1
(1)
0
1
1
1
0
1
1
1
Differential
1 × PBTL
(1)
INPUT_D
(1)
0
0
AD mode
1
0
BD mode
Reserved
INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=GND).
PACKAGE HEAT DISSIPATION RATINGS (1)
PARAMETER
TAS5611APHD
TAS5611ADKD
RqJC (°C/W) – 2 BTL or 4 SE channels
3.2
2.1
RqJC (°C/W) – 1 BTL or 2 SE channel(s)
5.4
3.5
RqJC (°C/W) – 1 SE channel
Pad Area
(1)
(2)
(2)
7.9
5.1
64 mm2
80 mm2
JC is junction-to-case, CH is case-to-heat sink
RqCH is an important consideration. Assume a 2-mil thickness of thermal grease with a thermal conductivity of 2.5 W/mK between the
pad area and the heat sink and both channels active. The RqCH with this condition is 1.1°C/W for the PHD package and 0.44°C/W for
the DKD package.
Table 1. ORDERING INFORMATION (1)
(1)
TA
PACKAGE
DESCRIPTION
0°C–70°C
TAS5611APHD
64 pin HTQFP
0°C–70°C
TAS5611ADKD
44 pin PSOP3
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
VALUE
UNIT
VDD to GND
–0.3 to 13.2
V
GVDD to GND
–0.3 to 13.2
V
–0.3 to 53
V
PVDD_X to GND_X (2)
OUT_X to GND_X
(2)
–0.3 to 53
V
–0.3 to 66.2
V
BST_X to GVDD_X (2)
–0.3 to 53
V
VREG to GND
–0.3 to 4.2
V
GND_X to GND
–0.3 to 0.3
V
GND to AGND
–0.3 to 0.3
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO-, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF
to GND
–0.3 to 4.2
V
INPUT_X
–0.3 to 7
V
RESET, SD, OTW1, OTW2, CLIP, READY to GND
–0.3 to 7
V
BST_X to GND_X (2)
Continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Operating junction temperature range, TJ
Storage temperature, Tstg
Electrostatic discharge
(1)
(2)
(3)
Human body model
(3)
9
mA
0 to 150
°C
–40 to 150
°C
±2
kV
±500
V
(all pins)
Charged device model (3) (all pins)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Please ensure
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
16
32.5
34.1
V
GVDD_x
Supply for logic regulators and gate-drive circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
3.5
4
1.8
2
1.6
2
2.8
3
7
10
7
15
7
10
Nominal
350
400
450
AM1
300
340
380
AM2
260
300
335
RL(BTL)
RL(SE)
Output filter according to schematics in the
application information section
Load impedance
RL(PBTL)
RL(BTL)
Load impedance
Output filter according to schematics in the
application information section and add
Schottky diodes on all output nodes to GND_X,
ROC = 22kΩ
Output filter inductance
Minimum output inductance at IOC
LOUTPUT(BTL)
LOUTPUT(SE)
LOUTPUT(PBTL)
PWM frame rate selectable for AM interference
avoidance; 1% Resistor tolerance.
FPWM
Nominal; Master mode
Ω
mH
9.5
10
10.5
AM1; Master mode
19.8
20
20.2
AM2; Master mode
29.7
30
30.3
RFREQ_ADJ
PWM frame rate programming resistor
CPVDD
PVDD close decoupling capacitors
ROC
Over-current programming resistor
Resistor tolerance = 5%
ROC_LATCHED
Over-current programming resistor
Resistor tolerance = 5%
4
Ω
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kHz
kΩ
2.0
mF
22
30
kΩ
47
64
kΩ
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TAS5611A
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SLAS709 – JUNE 2010
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VFREQ_ADJ
Voltage on FREQ_ADJ pin for slave mode
operation
TJ
Junction temperature
Slave mode
TYP
MAX
UNIT
3.3
0
V
150
°C
PIN FUNCTIONS
PIN
NAME
FUNCTION (1)
DESCRIPTION
PHD NO.
DKD NO.
AGND
8
10
P
Analog ground
BST_A
54
43
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_A required.
BST_B
41
34
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_B required.
BST_C
40
33
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_C required.
BST_D
27
24
P
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_D required.
CLIP
18
—
O
Clipping warning; open drain; active low
C_STARTUP
3
5
O
Startup ramp requires a charging capacitor of 4.7 nF to GND in BTL mode
FREQ_ADJ
12
14
I
PWM frame rate programming pin requires resistor to GND
7, 23, 24, 57,
58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
30
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
—
P
Gate drive voltage supply requires 0.1 mF capacitor to GND_A
GVDD_B
56
—
P
Gate drive voltage supply requires 0.1 mF capacitor to GND_B
GVDD_C
25
—
P
Gate drive voltage supply requires 0.1 mF capacitor to GND_C
GVDD_D
26
—
P
Gate drive voltage supply requires 0.1 mF capacitor to GND_D
GVDD_AB
—
44
P
Gate drive voltage supply requires 0.22 mF capacitor to GND_A/GND_B
GVDD_CD
—
23
P
Gate drive voltage supply requires 0.22 mF capacitor to GND_C/GND_D
INPUT_A
4
6
I
Input signal for half bridge A
INPUT_B
5
7
I
Input signal for half bridge B
INPUT_C
10
12
I
Input signal for half bridge C
INPUT_D
11
13
I
Input signal for half bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59–62
–
—
No connect, pins may be grounded.
GND
OC_ADJ
1
3
O
Analog overcurrent programming pin requires 30kΩ resistor to GND.
OSC_IO+
13
15
I/O
Oscillator master/slave output/input.
OSC_IO–
14
16
I/O
Oscillator master/slave output/input.
OTW
—
18
O
Overtemperature warning signal, open drain, active low.
OTW1
16
—
O
Overtemperature warning signal, open drain, active low.
OTW2
17
—
O
Overtemperature warning signal, open drain, active low.
OUT_A
52, 53
39, 40
O
Output, half bridge A
OUT_B
44, 45
36
O
Output, half bridge B
OUT_C
36, 37
31
O
Output, half bridge C
OUT_D
28, 29
27, 28
O
Output, half bridge D
63
1
P
PSU Reference requires close decoupling of 330 pF to GND
PSU_REF
(1)
I = Input, O = Output, P = Power
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PIN FUNCTIONS (continued)
PIN
FUNCTION (1)
DESCRIPTION
41, 42
P
Power supply input for half bridge A requires close decoupling of 2uF capacitor
GND_A
42, 43
35
P
Power supply input for half bridge B requires close decoupling of 2uF capacitor
GND_B
PVDD_C
38, 39
32
P
Power supply input for half bridge C requires close decoupling of 2uF
capacitor GND_C
PVDD_D
30, 31
25, 26
P
Power supply input for half bridge D requires close decoupling of 2uF
capacitor GND_D
19
19
O
Normal operation; open drain; active high
NAME
PHD NO.
DKD NO.
PVDD_A
50, 51
PVDD_B
READY
RESET
2
4
I
Device reset Input; active low
SD
15
17
O
Shutdown signal, open drain, active low
VDD
64
2
P
Power supply for digital voltage regulator requires a 10-mF capacitor in parallel
with a 0.1-mF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of 1nF to GND
VREG
9
11
P
Digital regulator supply filter pin requires 0.1-mF capacitor to GND
6
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SLAS709 – JUNE 2010
TYPICAL SYSTEM BLOCK DIAGRAM
ANALOG_IN_B
OSC_IO-
BST_A
VI_CM
/CLIP
READY
BST_B
OUT_A
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
OSC_IO+
C_STARTUP
Oscillator
Synchronization
/OTW1, /OTW2, /OTW
/SD
/RESET
(2)
PSU_REF
Caps for
External
Filtering
&
Startup/Stop
System
microcontroller
or
Analog circuitry
Input
H-Bridge 1
INPUT_B
Output
H-Bridge 1
2
OUT_B
2
Hardwire
PWM Frame
Rate Adjust
&
Master/Slave
Mode
ANALOG_IN_D
nd
OUT_C
Output
H-Bridge 2
Input
H-Bridge 2
INPUT_D
2
OUT_D
8
PVDD
32.5V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
OC_ADJ
VREG
AGND
BST_D
Bootstrap
Caps
4
GVDD, VDD,
& VREG
Power Supply
Decoupling
Hardwire
OverCurrent
Limit
GND
GND
12V
8
VDD
M3
2 Order
L-C Output
Filter for
each
H-Bridge
BST_C
GND
M2
GND_A, B, C, D
PVDD_A, B, C, D
M1
GVDD_A, B, C, D
2
Hardwire
Mode
Control
nd
2 Order
L-C Output
Filter for
each
H-Bridge
2-CHANNEL
H -BRIDGE
BTL MODE
INPUT_C
Input DC
Blocking
Caps
ANALOG_IN_C
FREQ_ADJ
Bootstrap
Caps
GVDD (12V)/VDD (12V)
VAC
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FUNCTIONAL BLOCK DIAGRAM
/CLIP
READY
/OTW1
/OTW2
/SD
PROTECTION & I/O LOGIC
M1
M2
M3
/RESET
C_STARTUP
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
TEMP
SENSE
STARTUP
CONTROL
GVDD_A
GVDD _C
GVDD_B
OVER-LOAD
PROTECTION
GND
GVDD_D
CURRENT
SENSE
CB3C
OC_ADJ
OSC_SYNC_IO+
OSC_SYNC_IO-
4
OSCILLATOR
PPSC
FREQ_ADJ
4
4
PVDD_X
OUT_X
GND_X
GVDD_A
PWM
ACTIVITY
DETECTOR
4
PSU_REF
BST_A
PVDD_A
PVDD_X
PSU_FF
VI_CM
GND
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND_A
GVDD_B
INPUT_A
BST_B
ANALOG
LOOP FILTER
+
PVDD_B
+
ANALOG
LOOP FILTER
-
+
ANALOG COMPARATOR MUX
INPUT_C
ANALOG
LOOP FILTER
ANALOG INPUT MUX
INPUT_B
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND_B
GVDD_C
BST_C
PVDD_C
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_C
+
INPUT_D
ANALOG
LOOP FILTER
GND_C
-
GVDD_D
BST_D
PVDD_D
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND_D
8
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SLAS709 – JUNE 2010
AUDIO CHARACTERISTICS (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V,
GVDD_X = 12 V, RL = 4Ω, fS = 400kHz, ROC = 30kΩ, TC = 75°C, Output Filter: LDEM = 7mH, CDEM = 680nF,
MODE = 010, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
THD+N
MIN
165
RL = 4 Ω, 10% THD+N
125
RL = 3 Ω, 1% THD+N (add Schottky diodes on
all output nodes OUT_X to GND_X, ROC =
22kΩ)
130
RL = 4 Ω, 1% THD+N
105
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
|VOS|
Output offset voltage
Inputs AC coupled to GND
(1)
TYP MAX
RL = 3 Ω, 10% THD+N (add Schottky diodes on
all output nodes OUT_X to GND_X, ROC =
22kΩ)
UNIT
W
0.03%
168
20
mV
40
mV
SNR
Signal-to-noise ratio
A-weighted, AES17 filter
100
dB
DNR
Dynamic range
A-weighted, AES17 filter
100
dB
Pidle
Power dissipation due to Idle losses (IPVDD_X)
PO = 0, 4 channels switching (2)
1.3
W
(1)
(2)
SNR is calculated relative to 1% THD+N output level..
Actual system idle losses also are affected by core losses of output inductors.
AUDIO CHARACTERISTICS (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 32.5V,
GVDD_X = 12 V, RL = 2Ω, fS = 400kHz, ROC = 30kΩ, TC = 75°C, Output Filter: LDEM = 7 mH, CDEM = 1.5 mF,
MODE = 101-10, unless otherwise noted.
PARAMETER
PO
Power output per channel
TEST CONDITIONS
MIN
TYP MAX
RL = 2 Ω, 10% THD+N
250
RL = 3 Ω, 10% THD+N
165
RL = 4 Ω, 10% THD+N
125
RL = 2 Ω, 1% THD+N
210
RL = 3 Ω, 1% THD+N
135
RL = 4 Ω, 1% THD+N
UNIT
W
105
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted
170
mV
A-weighted
100
dB
A-weighted
100
dB
1.3
W
(1)
SNR
Signal to noise ratio
DNR
Dynamic range
Pidle
Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching (2)
(1)
(2)
0.03%
SNR is calculated relative to 1% THD-N output level.
Actual system idle losses are affected by core losses of output inductors.
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ELECTRICAL CHARACTERISTICS
PVDD_X = 32.5V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VI_CM
Analog comparator reference node, VI_CM
IVDD
VDD supply current
IGVDD_X
GVDD_x gate-supply current per half-bridge
IPVDD_X
Half-bridge supply current
VDD = 12 V
3
3.3
3.6
V
1.5
1.75
1.9
V
Operating, 50% duty cycle
20
Idle, reset mode
20
mA
50% duty cycle
10
Reset mode
1.5
50% duty cycle with recommended output
filter
10
mA
540
mA
33
kΩ
Reset mode, No switching
mA
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage swing
IIN
Maximum input current
G
Voltage Gain (VOUT/VIN)
READY = HIGH
7
V
1
21
mA
dB
OSCILLATOR
Nominal, Master Mode
fOSC_IO+
AM1, Master Mode
FPWM × 10
AM2, Master Mode
VIH
High level input voltage
VIL
Low level input voltage
3.5
4
3.0
3.4
4.5
3.8
2.6
3
3.35
1.86
MHz
V
1.45
V
60
100
mΩ
60
100
mΩ
OUTPUT-STAGE MOSFETs
RDS(on)
10
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
TJ = 25°C, excludes metallization
resistance, GVDD = 12 V
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 32.5V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,G
Vuvp,hyst
9.5
(1)
V
0.6
V
(1)
Overtemperature warning 1
95
100
105
°C
OTW2 (1)
Overtemperature warning 2
115
125
135
°C
OTW1
OTWhyst
(1)
25
Overtemperature error
OTE (1)
OTEhyst
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event.
(1)
OLPC
IOC
145
165
°C
OTE-OTW differential
30
°C
A reset needs to occur for SD to be released
following an OTE event
25
°C
Overload protection counter
fPWM = 400 kHz
Overcurrent limit protection
IOC_LATCHED
155
°C
Overcurrent limit protection
2.6
ms
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 30kΩ
12.6
A
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 22kΩ (add
Schottky diodes on all output nodes
OUT_X to GND_X)
16.3
A
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 64kΩ
12.6
A
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 47kΩ (add
Schottky diodes on all output nodes
OUT_X to GND_X)
16.3
A
IOCT
Overcurrent response time
Time from switching transition to flip-state
induced by overcurrent
150
ns
IPD
Internal pulldown resistor at output of each
half bridge
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode.
3
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
INPUT_X, M1, M2, M3, RESET
1.9
V
0.8
V
100
mA
kΩ
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistance, OTW1 to VREG,
OTW2 to VREG, SD to VREG
VOH
High level output voltage
VOL
Low level output voltage
IO = 4 mA
FANOUT
Device fanout OTW1, OTW2, SD, CLIP,
READY
No external pullup
(1)
Internal pullup resistor
External pullup of 4.7 kΩ to 5 V
20
26
32
3
3.3
3.6
4.5
V
5
200
30
500
mV
devices
Specified by design.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC+NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
200
TC = 75°C
TC = 75°C
THD+N = 10%
3W
4W
1
8W
0.1
4W
6W
8W
100
50
0.01
0.001
0.01
150
0.1
1
100
10
PO - Output Power - W
0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVDD - Supply Voltage - V
1000
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
vs
SUPPLY VOLTAGE
SYSTEM EFFICIENCY
vs
OUTPUT POWER
100
TC = 75°C
90
3W
80
4W
8W
6W
4W
70
6W
100
Efficiency - %
PO - Output Power - W
3W
150
6W
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
8W
50
60
50
40
30
20
TC = 25°C
THD+N = 10%
10
0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVDD - Supply Voltage - V
0
0
Figure 3.
12
50
100
150
200
250
2 Channel Output Power - W
300
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
OUTPUT POWER
OUTPUT POWER
vs
CASE TEMPERATURE
40
200
3W
TC = 25°C
THD+N = 10%
4W
150
PO - Output Power - W
Power Loss - W
30
4W
6W
20
8W
6W
100
8W
50
10
THD+N = 10%
0
0
50
100
150
200
250
2 Channel Output Power - W
0
20
300
40
50
60
70
80
TC - Case Temperature - °C
90
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
100
10
0
-40
THD+N - Total Harmonic Distortion - %
TC = 75°C,
VREF = 22.98 V,
Sample Rate = 48 kHz,
FFT Size = 16384
-20
Noise Amplitude - dB
30
-60
-80
-100
-120
4W
-140
RL = 4 W,
TC = 75°C,
Toroidal Output Inductors
1
0.1
1W
0.01
17.3 W (1/8 Power)
-160
0
5
10
15
f - Frequency - kHz
20
0.001
10
Figure 7.
100
1k
10k
f - Frequency - Hz
100k
Figure 8.
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
300
TC = 75°C
2W
TC = 75°C
THD+N = 10%
3W
2W
250
3W
4W
1
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
6W
8W
0.1
200
4W
6W
150
8W
100
0.01
50
0.001
0.01
0.1
1
100
10
PO - Output Power - W
0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PVDD - Supply Voltage - V
1000
Figure 9.
Figure 10.
OUTPUT POWER
vs
CASE TEMPERATURE
300
2W
250
PO - Output Power - W
3W
200
4W
150
6W
100
50
8W
THD+N = 10%
0
20
30
40
50
60
70
80
TC - Case Temperature - °C
90
100
Figure 11.
14
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APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 2 oz. (70mm) is recommended for use with the TAS5611A. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance).
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000mF, 50V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
DECOUPLING CAPACITOR RECOMMENDATIONS
To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, a quality decoupling capacitors should be used. In practice, X7R should be used in this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2mF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50V is required for use with a 32.5V power
supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices used for the TAS5611A.
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R_RIGHT_N
IN_RIGHT_P
IN_LEFT_N
IN_LEFT_P
/RESET
10uF
C16
10uF
C14
10uF
C12
10uF
C10
C17
100pF
C15
100pF
C13
100pF
C11
100pF
C18
100pF
READY
/CLIP
/OTW2
/OTW1
/SD
OSC_IO-
OSC_IO+
100R
R13
100R
R12
100R
R11
100R
R10
100R
R18
GND
VREG
GND
R19
47k
GND
GND
GND
GND
GND
10k
R21
100nF
C22
VREG
1nF
C21
4.7nF
30k
C20
R20
330pF
C23
GND
2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
GND
C26
100nF
/OTW1
/SD
OSC_IO-
OSC_IO+
FREQ_ADJ
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
GND
1
C25
10uF
64
VDD
/OTW2
17
63
PSU_REF
/CLIP
18
62
19
C30
100nF
GND
3.3R
61
NC
READY
60
NC
M1
GND
20
C31
100nF
VREG
C33
100nF
GND
GND GND
C32
100nF
3.3R
3.3R
R33
R32
C43
33nF
U10
TAS5611APHD
GVDD_C
59
NC
M2
21
NC
M3
58
GND
23
GND
24
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GND
57
GND
C40
33nF
C60
2uF
26
R31
GVDD_D
3.3R
BST_D
27
53
OUT_A
OUT_D
28
56
GVDD_B
54
BST_A
55
GVDD_A
OUT_A
OUT_D
29
52
30
51
PVDD_A
PVDD_D
50
PVDD_A
PVDD_D
49
GND_A
GND_D
31
16
C63
2uF
32
R30
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
C62
2uF
C61
2uF
GND
L13
7uH
7uH
L12
C42
33nF
C41
33nF
L11
7uH
L10
7uH
1000uF
C65
C53
680nF
C52
680nF
GND
C51
680nF
C50
680nF
C72
1nF
GND
C73
1nF
GND
1000uF
C66
C71
1nF
GND
C70
1nF
R73
3.3R
C77
10nF
C76
10nF
R72
3.3R
GND
GND
C68
47uF
63V
R71
3.3R
C75
10nF
C74
10nF
R70
3.3R
GND
C67
1000uF
GND
GND
C69
2.2uF
GND
C64
1000uF
GND
PVDD
GND
PVDD
GVDD/VDD (+12V)
OUT_RIGHT_P
+
-
GND
OUT_RIGHT_M
C78
10nF
R74
3.3R
OUT_LEFT_P
+
-
OUT_LEFT_M
PVDD
GVDD/VDD (+12V)
TAS5611A
SLAS709 – JUNE 2010
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Figure 12. Typical Differential Input BTL Application With BD Modulation Filters
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READY
/CLIP
/OTW2
/OTW1
/SD
OSC_IO-
OSC_IO+
IN_N
IN_P
/RESET
10uF
10uF
100R
100R
100R
GND
GND
GND
100pF
100pF
100pF
GND
VREG
47k
VREG
GND
GND
GND
GND
GND
10k
100nF
1nF
4.7nF
30k
VREG
GND
GND
1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
GND GND
100nF
/OTW1
/SD
OSC_IO-
OSC_IO+
FREQ_ADJ
INPUT_D
INPUT_C
VREG
AGND
GND
VI_CM
INPUT_B
INPUT_A
C_STARTUP
/RESET
OC_ADJ
330pF
10uF
64
VDD
/OTW2
17
63
PSU_REF
/CLIP
18
62
19
61
100nF
NC
READY
60
NC
20
NC
GND
100nF
GND
GND GND
59
100nF
VREG
GND
3.3R
33nF
GND GND
100nF
TAS5611APHD
NC
M3
22
M1
56
GVDD_B
GVDD_C
3.3R
3.3R
33nF
3.3R
GVDD_D
26
54
BST_A
BST_D
27
58
GND
GND
23
M2
21
55
GVDD_A
OUT_A
OUT_D
28
53
OUT_A
OUT_D
29
52
30
51
PVDD_A
PVDD_D
49
GND_A
GND_D
50
PVDD_A
PVDD_D
31
57
GND
GND
24
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32
VDD (+12V)
2uF
GND_D
GND_C
GND_C
OUT_C
OUT_C
PVDD_C
PVDD_C
BST_C
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND_B
GND_B
GND_A
GND
2uF
48
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
GND
2uF
2uF
GND
33nF
33nF
7uH
7uH
7uH
7uH
1000uF
63V
1000uF
63V
1uF
250V
GND
1uF
250V
1000uF
63V
1000uF
63V
GND
GND
1nF
100V
1nF
100V
GND
GND
47uF
63V
GND
3.3R
10nF
100V
10nF
100V
3.3R
GND
10nF
100V
+
GVDD (+12V)
PVDD
OUT_LEFT_P
GND
OUT_LEFT_M
GND
2.2uF
100V
3.3R
PVDD
GVDD (+12V)
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Figure 13. Typical Differential (2N) PBTL Application With BD Modulation Filters
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TAS5611A
2 mF
2 mF
30 kW
TAS5611ADKD
2 mF
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2 mF
SLAS709 – JUNE 2010
Figure 14. Typical Differential Input BTL Application With BD Modulation Filters DKD Package
18
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5611A needs only a 12V supply in addition to the (typical) 32.5V
power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage
analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and
output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12V source,
it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit
board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended
high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their
associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors
must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the powerstage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5611A reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output impedance voltage regulator. Likewise, the 32.5V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5611A is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5611A does not require a power-up sequence. The outputs of the H-bridges remain in a
high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not
specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.
Powering Down
The TAS5611A does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1
OTW2,
OTW
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
Overload (OLP) or undervoltage (UVP)
1
0
0
Junction temperature higher than 125°C (overtemperature warning)
1
0
1
Junction temperature higher than 100°C (overtemperature warning)
1
1
1
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
DESCRIPTION
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW
outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5611A contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5611A responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table.
BTL Mode
Local error in
A
B
C
D
PBTL Mode
Turns Off or in
A+B
C+D
Local error in
SE Mode
Turns Off or in
A
B
C
Local error in
A
A+B+C+D
D
B
C
D
Turns Off or in
A+B
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an over current after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup will not
activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges
are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts
switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no
shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The total
duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is
20
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SLAS709 – JUNE 2010
<15ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will not react to changes
applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released. A device
reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the
detection is not performed in SE mode. To make sure the PPSC detection system is not tripped, it is
recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options has individual overtemperature protection schemes.
PHD Package:
The TAS5611A PHD package option has a three-level temperature-protection system that asserts an active low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package:
The TAS5611A DKD package option has a two-level temperature-protection system that asserts an active low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5611A fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after
an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the
falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal
goes low, hence, filtering is needed if the signal is intended for audio muting in non microcontroller systems.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
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21
TAS5611A
SLAS709 – JUNE 2010
www.ti.com
OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band,
and can be selected by the value of the FREQ_ADJ resistor connected to GND in master mode.
For slave mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This will configure the
OSC_I/O pins as inputs and needs to be slaved from an external clock.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 12.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 15. Printed Circuit Board - Top Layer
22
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Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 16. Printed Circuit Board – Bottom Layer
SPACER
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23
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TAS5611APHD
PREVIEW
HTQFP
PHD
64
90
TBD
Call TI
Call TI
Samples Not Available
TAS5611APHDR
PREVIEW
HTQFP
PHD
64
1000
TBD
Call TI
Call TI
Samples Not Available
TAS5611PHD
ACTIVE
HTQFP
PHD
64
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-5A-260C-24 HR
Purchase Samples
TAS5611PHDR
ACTIVE
HTQFP
PHD
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-5A-260C-24 HR
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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