RF2153 2 CDMA/TDMA/PACS 1900MHZ 3V POWER AMPLIFIER Typical Applications • 3V TDMA PCS Handsets • 3V 1850-1910MHz CDMA PCS Handsets • Spread-Spectrum Systems • 3V 1750-1780MHz CDMA PCS Handsets • Commercial and Consumer Systems 2 POWER AMPLIFIERS • PACS Handsets and Base Stations Product Description The RF2153 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 3V CDMA and TDMA handheld digital equipment, spread-spectrum systems, and other applications in the 1750MHz to 1910 MHz band. The device is packaged in a compact 4mmx4mm (LCC). The device’s frequency response can be optimized for linear performance in the 1750MHz to 1910MHz band. 4.20 3.95 3.50 3.35 1.50 1.20 0.40 sq. 0.38 1 3.50 3.35 1.50 sq. 2.00 4.20 3.95 0.28 0.13 0.80 ALL SOLDER PAD TOLERANCES P0.05mm Optimum Technology Matching® Applied ! Si BJT GaAs MESFET SiGe HBT Si CMOS Package Style: MP16KO1A Features VCC2 VCC2 VCC 2F0 • Single 3V Supply VCC2 Si Bi-CMOS GaAs HBT 1 16 15 14 13 • 29dBm Linear Output Power • 30dB Linear Gain 3 11 RF OUT • 40% Linear Efficiency TDMA RFIN 4 10 RF OUT • On-board Power Down Mode 5 6 7 8 9 BIAS GND VCC1 VPD2 • 33% Linear Efficiency CDMA V MODE 12 RF OUT VPD1 2 GND1 GND2 Functional Block Diagram Rev A18 001114 Ordering Information RF2153 RF2153 PCBA CDMA/TDMA/PACS 1900MHz 3V Power Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-167 RF2153 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT ≤31dBm) Mode Voltage (VMODE) POWER AMPLIFIERS 2 Control Voltage (VPD) Input RF Power Operating Case Temperature Storage Temperature Parameter Rating Unit +8.0 +4.5 +3.5 VDC VDC VDC +3.5 +10 -30 to +110 -30 to +150 VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T=25°C, VCC =3.4V unless otherwise specified Overall - CDMA Usable Frequency Range Typical Frequency Range Small Signal Gain Linear Gain Second Harmonic (including second harmonic trap) Third Harmonic Fourth Harmonic Minimum Linear Output Power (CDMA or TDMA Modulation) Idle Current CDMA Linear Efficiency CDMA Adjacent Channel Power Rejection @ 1.25MHz Minimum Linear Output Power (CDMA Modulation) Input VSWR Output Load VSWR Turn On/Off Time 1750 30 26 26 1910 1750-1780 1850-1910 32 29 29 34 dB -35 dBc -40 -45 dBc dBc dBm 29 90 30 28 MHz MHz MHz dB 100 33 -46 2-168 Output Matching Network Tune Output Matching Network Tune VMODE =Low 0V to 0.5V VMODE =High 2.5V to 3.0V VMODE =High 2.5V to 3V POUT =29dBm, VCC =3.4V, VREG =2.8V 200 mA -44 dBc VMODE =>2.5V POUT =29dBm, VCC =3.4V, VREG =2.8V POUT =29dBm, VCC =3.4V, VREG =2.8V dBm VCC =3.0V, VREG =2.8V +29 < 2:1 10:1 No Damage. 40 µs Overall - TDMA Idle Current TDMA Linear Efficiency TDMA ACP @ 30kHz TDMA ALT @ 60kHz Condition 30 250 40 -29 -49 500 -28 -48 mA % dBc dBc T=25°C, VCC =3.4V unless otherwise specified VMODE =0V to 0.5V POUT =30dBm, VCC =3.4V, VREG =2.8V POUT =30dBm POUT =30dBm Rev A18 001114 RF2153 Parameter Specification Min. Typ. Max. Unit Condition Power Supply Spurious Noise Power Rev A18 001114 3.0 2.7 2.5 3.4 10 11 0 2.8 2.8 0 3:1 20:1 <-60 -136 4.5 13 10 0.2 2.9 0.5 V mA mA µA V V V V dBc dBm/Hz Total pins 6 and 8 Total pins 6, 7 and 8 VPD = low 2 POWER AMPLIFIERS Power Supply Voltage VPD Current VPD and VMODE Current Total Current (Power down) VPD “Low” Voltage VPD “High” Voltage MODE “High” Voltage MODE “Low” Voltage Stability R1=1kΩ R1=1kΩ Inband Outband @80MHz offset 2-169 RF2153 POWER AMPLIFIERS 2 Pin 1 Function VCC2 2 GND2 3 VCC1 4 RF IN Description Interface Schematic Power supply for second stage and interstage match. Pins 1, 15 and 16 should be connected by a common trace where the pins contact the printed circuit board. Ground for second stage. Keep traces physically short and connect immediately to ground plane for best performance. This ground should be isolated from the backside ground contact on top metal layer. Power supply for first stage and interstage match. VCC should be fed See pin 4. through a 1.5nH inductor terminated with a 15pF capacitor on the supply side. RF input. An external 15pF series capacitor is required as a DC block and also provides for an input VSWR of <2:1 typical. VCC1 RF IN From Bias Network GND1 5 GND1 6 VPD1 7 VMODE 8 VPD2 9 10 BIAS GND RF OUT 11 12 13 RF OUT RF OUT 2FO 14 VCC 15 16 Pkg Base VCC2 VCC2 GND 2-170 Ground for first stage. Keep traces physically short and connect immediately to ground plane for best performance. This ground should be isolated from the backside ground contact on top metal layer. Power Down control for first and second stages. When this pin is “low”, all first and second stage circuits are shut off. When this pin is 2.8V, all first stage circuits are operating normally. VPD1 requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. For full power operation, MODE is set low. VMODE will reduce the bias current by up to 50% when set HIGH. Large Signal Gain is reduced approximately 1.5dB at 29dBm POUT and Small Signal Gain is reduced approximately 6dB. An external series resistor is optional to limit the amount of current required by the VMODE pin. See pin 4. Power Down control for the third stage. When this pin is “low”, the third stage circuit is shut off. When this pin is 2.8V, the third stage circuit is operating normally. VPD requires a regulated 2.8V for the amplifier to operate properly over all specified temperature and voltage ranges. A dropping resistor from a higher regulated voltage may be used to provide the required 2.8V. A 15pF high frequency bypass capacitor is recommended. Requires a 15nH inductor. RF output and power supply for final stage. This is the unmatched colRF OUT lector output of the third stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 1850MHz to 1910MHz. From Bias It is important to select an inductor with very low DC resistance with a Network 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 12. See pin 10. Same as pin 12. See pin 10. Second harmonic trap. Keep traces physically short and connect immediately to ground plane. This ground should be isolated from backside ground contact. Supply for bias reference and control circuits. High frequency bypassing may be necessary. Same as pin 1. Same as pin 1. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. Rev A18 001114 RF2153 Application Schematic US - CDMA VCC 10 nF 8 pF 10 pF Bypassing for VCC 2 10 nF 15 pF 1st Interstage tuning to match input return loss 15 pF Ground for 2nd Harmonic Trap TL3 1 1.5 nH 16 15 14 13 2 12 3 11 4 10 12 nH* TL2 TL1 To match input return loss and vary gain 15 pF 150 Ω RF IN 6 5 POWER AMPLIFIERS 10 nF 2nd Interstage tuning for centering frequency response 7 8 47 Ω 4.7 pF** L4 15 nH 1 pF 15 pF RF OUT 2.2** Matching Network for optimum load impedance 9 27 Ω 15 pF Bypassing for VREG1 and VREG2 15 pF VREG 1 kΩ VMODE * High Q inductor (i.e., Coilcraft 0805HQ-series). **High Q capacitors (i.e., Johanson C-series). Tied together for optimum linearity Transmission Line Length CDMA (US) Rev A18 001114 TL1 TL2 TL3 20 mils 100 mils 20 mils 2-171 RF2153 Application Schematic Korea - CDMA VC POWER AMPLIFIERS 2 1 st In tersta g e tu ning to m a tch in p ut re turn lo ss 10 nF 10 nF 9 pF 10 pF B yp assin g fo r V C C 2 n d In te rstag e tu n in g for ce nte rin g fre qu e n cy re sp o nse C 10 nF 15 pF 15 pF G ro un d fo r 2 n d H a rm on ic T rap TL3 16 1 1.8 nH 15 14 13 2 12 3 11 4 10 12 nH * TL2 TL1 T o m a tch inp u t retu rn lo ss a n d vary g a in 15 pF 180 Ω R F IN 6 7 47 Ω 8 15 pF RF OUT 5.6 pF ** 2.2 pF ** M a tching N etw o rk fo r o p tim um loa d im p e da n ce 15 nH 5 1.0 pF + .25 pF 9 B ia s re tu rn 27 Ω 15 pF B yp assin g fo r V R E G 1 an d V R E G 2 15 pF VREG 1 kΩ VMODE * H ig h Q in d u cto r (i.e ., C o ilcraft 0 8 05 H Q -se ries). **H ig h Q ca p a cito rs (i.e ., Joh a n so n C -se ries). T ie d to g eth e r fo r o p tim u m lin e arity 2-172 T ransm ission Line Length TL1 TL2 TL3 C D M A (K orea) 30 m ils 100 m ils 30 m ils Rev A18 001114 RF2153 Application Schematic US - TDMA VCC 10 nF 15 pF 10 pF 2 10 nF 15 pF 15 pF Ground for 2nd Harmonic Trap TL3 16 1 1 nH 15 14 13 2 12 3 11 4 10 12 nH* TL1 To match input return loss and vary gain 15 pF 100 Ω RF IN 6 7 0Ω 15 pF 8 1 pF TL2 15 pF 4.7 pF** 1.8 pF** 15 nH 5 POWER AMPLIFIERS 1st Interstage tuning to match input return loss 10 nF Bypassing for VCC 2nd Interstage tuning for centering frequency response 9 RF OUT Matching Network for optimum load impedance Bias return 0Ω Bypassing for VREG1 and VREG2 15 pF VREG 4.7 kΩ VMODE * High Q inductor (i.e., Coilcraft 0805HQ-series). **High Q capacitors (i.e., Johanson C-series). Tied together for optimum linearity Transmission Line Length TDMA (US) Rev A18 001114 TL1 TL2 TL3 20 mils 160 mils 10 mils 2-173 RF2153 Evaluation Board Schematic US - CDMA C7 1 uF POWER AMPLIFIERS 2 C2 4.7 uF + P1-1 C12 10 nF C8 10 nF C11 8 pF C30 C26 10 nF C6 15 pF TL4 C4 15 pF TL3 16 1 L3 1.5 nH 15 14 2 13 L1* 12 TL1 J1 RF IN C5 15 pF 50 Ω µstrip R2 3 11 4 10 6 5 7 8 R3 39 Ω TL2 C1** C14 1 pF C3 15 pF C15** L4 15 nH 9 R4 0Ω 2153400 Rev. A P1 P1-1 C27 15 pF C13 15 pF C10 1 uF R1 1 kΩ P2-2 Transmission Line Length CDMA (US) 2-174 C30 (pF) 10 C1 (pF) 4.7 VCC 2 GND P2-1 1 VREG P2-2 2 VMODE * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C15 are High Q capacitors (i.e., Johanson C-series). Tied together for optimum linearity R2 (Ω) 150 1 P2 P2-1 Board CDMA (US) J2 RF OUT L1 (nH) 12 C15 (pF) 2.2 TL1 TL2 TL3 TL4 20 mils 100 mils 20 mils 100 mils or > 2.7 nH inductor Rev A18 001114 RF2153 Evaluation Board Schematic Korea - CDMA C2 4.7 uF + P1-1 C12 10 nF C8 10 nF C11 9 pF C30 2 C26 10 nF C6 15 pF TL4 POWER AMPLIFIERS C7 1 uF C4 15 pF TL3 16 1 L3 1.5 nH 15 14 2 13 12 TL1 50 Ω µstrip J1 RF IN C5 15 pF R2 C14 1.5 pF L1* 3 11 4 10 6 5 7 8 R3 39 Ω TL2 C1** C15** L4 15 nH 2153401 Rev.- P1 P1-1 C13 15 pF C10 1 uF R1 1 kΩ P2-2 Transmission Line Length CDMA (Korea) Rev A18 001114 VCC 2 GND P2-1 1 VREG P2-2 2 VMODE * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C15 are High Q capacitors (i.e., Johanson C-series). Tied together for optimum linearity CDMA (Korea) 1 P2 P2-1 Board J2 RF OUT 9 R4 0Ω C27 15 pF C3 15 pF R2 (Ω) C30 (pF) C1 (pF) L1 (nH) C15 (pF) 180 11 5.6 12 2.2 TL1 TL2 TL3 TL4 30 mils 100 mils 30 mils 100 mils or > 2.7 nH inductor 2-175 RF2153 Evaluation Board Schematic US - TDMA C7 1 uF POWER AMPLIFIERS 2 C2 4.7 uF + P1-1 C12 10 nF C8 10 nF C11 15 pF C30 C26 10 nF C6 15 pF C4 15 pF TL3 16 1 L3 1 nH 15 14 2 13 L1* 12 TL1 J1 RF IN C5 15 pF 50 Ω µstrip R2 3 11 4 10 6 5 7 8 R3 0Ω TL2 C1** C3 15 pF J2 RF OUT C15** L4 15 nH 9 R4 0Ω 2153402A P1 P1-1 C27 15 pF C14 1 pF C13 15 pF 1 VCC 2 GND P2 P2-1 R1 4.7 kΩ P2-2 R2 (Ω) 100 C30 (pF) 10 C1 (pF) 4.7 L1 (nH) 12 C15 (pF) 1.8 Transmission Line Length TDMA (US) 2-176 1 VREG P2-2 2 VMODE * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C15 are High Q capacitors (i.e., Johanson C-series). Tied together for optimum linearity Board TDMA (US) P2-1 TL1 TL2 TL3 20 mils 160 mils 10 mils Rev A18 001114 RF2153 Evaluation Board Layout US - CDMA Board Size 2.0" x 2.0" Board Thickness 0.031”, Board Material FR-4 POWER AMPLIFIERS 2 Evaluation Board Layout Korea - CDMA Rev A18 001114 2-177 RF2153 Evaluation Board Layout US - TDMA POWER AMPLIFIERS 2 2-178 Rev A18 001114