RF2192 Preliminary 2 3V 900MHZ LINEAR POWER AMPLIFIER Typical Applications • 3V TDMA/GAIT Cellular Handsets • 3V JCDMA Cellular Handsets • Spread-Spectrum Systems • 3V CDMA2000 Cellular Handsets • Portable Battery-Powered Equipment Product Description 2 2 0.45 0.28 3.75 The RF2192 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in dual-mode 3V CDMA/AMPS and CDMA2000 handheld digital cellular equipment, spread-spectrum systems, and other applications in the 800MHz to 960MHz band. The RF2192 has a low power mode to extend battery life under low output power conditions. The device is packaged in a 16 pin, 4mmx4mm leadless chip carrier. 1 0.80 TYP 0.75 0.50 3.75 + 1 1.60 4.00 12° 1.50 SQ 3 INDEX AREA 3.20 0.75 0.65 4.00 1.00 0.90 0.05 0.00 NOTES: 1 Shaded Pin is Lead 1. 2 Dimensions in mm. Dimension applies to plated terminal and is measured 0.10 mm and 0.25 mm from terminal tip. The terminal #1 identifier and terminal numbering conv 3 shall conform to JESD 95-1 SPP-012. Details of termin identifier are optional, but must be located within the z indicated. The identifier may be either a mold or marke feature. 4 5 Optimum Technology Matching® Applied ü Si BJT GaAs MESFET SiGe HBT Si CMOS Package Style: LCC, 16-Pin, 4x4 Features VCC1 VCC1 VCC BIAS 2F0 • Single 3V Supply GND Si Bi-CMOS GaAs HBT Pins 1 and 9 are fused. Package Warpage: 0.05 max. 1 16 15 14 13 GND 2 12 RF OUT GND 3 11 RF OUT RF IN 4 10 RF OUT • 29dBm Linear Output Power • 37% Linear Efficiency • Low Power Mode • 45 mA idle current 9 GND 8 BIAS GND 7 VREG2 6 VMODE VREG1 5 Functional Block Diagram Rev A1 010830 • 47% Peak Efficiency 31dBm Output Ordering Information RF2192 RF2192 PCBA 3V 900MHz Linear Power Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-203 POWER AMPLIFIERS • 3V CDMA/AMPS Cellular Handsets RF2192 Preliminary Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT ≤31dBm) Mode Voltage (VMODE) POWER AMPLIFIERS 2 Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Moisture Sensitivity Parameter Rating Unit +8.0 +5.2 +4.2 VDC VDC VDC +3.0 VDC +10 dBm -30 to +110 °C -30 to +150 °C Modified JEDEC Level 2 Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Case T=25°C, VCC =3.4V, VREG = 2.85V, VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) High Power State (VMODE Low) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection 824 27 849 30 -33 <-60 29 37 -48 -58 2:1 Input VSWR Output VSWR MHz dB dBc dBc dBm -44 % dBc POUT =29dBm ACPR @885kHz -56 dBc ACPR @1980kHz 10:1 6:1 Noise Power -133 dBm/Hz Low Power State (VMODE High) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Max ICC Adjacent Channel Power Rejection Input VSWR Output VSWR 2-204 Condition 824 19 16 849 22 -33 <-60 20 150 -48 <-60 2:1 No damage. No oscillations. >-70dBc At 45MHz offset Case T=25 °C, VCC =3.4V, VREG =2.85V, VMODE =1.8V to 3V, Freq=824MHz to 849MHz (unless otherwise specified) MHz dB dBc dBc dBm -46 mA dBc POUT =+16dBm (all currents included) ACPR @885kHz -58 dBc ACPR @1980kHz 10:1 6:1 No damage. No oscillations. >-70dBc Rev A1 010830 RF2192 Preliminary Specification Min. Typ. Max. Unit Case T=25oC, VCC =3.4V, VREG =2.85V. VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) High Power State CDMA 2000 1x (VMODE LOW) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 824 849 29 26.5 MHz dB dBm Efficiency Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection -47 dBc <-60 dBc ACPR@ 1.98MHz dBm 4.5dB Peak Average Ratio at CCDF 1% -47 dBc ACPR@ 885kHz <-60 dBc 29 ACPR@ 1.98MHz Case T=25oC, VCC =3.4V, VREG =2.85V. VMODE =1.8V to 3V, Freq=824MHz to 849MHz 824 16 16 22 849 MHz dB 20 dBm 5.4dB Peak to Average Ratio at CCDF 1% -48 dBc ACPR@ 885kHz <-85 15 dBc % ACPR@ 1.98MHz POUT =20dBm 20 dBm 4.5dB Peak to Average Ratio at CCDF 1% <-50 dBc ACPR@ 885kHz <-65 dBc ACPR@ 1.98MHz Case T=25°C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) FM Mode Frequency Range Gain Second Harmonic Third Harmonic Max CW Output Power Total Efficiency (AMPS mode) Input VSWR Output VSWR 2 2.5dB Backoff included in IS98D CCDF 1% 5.4dB Peak Average Ratio at CCDF 1% ACPR@ 885kHz Low Power State CDMA 2000 1x (VMODE HIGH) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Condition 824 31 849 30 -33 <-60 32 47 2:1 10:1 6:1 MHz dB dBc dBc dBm % POUT =31dBm (room temperature) No damage. No oscillations. >-70dBc Note: DCCH: Dedicated Control Channel FCH: Fundamental Channel CCDF: Complementary Cumulative Distribution Function Rev A1 010830 2-205 POWER AMPLIFIERS Parameter RF2192 Parameter Preliminary Specification Min. Typ. Max. Unit Condition DC Supply Supply Voltage 3.0 Quiescent Current POWER AMPLIFIERS 2 3.4 160 45 VREG Current VMODE Current Turn On/Off Time Total Current (Power Down) VREG “Low” Voltage VREG “High” Voltage VMODE “Low” Voltage VMODE “High” Voltage 2-206 0 2.75 0 1.8 2.85 2.85 4.2 V 70 10 1 <40 mA mA mA mA µs 10 0.5 2.95 0.5 3.0 µA V V V V The maximum power out for VCC =3.0V is 28dBm. VMODE =Low VMODE =High Time between VREG turned on and PA reaching full power. Turn on/off time can be reduced by lowering the bypass capacitor value on the VREG line. VREG =Low Rev A1 010830 RF2192 Preliminary Function GND GND GND RF IN Description Interface Schematic Ground connection. Ground connection. Ground connection. RF input. An external 100pF series capacitor is required as a DC block. In addition, shunt inductor and series capacitor are required to provide 2:1VSWR. VCC1 2 100 pF RF IN From Bias GND1 Stages 5 VREG1 6 VMODE 7 VREG2 8 9 10 BIAS GND GND RF OUT 11 12 13 RF OUT RF OUT 2FO 14 VCC BIAS 15 16 Pkg Base VCC1 VCC1 GND Rev A1 010830 Power Down control for first stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, the driver and final stage are dynamically scaled to reduce the device size and as a result to reduce the idle current. Power Down control for the second stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). Bias circuitry ground. See application schematic. Ground connection. RF output and power supply for final stage. This is the unmatched collector output of the second stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 824MHz to 849MHz. It is important to select an inductor with very low DC resistance with a 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 10. RF OUT From Bias Stages See pin 10. Same as pin 10. Harmonic trap. This pin connects to the RF output but is used for providing a low impedance to the second harmonic of the operating frequency. An inductor or transmission line resonating with an on chip capacitor at 2fo is required at this pin. Power supply for bias circuitry. A 100pF high frequency bypass capacitor is recommended. Power supply for first stage. Same as Pin 15. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. 2-207 POWER AMPLIFIERS Pin 1 2 3 4 RF2192 Preliminary Evaluation Board Schematic US - CDMA (Download Bill of Materials from www.rfmd.com.) C2 4.7 uF VCC 2 POWER AMPLIFIERS C25 4.7 µF C6 100 pF C30 C28 10 nF C4 100 pF L5 1 nH TL3 TL5 1 C9 100 pF J1 RF IN L2 5.6 nH 15 14 2 R2 510 Ω C5 100 pF 16 C24 12 pF 13 12 3 11 4 10 5 6 7 8 TL2 C1** C3 100 pF J4 RF OUT C14** * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). R3 0Ω L4 39 nH R4 0Ω Board CDMA (US) C13 100 pF VREG VMODE TL1 C17 2.4 pF 9 C27 100 pF C26 4.7 µF L1* Transmission Line Length CDMA (US) C30 (pF) C1 (pF) L1 (nH) C14 (pF) 100 9.1 20 9.1 TL1 TL2 TL3 TL5 15 mils 350 mils 105 mils 85 mils R1 0Ω 2-208 Rev A1 010830 RF2192 Preliminary Evaluation Board Layout 2.0” x 2.0” Board Thickness 0.031”, Board Material FR-4, Multi-Layer, Ground Plane at 0.015” POWER AMPLIFIERS 2 Rev A1 010830 2-209 RF2192 Preliminary POWER AMPLIFIERS 2 2-210 Rev A1 010830