RF2668 Preliminary 5 CDMA/FM TRANSMIT MODULATOR, IF AGC, AND UPCONVERTER WITH INTEGRATED PLL Typical Applications • CDMA/FM Cellular and PCS Systems • Wireless Local Loop Systems • Tri-Mode/Dual-Band CDMA Applications • Spread-Spectrum Cordless Phones • W-CDMA Systems • High Speed Data Modems Product Description 9.00 + 0.20 sq. NC 1 CE TX_EN MIX_EN VCO_EN PLLON PLLISET VREFPLL OSCREF SET1 Si CMOS MODE SiGe HBT VCC3 GaAs MESFET BG üSi Bi-CMOS GaAs HBT 48 47 46 45 44 43 42 41 40 39 38 37 Band Gap Rel 5 0.50 7.00 + 0.10 sq. 0.22 + 0.05 1.40 + 0.05 7° MAX 0° MIN 0.60 + 0.15 0.10 Optimum Technology Matching® Applied Si BJT 0.35 0.25 MODULATORS AND UPCONVERTERS The RF2668 is an integrated complete quadrature modulator, IF AGC amplifier, upconverter, and PLL, designed for the transmit section of dual-mode CDMA/FM cellular, PCS, and tri-mode CDMA applications. It is designed to modulate baseband I and Q signals, amplify the resulting IF signals while providing 95dB of gain control range, and perform the final upconversion to UHF. Noise Figure, IP3, and other specifications are designed to be compatible with the IS-98 Interim Standard. This circuit is designed as part of RFMD’s newest CDMA chipset, which also includes the RF2667 CDMA/FM Receive IF AGC and Demodulator. The IC is manufactured on an advanced 18GHz FT Silicon Bipolar process, and is supplied in a 48-lead plastic LQFP package. 0.127 Package Style: LQFP-48_7x7 Features • Supports Tri-Mode Operation • Digitally Controlled Power Down Modes 36 SET2 Bias Supply NC 2 35 PLLVCC /R RFOUT 3 VCC4 4 /N Lock Detect 34 PLLGND Charge Pump 33 LD LO2+ 5 32 DO LO2- 6 31 VCO+ GND2 7 30 VCO- GND2 8 29 LO1+ MIX_DEC 9 • 2.7V to 3.3V Operation • Digital First LO Quadrature Divider • Double-Balanced UHF Upconvert Mixer • IF AGC Amp with 95dB Gain Control 28 LO1- Σ MIX IN+ 10 27 VCC1 Quad /2 MIX IN- 11 26 VCO_ISET NC 12 14 15 16 17 18 19 20 21 22 23 24 NC MOD OUT- MOD OUT+ GND1 AGC_DEC VGC VCC2 GND1 QSIG QREF IREF ISIG 25 NC 13 Functional Block Diagram Rev B4 010423 Ordering Information RF2668 CDMA/FM Transmit Modulator, IF AGC, and Upconverter with Integrated PLL RF2668 PCBA-PCS/CEL Fully Assembled Evaluation Boards RF2668 PCBA-DO Fully Assembled Evaluation Boards RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 5-71 RF2668 Preliminary Absolute Maximum Ratings Parameter Supply Voltage Power Down Voltage (VPD) I and Q Levels, per pin LO1 Level, balanced Operating Ambient Temperature Storage Temperature Parameter MODULATORS AND UPCONVERTERS 5 Rating Unit -0.5 to +5 -0.5 to VCC + 0.7 1 +6 -40 to +85 -40 to +150 VDC V VPP dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit I/Q Modulator & AGC I/Q Input Frequency Range I/Q Input Impedance I/Q Input Reference Level LO1/FM Frequency Range LO1/FM Input Level LO1/FM Input Impedance Sideband Suppression Carrier Suppression Max Output, FM Mode Max Output, CDMA Mode 0 to 20 80 1.3 0 -15 35 40 +2.5 -3 -2 Min Output, CDMA Mode Output Power Accuracy Adjacent Channel Power Rejection @ 885kHz Adjacent Channel Power Rejection @ 1.98MHz Output Noise Power Output Impedance Current Consumption 5-72 -10 200 40 27 50 30 +5 0 0 -95 -3 -2 800 -5 -89 +3 +2 MHz kΩ VDC MHz dBm Ω dBc dBc dBc dBc dBm dBm dBm dBm -60 dB dB dBc -69 dBc -117 200 40 -111 dBm/Hz Ω mA Condition T=25 °C, VCC =3.0V, ZLOAD =200Ω, LO1=-10dBm @ 260MHz, IF=130MHz, I SIG=Q SIG=300mVPP, RF Output externally matched Balanced Balanced Per Pin Balanced I/Q Amplitude adjusted to within ±20mV Unadjusted I/Q DC Offset adjusted to within ±20mV Unadjusted VGC =2.4VDC, T=-20°C to +85°C VGC =2.4VDC, T=-20°C to +85°C, IS-95A CDMA Modulation ISIG=QSIQ=300mVpp@ 100kHz VGC =0.3VDC, T=-20°C to +85°C, IS-95A CDMA Modulation T=-20 to +85 °C, Ref=25 °C 1.4V≤GC≤ 2.5 IS-95A CDMA Modulation POUT = -5dBm IS-95A CDMA Modulation POUT = -5dBm POUT = -1dBm, T=-20°C to +85°C Balanced I/Q modulator and AGC only. Rev B4 010423 RF2668 Preliminary Specification Min. Typ. Max. Unit UHF Upconverter General IF Input Impedance IF Input Frequency Range LO2 Input Impedance LO2 Input Level LO2 Input Frequency Range RF to LO2 Isolation LO Input VSWR Current Consumption Cellular Conversion Gain Noise Figure (SSB) Output IP3 Output externally matched 200 0 -6 400 50 -3 0 2.5 30 <2:1 24 -1.5 Ω MHz Ω dBm GHz dB mA -0.5 15 +13 dB dB dBm RF Output VSWR W-CDMA Conversion Gain <2:1 -1.5 dB Noise Figure Output IP3 TBD 10 dB dBm RF Output VSWR <2:1 Dual Output Cellular Conversion Gain Noise Figure Output IP3 RF Output VSWR PCS Conversion Gain Noise Figure Output IP3 RF Output VSWR -1.5 -0.5 15 12.5 -1.0 15 10.5 50Ω UHF upconverter only. RFOUT =830MHz RFOUT =830MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =830MHz, LO2=960MHz@ -3dBm RFOUT = 830MHz RFOUT =1950MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =1950MHz, LO2=1570MHz @-3dBm RFOUT =1950MHz. See note on eval board schematic. dB dB dBm RFOUT =1880MHz RFOUT =1880MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =1880MHz, LO2=1750MHz @-3dBm RFOUT =1880MHz PLL locked with Loop BW =5kHz, Tank Values: 39nH and SMV1234 varactor. <1.5:2 -110 1 Single Ended RFOUT =830MHz RFOUT =830MHz PIN =-15dBm per tone, 200kHz tone separation, RFOUT =830MHz, LO2=960MHz@-3dBm RFOUT =830MHz <1.5:1 -1.5 Balanced dB dB dBm VCO Phase Noise @ 100kHz Current Consumption Condition dBc/Hz mA PLL Charge Pump Current TCXO Input Level 0.8 µA VPP PLL Lock Time Current Consumption 4/Loop BW 4 s mA Rev B4 010423 100 PLL only. 5-73 5 MODULATORS AND UPCONVERTERS Parameter RF2668 Parameter Preliminary Specification Min. Typ. Max. Unit Condition Power Supply Supply Voltage Current Consumption Power Down Current VPD HIGH Voltage VPD LOW Voltage 2.7 3.0 69 <10 3.3 VCC-0.3 0.3 V mA µA V V Total device current. PLL Settings MODULATORS AND UPCONVERTERS 5 Application LO Frequency, MHz Crystal, MHz Reference Divider Phase Detector Frequency, kHz Prescaler Swallow Counter (A) Fixed Divider (N) Net N in VCO Path SET1 SET2 5-74 Japan 333.7 19.2 192 100 32/33 9 104 3337 VCC GND Japan 333.7 19.8 198 100 32/33 9 104 3337 GND VCC US/Korea 260.76 19.68 252 78.09524 32/33 11 104 3339 GND GND IF Frequency =LO Frequency/2 Rev B4 010423 RF2668 Preliminary Pin 1 2 3 Function NC NC RF OUT Description Interface Schematic Not connected. Not connected. RF output pin. An external shunt inductor to VCC plus a series blocking/ matching capacitor are required for 50Ω output. VCC4 300 Ω RF OUT VCC4 5 LO2+ 6 LO2- 7 GND2 8 9 GND2 MIX_DEC 10 11 MIX IN+ MIX IN- 12 13 14 15 16 NC NC MOD OUT- MOD OUT+ GND1 Rev B4 010423 Supply for the mixer stage only. The supply for the mixer is separated to maximize IF to RF isolations and reduce the carrier leakage. A 10nF external bypass capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. One half of the balanced mixer LO2 input. In single-ended applications, the other half of the input, LO2- is AC grounded. This is a 50Ω impedance port. This pin is NOT internally DC-blocked. An external blocking capacitor (100pF recommended) must be provided if the pin is connected to a device with DC present. One half of the balance mixer LO2 input. In single ended applications, this pin is AC grounded with a 100pF capacitor. Ground connection for the mixer stage. For best performance, keep traces physically short and connect immediately to ground plane. Same as pin 7. Current Mirror decoupling pin. A 1000pF external capacitor is required to bypass this pin. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 11, except complementary input. One half of the 200Ω balanced impedance input to the mixer stage. This pin is NOT internally DC-blocked. An external blocking capacitor (1000pF recommended) must be provided if the pin is connected to a device with DC present. If no IF filter is needed this pin may be connected to MOD OUT+ through a DC blocking capacitor. An appropriate matching network may be needed if an IF filter is used. BIAS BIAS 50 Ω 5 50 Ω LO2+ LO2- See pin 5. See pin 11. BIAS BIAS 100 Ω 100 Ω MIX IN- MIX IN+ Not connected. Not connected. One half of the balanced AGC output port. The impedance of this port is 200Ω balanced. If no filtering is required, this pin can be connected to the MIX IN- pin through a DC blocking capacitor. This pin requires an inductor to VCC to achieve full dynamic range. In order to maximize gain, this inductor should be a high-Q type and should be parallel resonated out with a capacitor (see application schematic). This pin is NOT DC-blocked. A blocking capacitor of 2200pF is needed when this pin is connected to a DC path. An appropriate matching network may be needed if an IF filter is used. Same as pin 14, except complementary output. VCC3 100 Ω VCC3 100 Ω MOD OUTMOD OUT+ See pin 14. Ground connection for all baseband circuits including bandgap, AGC, flip-flop, modulator and FM amp. For best performance, keep traces physically short and connect immediately to ground plane. 5-75 MODULATORS AND UPCONVERTERS 4 RF2668 Pin 17 Function AGC_DEC 18 VGC Preliminary Description AGC decoupling pin. An external bypass capacitor of 1nF capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Analog gain control for AGC amplifiers. Valid control voltage ranges are from 0.3VDC to 2.4VDC. The gain range for the AGC is 95dB. These voltages are valid ONLY for a 39kΩ source impedance. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Interface Schematic BIAS 21 kΩ GC 40 kΩ 19 VCC2 20 21 GND1 Q SIG MODULATORS AND UPCONVERTERS 5 Supply for the modulator stage only. A 10nF external bypass capacitor is required and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 16. Baseband input to the Q mixer. This pin is DC-coupled. The DC level of 1.3V must be supplied to this pin to bias the transistor. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Q SIG 22 Q REF 23 I REF See pin 24. Reference voltage for the I mixer. This voltage should be the same as the DC voltage supplied to the I SIG pin. For maximum carrier suppression, DC voltage on this pin relative to the I SIG DC voltage may be adjusted. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. 24 I SIG Baseband input to the I mixer. This pin is DC coupled. The DC level of 1.3V must be supplied to this pin to bias the transistor. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. 25 26 NC VCO_ISET 27 VCC1 28 LO1- 5-76 Reference voltage for the Q mixer. This voltage should be the same as the DC voltage supplied to the Q SIG pin. For maximum carrier suppression, DC voltage on this pin relative to the Q SIG DC voltage may be adjusted. Input impedance of this pin is 50kΩ minimum. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Q REF See pin 21. I SIG I REF Not connected. An external resistor of 47kΩ is used to set the VCO current for minimum phase noise. Supply Voltage for the LO1 flip-flop and limiting amp only. This supply is isolated to minimize the carrier leakage. A 1nF external bypass capacitor is required, and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. External LO input to modulator. Controlled by VCO_EN signal. Logic See pin 29. low is internal VCO, while logic high is external VCO. Rev B4 010423 RF2668 Preliminary Pin 29 Function LO1+ Description Interface Schematic External LO input to modulator. Controlled by VCO_EN signal. Logic low is internal VCO, while logic high is external VCO. 1 kΩ LO1+, FM+ VCOVCO+ 32 DO 33 LD 34 PLLGND 35 PLLVCC 36 37 38 39 40 SET2 SET1 OSCREF VREFPLL PLLISET 41 42 43 PLLON VCO_EN MIX_EN 44 TX_EN 45 CE 46 MODE Rev B4 010423 See VCO+ description. This port is used to supply DC voltage to the VCO as well as to tune the center frequency of the VCO. Equal value inductors should be connected to this pin and pin 30 although a small imbalance can be used to tune in the proper frequency range. Output of the charge pump, and input to the VCO control. An RC network from this pin to ground is used to establish the PLL bandwidth. Lock detector output for synthesizer. Requires external transistor to provide hysteresis and inversion of signal. See Application circuit. Ground for synthesizer. For best performance, keep traces physically short and connect immediately to ground plane. Supply for the PLLVCC only. A 10nF external bypass capacitor is required and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. PLL Setting (Divider) pin. See the PLL settings table. 5 MODULATORS AND UPCONVERTERS 30 31 Same as pin 36. TCXO reference input for synthesizer. Bypass pin for the synthesizer reference voltage. Current setting pin for synthesizer charge pump. For normal operation, a 390Ω resistor to ground should be used to set the current. Synthesizer Enable pin. See pin 45. VCO Enable pin. Switches between internal and external VCO. See pin 45. Power down control for mixer only. When connected to logic “high” (>VCC -0.3) the mixer circuits are operating; when connected to ground (≤0.3V), the mixer is turned off but all other circuits are operating. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. 1 kΩ MIX EN 450 Ω Shuts down the entire TX path. VCO is still active when TX disabled. Logic high (>VCC -0.3) for TX Enable. Power down control for overall circuit. When logic “high” (≥VCC -0.3V), all circuits are operating; when logic “low” (≤0.3V), all circuits are turned off. The input impedance of this pin is >10kΩ. A DC voltage less than or equal to the maximum allowable Vcc may be applied to this pin when no voltage is applied to the VCC pins. Selects between CDMA and FM mode. This is a digitally controlled input. A logic “high” (≥VCC -0.3VDC) selects CDMA mode. A logic “low” (<0.3VDC) selects FM mode. In FM mode, this switch enables the FM amplifier and turns off the I&Q modulator. The impedance on this pin is 30kΩ. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. 10 kΩ CE BIAS 60 kΩ MODE 60 kΩ 5-77 RF2668 Pin 47 Function VCC3 48 BG OUT Preliminary Description Interface Schematic Supply voltage for the AGC and the Bandgap circuitry. A 1nF external bypass capacitor is required and an additional 0.1µF will be required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Bandgap voltage reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 1nF external bypass capacitor is required. MODULATORS AND UPCONVERTERS 5 5-78 Rev B4 010423 RF2668 Preliminary VCC3 MODE CE TX_EN MIX_EN VCO_EN PLLON PLLISET VREFPLL OSCREF SET1 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 36 SET2 NC 2 35 PLLVCC RFOUT 3 34 PLLGND VCC4 4 33 LD LO2+ 5 32 DO LO2- 6 31 VCO+ GND2 7 30 VCO- GND2 8 29 LO1+ MIX_DEC 9 28 LO1- MIX IN+ 10 27 VCC1 MIX IN- 11 26 VCO_ISET Rev B4 010423 13 14 15 16 17 18 19 20 21 22 23 24 MOD OUT- MOD OUT+ GND1 AGC_DEC VGC VCC2 GND1 QSIG QREF IREF ISIG 25 NC NC NC 12 5 MODULATORS AND UPCONVERTERS BG Pin-Out 5-79 RF2668 Preliminary Application Schematic Single- or Dual-Mode Operation VCC MODE CE AGC MIX EN VCO EN PLL ON 270 Ω 1 nF OSC REF 10 nF SET1 1 nF 10 nF VCC 12 nH 1 SET2 48 47 46 Band Gap Rel 45 44 43 42 41 40 VCC 10 nF 36 35 /R 3 4 MODULATORS AND UPCONVERTERS 37 Bias Supply 10 nF 5 38 2 2 pF RF OUT 39 /N Lock Detect 34 Charge Pump 33 5 32 100 pF 6 31 100 pF 7 30 8 29 9 28 1 nF 2.2 nF LD 36 kΩ 220 pF 33 pF VCC LO2 D1 DO 39 nH 10 nF ** 39 nH ** 1 nF 1 nF Σ MIX IN+ 10 MIX IN- 11 26 12 25 14 15 16 17 18 19 20 21 22 23 DO 200 Ω 3.9 kΩ LO1+ LO1- 27 Quad /2 VCC 1 nF 13 VTUNE 24 10 nF 47 kΩ VCC VCC 10 nF L1* 1 nF 10 nF 10 nF L2* MOD OUT1 nF 39 kΩ MOD OUT+ *L1 and L2 are the bias choke inductor. 5-80 **Denotes components not normally populated. VGC OSIG REF ISIG Rev B4 010423 RF2668 Preliminary Application Schematic Tri-Mode/Dual-Band Operation VCC MODE CE AGC MIX EN VCO EN PLL ON 270 Ω 1 nF OSC REF 10 nF SET1 4.7 pF VCC 1 nF 12 nH 4.7 pF 8 nH 1 SET2 48 47 46 Band Gap Rel RF OUT (CELL) 45 44 43 42 41 40 39 38 37 36 Bias Supply 2 8.2 nH 35 /R 0.5 pF RF OUT (PCS) VCC 3.9 nH 10 nF 3 Lock Detect 34 4 Charge Pump 33 10 nF /N 5 1 nF LD 2.2 nF 36 kΩ 220 pF 33 pF 32 VCC LO2 100 pF 6 31 100 pF 7 30 8 29 D1 DO 39 nH 10 nF ** 39 nH 5 ** 1 nF 9 28 1 nF MIX IN+ Σ 10 MIX IN- VTUNE DO 200 Ω 3.9 kΩ LO1+ LO1- 27 Quad /2 11 26 1 nF 12 MODULATORS AND UPCONVERTERS 10 nF 10 nF VCC 25 13 14 15 16 17 18 19 20 21 22 23 24 REF ISIG 47 kΩ VCC VCC 10 nF L1* 1 nF 10 nF 10 nF L2* MOD OUT1 nF 39 kΩ MOD OUT+ *L1 and L2 are the bias choke inductor. Rev B4 010423 **Denotes components not normally populated. VGC OSIG 5-81 RF2668 Preliminary Evaluation Board Schematic RFOUT =830MHz (Download Bill of Materials from www.rfmd.com.) CE R6* LD Q1 PNP Zetex FMMT3906TA R5 510 Ω LD OUT C25 10 nF MIX EN P1 5 1 MODE 2 CE 3 TX EN 4 MIX EN 5 VCO EN MODULATORS AND UPCONVERTERS PLLON 7 SET1 8 SET2 9 GND 10 LDOUT P2 PLL ON REF 2 GND 3 VGC VTUNE 2 GND 3 VCC 50 Ω µstrip C19 1 nF C18 10 nF J1 RF OUT J2 LO2 C3 2 pF 50 Ω µstrip 1 L1 12 nH 48 47 46 Band Gap Rel 45 44 43 42 41 40 39 36 Bias Supply 35 /R 4 /N Lock Detect 34 Charge Pump 33 5 32 C5 100 pF 6 31 C6 100 pF 7 30 8 29 50 Ω µstrip T1 T4-1 C8 1 nF Σ 10 2668400A 50 Ω µstrip C21 2.2 nF R4 36 kΩ D1 C22 220 pF C27 33 pF DO L3 39 nH L2 39 nH C16** VCC C17 10 nF VTUNE R9 3.9 kΩ R7 200 Ω 26 25 13 14 15 16 17 18 19 20 21 22 23 DO T3 T4-1 27 Quad /2 12 C9 1 nF J4 MOD OUT LD 28 9 50 Ω µstrip C26 1 nF R8** C7 1 nF J3 MIX IN SET2 C20 10 nF 37 2 3 C4 10 nF 38 11 50 Ω µstrip R2 47 kΩ VCC 50 Ω µstrip VCC C10 10 nF NOTE: To tune the board for RF OUT = 1950 MHz, change L1 to 2.2 nH. R1 39 kΩ **Denotes not normally populated. VCC VGC C12 1 nF J7 L01 C13 10 nF 24 T2 T4-1 C11 1 nF 5-82 J8 OSC REF SET1 C1 1 nF P3 1 R3 270 Ω C2 10 nF VCC 1 VCO EN AGC CE MODE VCC VCC 6 R10 510 kΩ C23 10 nF J6 ISIG REF C23 10 nF 50 Ω µstrip J5 OSIG Rev B4 010423 RF2668 Preliminary Evaluation Board Schematic Dual Output Band VCC P1 2 CE 3 TX EN 4 MIX EN 5 MIX EN VCO EN PLL ON PLLON 7 SET1 8 SET2 9 GND 10 LDOUT P2 C18 10 nF J9 Cellular RF OUT J1 PCS RF OUT L8* 50 Ω µstrip C29 3 pF C3 0.5 pF 50 Ω µstrip L6* 2 GND 3 VGC J2 LO2 L1 100 nH L7 22 nH 50 Ω µstrip C5 100 pF C6 100 pF C7 1 nF VTUNE 2 GND 3 VCC 1 50 Ω µstrip 47 46 Band Gap Rel 45 44 43 42 41 40 39 38 50 Ω µstrip T1 T4-1 C8 1 nF SET1 37 C20 10 nF 36 Bias Supply 2 VCC 35 3 /N Lock Detect 34 Charge Pump 33 5 32 6 31 7 30 8 29 C26 1 nF C21 2.2 nF R4 36 kΩ LD D1 C22 220 pF DO L3 39 nH L2 39 nH C16* C27 33 pF VCC C17 10 nF R8* 9 J3 MIX IN J8 OSC REF SET2 48 4 C4 10 nF P3 1 C1 1 nF C19 1 nF /R L5 10 nH VCC REF R3 270 Ω C2 10 nF VCO EN 6 1 TX EN VCC MODE CE MODE VTUNE T3 T4-1 28 Σ 10 11 26 12 25 J7 R9 L01 3.9 kΩ R7 200 Ω 27 Quad /2 VCC C9 1 nF 13 14 15 16 17 18 19 20 21 22 23 C13 10 nF 24 2668401- R11* J4 MOD OUT 50 Ω µstrip T2 T4-1 L4* 22 nH 50 Ω µstrip VCC C11 1 nF C28* 4 pF R1 39 kΩ *Denotes not normally populated. C12 1 nF C23 10 nF REF C24 10 nF 50 Ω µstrip C10 10 nF Chip Enable R2 47 kΩ J6 ISIG R6* Q1 PNP Digikey MMBT3906DICT-ND LD R5 510 Ω J5 OSIG LD OUT C25 10 nF R10 510 kΩ R12* VCC Rev B4 010423 5 DO 50 Ω µstrip VGC 5-83 MODULATORS AND UPCONVERTERS 1 RF2668 Preliminary Evaluation Board Layout 2.500" X 2.250" Board Thickness 0.031”, Board Material FR-4 MODULATORS AND UPCONVERTERS 5 5-84 Rev B4 010423 Preliminary RF2668 Evaluation Board Layout - Dual Band Output MODULATORS AND UPCONVERTERS 5 Rev B4 010423 5-85 RF2668 Preliminary MODULATORS AND UPCONVERTERS 5 5-86 Rev B4 010423