RFMD RF2705

RF2705
0
LOW NOISE, MULTI-MODE, QUAD-BAND,
QUADRATURE MODULATOR AND PA DRIVER
Typical Applications
• EDGE/GSM (GSM850/900) Handsets
• EDGE/GSM (DCS/PCS) Handsets
• W-CDMA/GSM/EDGE Multimode Handsets
and Data Cards
• W-CDMA Handsets/Data Cards
Product Description
-A-
4.00
The RF2705 is a low noise, multi-mode, quad-band direct
I/Q to RF modulator and PA driver designed for handset
applications where multiple modes of operation are
required. Frequency doublers, dividers and LO buffers
are included to support a variety of LO generation
options. Dynamic power control is supported through a
single analog input giving 90dB of power control range for
the W-CDMA mode and 40dB of power control in the
other two modes. Three sets of RF outputs are provided:
high band and low band low noise EDGE/GMSK outputs,
as well as one wideband W-CDMA output. The device is
designed for 2.7V to 3.3V operation, and is assembled in
a plastic, 24-pin, 4mmx4mm QFN.
-B-
1.00
0.80
0.10 C
4.00
0.10 C
0.10 C
0.10 C
2.45
0.50 TYP
-C-
+0.10
-0.10
SEATING
PLANE
Shaded lead is pin 1.
Dimensions in mm.
Scale: None
2.45
0.05
0.00
0.10 C
+0.10
-0.10
0.08 C
0.30
TYP
0.18
0.50
TYP
0.30
0.10 M C A B
Optimum Technology Matching® Applied
Si BJT
GaAs HBT
GaAs MESFET
Si Bi-CMOS
SiGe HBT
Si CMOS
InGaP/HBT
GaN HEMT
MODE B
I SIG N
I SIG P
VCC1
MODE A
GND
9SiGe Bi-CMOS
24
23
22
21
20
19
VCC2 1
RF OUT
17
WB N
DIV
2
+45°
-45°
• W-CDMA High/Mid/Low Power Modes
• Variable Gain PA Drivers
RF OUT
WB P
Note: The die flag is the
chip's main ground.
LO HB N 3
Features
• Quad-Band Direct Quadrature Modulator
18
LO HB P 2
Package Style: QFN, 24-Pin, 4x4
16
RF OUT
HB P
15
RF OUT
HB N
14
RF OUT
LB P
13
RF OUT
LB N
• GMSK Bypass Amplifiers
• LO Frequency Doubler and Divider
• Baseband Filtering
Σ
Flo
x2
LO LB P 4
LO LB N 5
+45°
-45°
Mode Control
and Biasing
Power
Control
RF2705
7
8
9
10
11
12
MODE D
Q SIG N
Q SIG P
VREF
GC DEC
GC
MODE C 6
Functional Block Diagram
Rev A4 041026
Ordering Information
Low Noise, Multi-Mode, Quad-Band, Quadrature
Modulator and PA Driver
RF2705PCBA-41XFully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
5-113
RF2705
Absolute Maximum Ratings
Parameter
Supply Voltage
Storage Temperature
Operating Ambient Temperature
Input Voltage, any pin
Input Power, any pin
Rating
Unit
-0.5 to 3.6
-40 to +150
-40 to +85
-0.5 to +3.6
+5
V
°C
°C
V
dBm
Specification
Min.
Typ.
Max.
Output Performance with Modulated Baseband Inputs
Low Band EDGE 8PSK Mode (GSM850/GSM900)
Parameter
Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Unit
Condition
Mode=Low Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
VCC =2.7V, T=+25°C
Output Power
Maximum Output Power with
8PSK Modulated Signal*
Maximum VGC
Minimum VGC
Gain Range
0
+2.5
-39
42
-37
dBm
dBm
dB
While meeting spectral mask
While meeting spectral mask
Difference between output power at
GC=2.0V and GC=0.2V.
30kHz BW
30kHz BW
30kHz BW
30kHz BW
100kHz BW
100kHz BW
100kHz BW
8PSK Modulation
Out-of-Band Emission
Spectrum Emission Mask*
Frequency Spacing
200kHz
250kHz
400kHz
600kHz to 1800kHz
1800kHz to 3000kHz
3000kHz to 6000kHz
>6000kHz
-36
-43
-67
-73
-73
-73
-75
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
2
-40
4
3
-34
9
%
dB
%
Error Vector Magnitude
RMS*
Origin Offset*
Peak*
Output Noise
At FC ±20MHz*
Relative Noise at:
Maximum Gain
Absolute Noise at:
Maximum Gain
All Gain Settings
-156
-152
dBc/Hz
dBc/Hz
-156
-154
dBm
dBm
GC=2.0V, IQ=1.2VP-P 8PSK
GC=2.0V to 1.4V
GC=2.0V, IQ=0VP-P
IQ=1.2VP-P 8PSK
General Conditions
Local Oscillator
LO LB Input Frequency
RF LB Output Frequency
Input Power
IQ Baseband Inputs
IQ Level
IQ Common Mode
Input Bandwidth
Baseband Filter Attenuation
* Not tested in Production
5-114
824
824
-6.0
0.7
20
0.0
915
915
+3.0
MHz
MHz
dBm
1.2
VP-P
1.2
1.0
V
MHz
dB
8PSK
Input IQ signal driven differentially and in
quadrature.
At 20MHz offset
Rev A4 041026
RF2705
Specification
Min.
Typ.
Max.
Output Performance with Modulated Baseband Inputs
High Band EDGE 8PSK Mode (DCS1800/PCS1900)
Parameter
Unit
Condition
Mode=High Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
VCC =2.7V, T=+25°C
Output Power
Maximum Output Power with
8PSK Modulated Signal*
Maximum VGC
Minimum VGC
Gain Range
-1
+1.5
-40
42
-38
dBm
dBm
dB
While meeting spectral mask
While meeting spectral mask
Difference between output power at
GC=2.0V and GC=0.2V.
30kHz BW
30kHz BW
30kHz BW
30kHz BW
100kHz BW
100kHz BW
100kHz BW
8PSK Modulation
Out-of-Band Emission
Spectrum Emission Mask*
Frequency Spacing
200kHz
250kHz
400kHz
600kHz to 1800kHz
1800kHz to 3000kHz
3000kHz to 6000kHz
>6000kHz
-36
-43
-67
-73
-73
-73
-75
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1.3
-37
3
3
-30
11
%
dB
%
Error Vector Magnitude
RMS*
Origin Offset*
Peak*
Output Noise
At FC ±20MHz*
Relative Noise at:
Maximum Gain
Absolute Noise at:
Maximum Gain
All Gain Settings
-154
-150
dBc/Hz
dBc/Hz
-153
-151
dBm
dBm
GC=2.0V, IQ=1.2VP-P 8PSK
GC=2.0V to 1.4V
GC=2.0V, IQ=0VP-P
IQ=1.2VP-P 8PSK
General Conditions
Local Oscillator
LO HB Input Frequency
RF HB Output Frequency
Input Power
IQ Baseband Inputs
IQ Level
IQ Common Mode
Input Bandwidth
Baseband Filter Attenuation
* Not tested in Production
Rev A4 041026
1710
1710
-6.0
0.7
20
0.0
1910
1910
+3.0
MHz
MHz
dBm
1.2
VP-P
1.2
1.0
V
MHz
dB
8PSK
Input IQ signal driven differentially and in
quadrature.
At 20MHz offset
5-115
RF2705
Specification
Min.
Typ.
Max.
Output Performance with Modulated Baseband Inputs
W-CDMA Mode
Parameter
Unit
Condition
Mode=Wideband FLOx2 (see Control Logic Truth Table for Mode Control Settings)
VCC =2.7V, T=+25°C, while meeting 48dBc
ALCR
Output Power
Maximum Output Power with
W-CDMA Modulated Signal*
High Power Mode
Medium Power Mode
3
-4
6
-1
dBm
dBm
90
dB
Gain Range
High Power Mode
±0.5
TBD
dB
dB
Gain step when switching between power
modes in either direction.
GC=1.4V
GC=TBD
50
65
dBc
dBc
3.84MHz relative to channel power
3.84MHz relative to channel power
1.4
%rms
Gain Step
High Power to Medium Power
Medium Power to Low Power
GC=2.0V
GC=1.5V
Difference between output power at
GC=2.0V and GC=0.2V.
Out-of-Band Emission
Adjacent Channel Leakage
Power Ratio (ALCR)*
Channel Spacing
±5MHz
±10MHz
Error Vector Magnitude
RMS*
3GPP W-CDMA
Output Noise
At FC ±40MHz*
-152
-146
-146
dBc/Hz
dBc/Hz
990
1980
+3.0
MHz
MHz
dBm
GC=2.0V
GC=2.0V to 1.5V
General Conditions
Local Oscillator
LO LB Input Frequency
RF WB Output Frequency
Input Power
IQ Baseband Inputs
960
1920
-10.0
IQ Level
IQ Common Mode
Input Bandwidth
Baseband Filter Attenuation
* Not tested in Production
5-116
8
10
0.0
0.8
VP-P
1.2
11
V
MHz
dB
3GPP W-CDMA
HQPSK, 1DPCCH+1DPDCH
Input IQ signal driven differentially and in
quadrature.
At 40MHz offset
Rev A4 041026
RF2705
Specification
Min.
Typ.
Max.
Output Performance with CW Baseband Inputs
Wideband Mode
Parameter
Unit
Condition
Mode=Wideband FLOx2 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power W-CDMA Modulated*
Output Power CW
Gain Control Voltage Range
Gain Control Range
5
2
0.2
5
dBm
8
2.0
VCC =2.7V, T=+25°C, LO=975MHz to
990MHz at -10dBm, IQ=540mVP-P** at
100kHz, unless otherwise noted
GC=2.0V, IQ=0.8VP-P at HQPSK
92
dBm
V
dB
GC=2.0V
Gain Control Slope
73
dB/V
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=1.0V and 0.5V
Sideband Suppression
*
*
*
Carrier Suppression
-48
-50
-50
-50
-42
-41
-38
-23
-55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V
Modulator
3rd Harmonic of Modulation
Suppression at FC-3x300kHz
-30
-30
-30
-30
-30
-30
-30
-10
-50
Spurious Outputs
Spurious Output at Integer Multiples of FLO LB*
FLO LB
4xFLO LB
6xFLO LB
GC=2.0V, I/Q=540mVP-P at 100kHz
-60.0
-14.0
-47.0
dBm
dBm
dBm
FLO LB leakage
Second harmonic of carrier
Third harmonic of carrier
+11.5
dBm
I/Q=100kHz
Output IP3*
+20
dBm
Intermodulation IM3 tone at
FC +70kHz and FC +130kHz
relative to tones at
FC +90kHz and FC +110kHz
-37
dBc
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mVP-P.
GC=2.0V
0
0
Output Compression
Output P1dB*
Intermodulation
-40
dBc
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
Rev A4 041026
GC=1.5V
5-117
RF2705
Specification
Min.
Typ.
Max.
Output Performance with CW Baseband Inputs
Low Band Mode (GSM850/GSM900)
Parameter
Unit
Condition
Mode=Low Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power 8PSK Modulated*
Output Power CW
42
dBm
dBm
dBm
dBm
dBm
dBm
V
dB
Gain Control Slope
28
dB/V
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=0.5V and 1.5V
Sideband Suppression
*
*
*
*
Carrier Suppression
-36
-36
-36
-36
-36
-44
-44
-44
-44
-40
-30
-30
-30
-30
-30
-34
-34
-34
-34
-34
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
-49
-40
dBc
GC=2.0V
FLO/2 Mode
GC=2.0V, I/Q=800mVP-P at 100kHz
dBm
dBm
Second harmonic of carrier and LO leakage
Third harmonic of carrier
0
*
Gain Control Voltage Range
Gain Control Range
-44
0.2
+2.5
2.2
-1.2
-13.5
-30
-40
VCC =2.7V, T=+25°C,
LO=824MHz to 915MHz at 0dBm,
IQ=800mVP-P** at 100kHz,
unless otherwise noted
GC=2.0V, IQ=1.2VP-P 8PSK
GC=2.0V, IQ=800mVP-P at 100kHz
GC=1.5V, IQ=800mVP-P at 100kHz
GC=1.0V, IQ=800mVP-P at 100kHz
GC=0.5V, IQ=800mVP-P at 100kHz
GC=0.2V, IQ=800mVP-P at 100kHz
+5
-37
2.0
Modulator
*
3rd Harmonic of Modulation
Suppression at FC-3x300kHz
Spurious Outputs
Spurious Outputs at Integer
Harmonics of 1/2xFLOHB*
FLO HB
(3/2)xFLO LB
-62.0
-19.0
Output Compression
Output P1dB*
+7.0
dBm
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
5-118
I/Q=100kHz
Rev A4 041026
RF2705
Specification
Min.
Typ.
Max.
Output Performance with CW Baseband Inputs
Low Band Mode (GSM850/GSM900), cont’d
Parameter
Unit
Condition
Mode=Low Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
Intermodulation
Output IP3*
Intermodulation IM3 tone at
FC +70kHz and FC +130kHz
relative to tones at
FC +90kHz and FC +110kHz
+20.0
dBm
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mVP-P.
-48
dBc
GC=2.0V
Low Band Bypass Mode (GSM850/GSM900)
Mode=Low Band Bypass (see Control Logic Truth Table for Mode Control Settings)
PA Driver
GMSK Input Power*
GMSK Output Power
Output Impedance*
-3
5.0
0
7.5
50
+3
10.0
dBm
dBm
Ω
-161
-159
dBc/Hz
VCC =2.7V
At LO LB input from a 50Ω source.
At RF LB output
Output Noise
At FC ±20MHz*
* Not tested in Production
Rev A4 041026
AM+PM noise, LO=0dBm
5-119
RF2705
Specification
Min.
Typ.
Max.
Output Performance with CW Baseband Inputs
High Band Mode (DCS1800/PCS1900)
Parameter
Unit
Condition
Mode=High Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power 8PSK Modulated*
Output Power CW
0
0
42
dBm
dBm
dBm
dBm
dBm
dBm
V
dB
Gain Control Slope
28
dB/V
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=0.5V and 1.5V
Sideband Suppression
*
*
*
*
Carrier Suppression
-45
-45
-45
-45
-45
-40
-40
-40
-39
-37
-30
-30
-30
-30
-30
-34
-34
-33
-30
-30
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
-50
-40
dBc
GC=2.0V
FLOx2 Mode
GC=2.0V, I/Q=800mVP-P at 100kHz
dBm
dBm
dBm
FLO LB leakage
Second harmonic of carrier
Third harmonic of carrier
*
Gain Control Voltage Range
Gain Control Range
-44
0.2
2.2
2
-1.6
-17.6
-30
-40
VCC =2.7V, T=+25°C,
LO=1710MHz to 1910MHz at 0dBm,
IQ=800mVP-P** at 100kHz,
unless otherwise noted
GC=2.0V, IQ=1.2VP-P 8PSK
GC=2.0V, IQ=800mVP-P at 100kHz
GC=1.5V, IQ=800mVP-P at 100kHz
GC=1.0V, IQ=800mVP-P at 100kHz
GC=0.5V, IQ=800mVP-P at 100kHz
GC=0.2V, IQ=800mVP-P at 100kHz
+6.0
-37
2.0
Modulator
*
3rd Harmonic of Modulation
Suppression at FC-3x300kHz
Spurious Outputs
Spurious Outputs at Integer
Harmonics of 1/2xFLOHB
FLO LB
4xFLO LB
6xFLO LB
-70.0
-25.0
-40.0
Output Compression
Output P1dB*
+8.0
dBm
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
5-120
I/Q=100kHz
Rev A4 041026
RF2705
Specification
Min.
Typ.
Max.
Output Performance with CW Baseband Inputs
High Band Mode (DCS1800/PCS1900), cont’d
Parameter
Unit
Condition
Mode=High Band FLOx1 (see Control Logic Truth Table for Mode Control Settings)
Intermodulation
Output IP3*
+20
Intermodulation IM3 tone at
FC +70kHz and FC +130kHz
relative to tones at
FC +90kHz and FC +110kHz
-53
-42
dBm
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mVP-P.
dBc
GC=2.0V
Output Performance with CW Baseband Inputs
Wideband Mode
Mode=Wideband FLOx2 (see Control Logic Truth Table for Mode Control Settings)
VGA and PA Driver
Output Power W-CDMA Modulated*
Output Power CW
Gain Control Voltage Range
Gain Control Range
5
2
0.2
5
dBm
8
2.0
VCC =2.7V, T=+25°C, LO=975MHz to
990MHz at -10dBm, IQ=540mVP-P** at
100kHz, unless otherwise noted
GC=2.0V, IQ=0.8VP-P at HQPSK
92
dBm
V
dB
GC=2.0V
Gain Control Slope
73
dB/V
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=1.0V and 0.5V
Sideband Suppression
*
*
*
Carrier Suppression
-48
-50
-50
-50
-42
-41
-38
-23
-55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V
Modulator
3rd Harmonic of Modulation
Suppression at FC-3x300kHz
-30
-30
-30
-30
-30
-30
-30
-10
-50
Spurious Outputs
Spurious Output at Integer Multiples of FLO LB*
FLO LB
4xFLO LB
6xFLO LB
GC=2.0V, I/Q=540mVP-P at 100kHz
-60.0
-14.0
-47.0
dBm
dBm
dBm
FLO LB leakage
Second harmonic of carrier
Third harmonic of carrier
+11.5
dBm
I/Q=100kHz
Output IP3*
+20
dBm
Intermodulation IM3 tone at
FC +70kHz and FC +130kHz
relative to tones at
FC +90kHz and FC +110kHz
-37
dBc
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mVP-P.
GC=2.0V
0
0
Output Compression
Output P1dB*
Intermodulation
-40
dBc
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
Rev A4 041026
GC=1.5V
5-121
RF2705
Specification
Min.
Typ.
Max.
High Band Bypass Mode (DCS1800/PCS1900)
Parameter
Unit
Condition
Mode=High Band Bypass (see Control Logic Truth Table for Mode Control Settings)
PA Driver
GMSK Input Power*
GMSK Output Power
Output Impedance*
-3
4.0
0
6.8
50
+3
9.0
dBm
dBm
Ω
-161
-159
dBc/Hz
VCC =2.7V
At LO LB input from a 50Ω source.
At RF LB output
Output Noise
At FC ±20MHz*
* Not tested in Production
5-122
AM+PM noise, LO=0dBm
Rev A4 041026
RF2705
Parameter
Specification
Min.
Typ.
Max.
Unit
Condition
General Specifications
Operating Range
Supply Voltage
Temperature
2.7
-40
3.3
+85
V
°C
Refer to Logic Control Truth Table for Mode
Control Pin Voltages.
Current Consumption
Sleep
Wideband FLOx1 (high power)
*
(medium power)
*
(low power)
*
Wideband FLOx2 (high power)
<1
114
85
89
54
63
42
110
84
80
53
54
41
72
82
23
22
76
74
(medium power)
(low power)
High Band FLOx2
Low Band FLO/2
High Band Bypass
Low Band Bypass
High Band FLOx1
Low Band FLOx1
10
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
GC=2.0V
GC=0.2V
GC=2.0V
GC=0.2V
GC=2.0V. See Note 1.
GC=0.2V. See Note 1.
GC=2.0V
GC=0.2V
GC=2.0V
GC=0.2V
GC=2.0V. See Note 1.
GC=0.2V. See Note 1.
GC=2.0V
GC=2.0V
GC=2.0V
GC=2.0V
Logic Levels
Input Logic 0
Input Logic 1
Logic Pins Input Current
0
1.4
0.4
VCC
<1.0
V
V
µA
CMOS inputs
LO Input Ports
LO LB Input Frequency Range
LO HB Input Frequency Range
Input Impedance
800
1600
1000
2000
50
MHz
MHz
Ω
Externally matched
I/Q Baseband Inputs
Baseband Input Voltage
Baseband Input Level
1.15
1.25
V
Common mode voltage
Differential
EDGE
1.2
VP-P
1DPCCH+1DPDCH. See Note 1.
W-CDMA
0.8
VP-P
Differential
GMSK
1.0
VP-P
Baseband Input Impedance
100k||1pF
Ω
Measured at 100kHz
Input Bandwidth
EDGE
0.7
1.0
MHz
W-CDMA
8.0
11.0
MHz
Baseband Filter Attenuation
EDGE
20
dB
At 20MHz
W-CDMA
10
dB
At 40MHz
Baseband Input DC Current
-10
0
10
µA
Gain Control
Gain Control Voltage
0.2
2.2
V
Gain Control Impedance
10
kΩ
Note 1: In low power mode it is recommended that the IQ level be reduced to 0.4VP-P. If IQ level is >0.4VP-P, this mode should be used
for W-CDMA TX power levels below -20dBm (measured at antenna).
Rev A4 041026
5-123
RF2705
Pin
1
Function
VCC2
Description
Supply for LO buffers, frequency doubler and dividers.
Interface Schematic
VCC2
Modulator and
VGA
2
LO HB P
3
LO HB N
5-124
High band local oscillator input (1800MHz).
In “low band FLO/2” modes the signal (LOHBP-LOHBN) undergoes a
frequency division of 2 to provide the low band LO signal for the modulator.
VCC
In “high band FLOx1” modes the signal (LOHBP-LOHBN) is used as
the high band LO signal for the modulator.
In “high band bypass” a modulated DCS1800/PCS1900 signal
(LOHBP-LOHBN) is switched into the RF signal path. The modulator
is disabled and the signal is routed to the RFOutHb outputs through a
differential PA driver amplifier.
The LOHBP input is AC-coupled internally.
LO HB P
The noise performance, carrier suppression at low output powers and
sideband suppression all vary with LO power. The optimum LO power
is between -3dBm and +3dBm. The device will work with LO powers as LO HB N
low as -20dBm however this is at the expense of higher phase noise in
the LO circuitry and poorer sideband suppression.
The input impedance should be externally matched to 50Ω. The port
can be driven either differentially or single ended. The port impedance
does not vary significantly between active and power down modes.
The RF2705 is intended for use with the RF6002. This performs the
GSM GMSK modulation within a Frac-N synthesizer loop. The 8PSK
EDGE and W-CDMA signal modulations are performed in the RF2705
and uses the RF6002’s synthesizers to generate the LO signals. The
LO signal for EDGE900 mode is derived by frequency division by 2 of
the RF6002’s DCS1800 VCO. This helps protect the system against PA
pulling.
The complementary LO input for both LOHBP LO signals.
See pin 2.
In any of the modes the LOHB input may be driven either single ended
or differentially. If the LO is driven single ended then the PCB board
designer can ground this pin.
It is recommended that if this pin is grounded that it is kept isolated
from the GND1 pin and the die flag ground. All connections to any other
ground should be made through a ground plane. Poor routing of this
ground signal can significantly degrade the LO leakage performance.
Rev A4 041026
RF2705
Pin
4
Function
LO LB P
5
LO LB N
6
MODE C
7
MODE D
Rev A4 041026
Description
Interface Schematic
Low band local oscillator input (900MHz).
In “wideband FLOx2” and “high band FLOx2” modes the signal
(LOLBP-LOLBN) is doubled in frequency to provide the LO signal for
the modulator.
In “Low band FLOx1” modes the signal (LOLBP-LOLBN) is used as
VCC
the LO signal for the modulator.
In “Low band Bypass” a modulated GSM900 signal (LOLBP-LOLBN)
is switched into the RF signal path. The modulator is disabled and the
signal is routed to the RFOutLb outputs through a differential PA driver
amplifier.
This LOLBP input is AC-coupled internally.
The noise performance, carrier suppression at low output powers and
LO LB P
sideband suppression performance are functions of LO power. The
optimum LO power is between -3dBm and +3dBm. The device will
work with LO powers as low as -20dBm however this is at the expense LO LB N
of higher noise performance at high output powers and poorer sideband suppression.
The input impedance should be externally matched to 50Ω. The port
impedance does not vary significantly between active and powered
modes.
The RF2705 is intended for use with the RF6002 which performs the
GSM GMSK modulation within a Frac-N synthesizer loop. The 8PSK
EDGE and W-CDMA signal modulations are performed in the RF2705
and uses the RF6002’s synthesizers to generate the LO signals. The
LO signal for DCS1800 mode is derived by frequency doubling
RF6002’s GSM900 VCO. This helps protect the system against PA pulling.
The complementary LO input for both LOLBP LO signals.
See pin 4.
In any of the modes the LOLB input may be driven either single ended
or differentially. If the LO is driven single ended then the PCB board
designer can ground this pin.
It is recommended that if this pin is grounded that it is kept isolated
from the GND1 pin and the die flag ground. All connections to any other
ground should be made through a ground plane. Poor routing of this
GndLO signal can significantly degrade the LO leakage performance.
Chip enable control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.
VCC2
See pin 6.
5-125
RF2705
Pin
8
9
10
11
12
Function
Q SIG N
Q SIG P
VREF
GC DEC
GC
Description
Quadrature Q channel negative baseband input port.
Best performance is achieved when the QSIGP and QSIGN are driven
differentially with a 1.2V common mode DC voltage. The recommended differential drive level (VQSIGP -VQSIGN) is 1.2VP-P for EDGE,
0.8VP-P for W-CDMA modulation and 1.0VP-P for GMSK modulation.
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is
de-biased.
Phase or amplitude errors between the QSIGP and QSIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the QSIGP and QSIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel out the LO leakage. The optimum corrective DC offsets will change
with mode, frequency and gain control.
Common-mode noise on the QSIGP and QSIGN should be kept low
as it may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degraded sideband suppression.
Quadrature Q channel negative baseband input port. See pin 8.
Voltage reference decouple.
External 10nF decoupling capacitor to ground.
The voltage on this pin is typically 1.67V when the chip is enabled. The
voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency
noise (20MHz) on the gain control lines.
Poor positioning of the VREF decoupling capacitor can cause a degradation in LO leakage.
A voltage of around 2.5V on this pin indicates that the die flag under
the chip is not grounded and the chip is not biased correctly.
Gain control voltage decouple with an external 1nF decoupling capacitor to ground.
The voltage on this pin is a function of gain control (GC) voltage when
the chip is enabled. The voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency
noise (20MHz) on the gain control lines. The size capacitor on the GC
DEC line will effect the settling time response to a step in gain control
voltage. A 1nF capacitor equates to around 200ns settling time and a
0.5nF capacitor equates to a 100ns settling time. There is a trade-off
between settling time and noise contributions by the gain control circuitry as gain control is applied.
Poor positioning of the VREF decoupling capacitor can cause a degradation in LO leakage.
Gain control voltage. Maximum output power at 2.0V. Minimum output
power at 0V. When the chip is enabled the input impedance is 10kΩ to
1.67VDC. When the chip is powered down a FET switch is opened and
the input goes high impedance.
Interface Schematic
VCC2
x1
See pin 8.
VCC2
4 kΩ
+
VCC2
4 kΩ
+
VCC2
4 kΩ
10 kΩ
-
1.7 V
5-126
+
Rev A4 041026
RF2705
Pin
13
Function
RF OUT
LB N
Description
Interface Schematic
Differential low band PA driver amplifier output.
This output is intended for low band (GSM850/900) operation and
drives a differential SAW.
A bypass mode allows the low band PA driver amplifier’s input to be
switched between the signal from the modulator and the signal applied
at LOLB. This enables a GMSK-modulated signal on the LOLB input to
be switched into the RF signal path.
The output is an open collector. The outputs are matched off-chip.
VCC
VCC
VCC
RF OUT LB P
RF OUT LB N
14
15
RF OUT
LB P
RF OUT
HB N
Complementary differential low band PA driver amplifier output.
See pin 13.
See pin 13.
Differential high band PA Driver amplifier output.
This output is intended for DCS1800/PCS1900 band operation.
A bypass mode allows the high band PA driver amplifier’s input to be
switched between the signal from the modulator and the signal applied
at LOHB. This enables a GMSK-modulated DCS1800/PCS1900 signal
on the LOHB input to be switched into the RF signal path.
The output is an open collector. The outputs are matched off-chip.
VCC
VCC
VCC
RF OUT HB P
RF OUT HB N
16
17
RF OUT
HB P
RF OUT
WB N
Complementary differential high band PA driver amplifier output.
See pin 15.
See pin 15.
Differential high band PA driver amplifier output.
This output is intended for wide band (W-CDMA) applications.
The output is an open collector. The output are matched off-chip.
VCC
VCC
VCC
RF OUT WB P
RF OUT WB N
18
19
20
RF OUT
WB P
GND
MODE A
21
VCC1
Complementary differential wideband PA driver amplifier output.
See pin 17.
See pin 17.
Ground.
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.
Supply for modulator, VGA and PA driver amplifiers.
See pin 6.
VCC1
LO Quadrature
Generator and
Buffers
GND1
Rev A4 041026
5-127
RF2705
Pin
22
Function
I SIG P
23
24
I SIG N
MODE B
Pkg
Base
DIE FLAG
5-128
Description
In-phase I channel positive baseband input port.
Best performance is achieved when the ISIGP and ISIGN are driven
differentially with a 1.2V common mode DC voltage. The recommended differential drive level (VISIGP -VISIGN) is 1.2VP-P for EDGE,
0.8VP-P W-CDMA modulation and 1.0VP-P for GMSK modulation.
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is
de-biased.
Phase or amplitude errors between the ISIGP and ISIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the ISIGP and ISIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to cancel out the LO leakage. The optimum corrective DC offsets will change
with mode, frequency and gain control.
Common-mode noise on the ISIGP and ISIGN should be kept low as it
may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degrades sideband suppression.
In-phase I channel negative baseband input port. See pin 22.
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to VCC.
Interface Schematic
VCC2
x1
See pin 22.
See pin 6.
Ground for LO section, modular, biasing, variable gain amplifier, and
substrate.
Rev A4 041026
RF2705
LO Frequency Planning Options for European 3GPP W-CDMA/EDGE
Recommended Frequency Plan: Frequency Doubler/Divide by 2/GMSK Modulator Bypass Modes
Modulation
Output Frequency Band
LO Port
LO Frequency Range
Comments
Format
Band
GSM850
Lower Limit Upper Limit
824MHz
849MHz
EDGE 8PSK
LOHB
GSM850
824MHz
849MHz
GSM GMSK
LOLB
GSM900
880MHz
915MHz
EDGE 8PSK
LOHB
GSM900
880MHz
915MHz
GSM GMSK
LOLB
DCS1800
1710MHz
1785MHz
EDGE 8PSK
LOLB
DCS1800
1710MHz
1785MHz
GSM GMSK
LOHB
PCS1900
1850MHz
1910MHz
EDGE 8PSK
LOLB
PCS1900
1850MHz
1910MHz
GSM GMSK
LOHB
W-CDMA1950
1920MHz
1980MHz
3GPP W-CDMA
LOLB
On Frequency LO with GMSK Modulator Bypass Modes
Modulation
Output Frequency Band
LO Port
Format
Band
GSM850
Lower Limit Upper Limit
824MHz
849MHz
EDGE 8PSK
LOLB
GSM850
824MHz
849MHz
GSM GMSK
LOLB
GSM900
880MHz
915MHz
EDGE 8PSK
LOLB
GSM900
880MHz
915MHz
GSM GMSK
LOLB
DCS1800
1710MHz
1785MHz
EDGE 8PSK
LOHB
DCS1800
1710MHz
1785MHz
GSM GMSK
LOHB
PCS1900
1850MHz
1910MHz
EDGE 8PSK
LOHB
PCS1900
1850MHz
1910MHz
GSM GMSK
LOHB
W-CDMA1950
1920MHz
1980MHz
3GPP W-CDMA
LOHB
Rev A4 041026
Lower Limit Upper Limit
1648MHz
1698MHz FLO/2
Divide by 2
824MHz
849MHz
FLO_bypass Bypass,
GMSK-modulated LO
1760MHz
1830MHz FLO/2
Divide by 2
880MHz
915MHz
FLO_bypass Bypass,
GMSK-modulated LO
855MHz
892.5MHz FLOx2
Frequency Doubler
1710MHz
1785MHz FLO_bypass Bypass,
GMSK-modulated LO
925MHz
955MHz
FLOx2
Frequency Doubler
1850MHz
1910MHz FLO_bypass Bypass,
GMSK-modulated LO
960MHz
990MHz
FLOx2
Frequency Doubler
LO Frequency Range
Comments
Lower Limit Upper Limit
824MHz
849MHz
FLOx1
On Frequency
824MHz
849MHz
FLO_bypass Bypass,
GMSK-modulated LO
880MHz
915MHz
FLOx1
On Frequency
880MHz
915MHz
FLO_bypass Bypass,
GMSK-modulated LO
1710MHz
1785MHz FLOx1
On Frequency
1710MHz
1785MHz FLO_bypass Bypass,
GMSK-modulated LO
1850MHz
1910MHz FLOx1
On Frequency
1850MHz
1910MHz FLO_bypass Bypass,
GMSK-modulated LO
1920MHz
1980MHz FLOx1
On Frequency
5-129
RF2705
Control Logic Truth Table
Active RF
I/Os
Input Logic
Mode Description
Comment
Expected Mode of
Operation
Mode A Mode B Mode C Mode D
Sleep Mode
Sleep
X
0
0
0
Sleep
Frequency Doubler/Divide by 2 Options
Wideband FLOx2 (High Power)
Modulator and frequency doubler
enabled
Wideband FLOx2 (Medium Power)
Modulator and frequency doubler
enabled
Wideband FLOx2 (Low Power)
Modulator and frequency doubler
enabled
High Band FLOx2
Modulator and frequency doubler
enabled
Low Band FLO/2
Modulator and divide by 2 enabled
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
1
LoLbP LoLbN
RFOutWb P
RFOutWb N
LoLbP LoLbN
RFOutWb P
RFOutWb N
LoLbP LoLbN
RFOutWb P
RFOutWb N
LoLbP LoLbN
RFOutHb P
RFOutHb N
LoHbP LoHbN
RFOutLb P
RFOutLb N
Bands: 1920MHz to 1980MHz
Modulation: 3GPP W-CDMA
Bands: 1920MHz to 1980MHz
Modulation: 3GPP W-CDMA
Bands: 1920MHz to 1980MHz
Modulation: 3GPP W-CDMA
Bands: DCS1800 or PCS1900
Modulation: GMSK, TDMA and
8PSK EDGE
Bands: GSM900 or GSM850
Modulation: GMSK, TDMA and
8PSK EDGE
GMSK Modulator Bypass Options
Low Band Bypass
Modulator bypass enabled
X
1
0
0
High Band Bypass
Modulator bypass enabled
X
1
1
0
Wideband FLOx1 (High Power)
Modulator and on-frequency LO
enabled
Wideband FLOx1 (Medium Power)
Modulator and on-frequency LO
enabled
Wideband FLOx1 (Low Power)
Modulator and on-frequency LO
enabled
High Band FLOx1
Modulator and on-frequency LO
enabled
Low Band FLOx1
Modulator and on-frequency LO
enabled
0
0
1
0
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
1
LoLbP LoLbN
RFOutLb P
RFOutLb N
LoHbP LoHbN
RFOutHb P
RFOutHb N
Bands: GSM850 or GSM900
Modulation: GMSK
Bands: DCS1800 or PCS1900
Modulation: GMSK
On-Frequency LO Options
5-130
LoHbP LoHbN
RFOutWb P
RFOutWb N
LoHbP LoHbN
RFOutWb P
RFOutWb N
LoHbP LoHbN
RFOutWb P
RFOutWb N
LoHbP LoHbN
RFOutHb P
RFOutHb N
LoLbP LoLbN
RFOutLb P
RFOutLb N
Bands: 1920MHz to 1980MHz
Modulation: 3GPP W-CDMA
Bands: 1920MHz to 1980MHz
Modulation: 3GPP W-CDMA
Bands: 1920MHz to 1980MHz
Modulation: 3GPP W-CDMA
Bands: DCS1800 or PCS1900
Modulation: GMSK, TDMA and
8PSK EDGE
Bands: GSM900 to GSM850
Modulation: GMSK, TDMA and
8PSK EDGE
Rev A4 041026
RF2705
Application Information
The baseband inputs of the RF2705 must be driven with balanced signals. Amplitude and phase matching <0.5dB and
<0.5 degrees are recommended. Phase or gain imbalances between the complementary input signals will cause additional distortion including some second order baseband distortion.
The RF2705 is designed to be driven with either single-ended or differential LO signals. Driving the chip differentially is
beneficial in improving the LO leakage performance. Decreasing the LO drive level will also improve LO leakage, but the
output noise performance will be degraded. Driving the LO level too high will degrade linearity.
The ground lines for the LO sections are brought out of the chip independently from the ground to the RF and modulator
sections. This is intended to give the board design the independence of isolating the LO signals from the RF output sections.
The RF2705 includes frequency doubler and divider modes that allow the LO to operate at half or twice the frequency
depending on the application. This provides some flexibility in improving VCO isolation and LO leakage through frequency translation.
The RF outputs use open collector architecture and may be biased at voltages higher than VCC. In practice, biasing at a
higher voltage may improve the intermodulation performance. The load resistors are selected to provide sufficient output
power while maintaining good linearity.
The GC DEC and VREF output pins should be decoupled to ground. A 10nF capacitor on VREF and a 1nF capacitor on
GC CEC are recommended. The purpose of these capacitors is to filter out low frequency noise (20MHz) in the gain
control lines that may cause noise on the RF signal. The capacitor on the GC DEC line will effect the settling time of the
step response in power control voltage. A 1nF capacitor equates to around a 200ns settling time; a 0.5nF capacitor
equates to a 100ns settling time. There is a trade-off between setting time and phase noise as gain control is applied.
As with any RF circuit, the RF2705 is sensitive to PC board layout. The suggested schematic and board layout is
included as a guideline. Proper grounding of the die flag under the chip is essential in achieving acceptable RF performance. A symmetric output structure will maintain signal balance while keeping the RF lines short will reduce losses.
Proper routing and bypassing of the supply lines will improve stability and performance, especially under low gain control
settings where carrier suppression becomes crucial. The location and value of the bypass capacitor on pin 1 is critical in
promoting good carrier suppression and is designated to resonate out the series wire bond and PC board inductance.
Rev A4 041026
5-131
RF2705
Application Schematic
VCC
MODE A
VCC
2.2 nH
4.3 pF
I SIG P
T1
RF OUT WB
1 pF
1 kΩ
4.3 pF
I SIG N
1 nF
MODE B
2:1
2.2 nH
5.6 pF
VCC
24
23
22
21
20
19
1
3.9 nH
VCC
18
Note: The die flag is the
chip's main ground.
LO HB
1.8 pF
VCC
2
430 Ω
17
4.3 nH
T2
RF OUT HB
1.6 pF
DIV
2
3
+45°
16
-45°
2:1
LO LB
3 pF
1.6 pF
Σ
22.0 nH
Flo
x2
4
430 Ω
15
+45°
4.3 nH
VCC
-45°
VCC
Mode Control
and Biasing
5
14
Power
Control
12 nH
MODE C
6
3.3 pF
13
7
8
9
10
11
12
RF OUT LB
0.5 pF
1 kΩ
3.3 pF
MODE D
Q SIG N
Q SIG P
T3
10 nF
1 nF
2:1
12 nH
VCC
GC
5-132
Rev A4 041026
RF2705
Evaluation Board Schematic
23
22
21
20
Flo
x2
1
2
C10
1.6 pF
GND
1
OUT
GND
2
GND
Murata
LDB211G8020C-001
6
R3
430 Ω
T2
-45°
VCC
14
8
9
10
11
12
L8
12 nH
C18
0.5 pF
C14
10 nF
C15
1 nF
C17
3.3 pF
R4
1 kΩ
C16
3.3 pF
4
IN
MODE D
L7
12 nH
OUT
IN
7
1
50 Ω µstrip
GND
C8
100 pF
13
J7
LB RF OUT
T3
Murata
LDB21906M20C-001
6
Power
Control
6
J9
Q SIG P
OUT
C5
DNI
J5
HB RF OUT
15
+45°
Mode Control
and Biasing
5
50 Ω µstrip
GND
3
IN
L5
4.3 nH
IN
C9
1.6 pF
Σ
L6
22 nH
L4
4.3 nH
16
-45°
C13
3 pF
J8
Q SIG N
6
3
IN
R2
430 Ω
+45°
5
DIV
2
4
C4
1.8 pF
4
MODE C
Murata
LDB211G9020C-001
50 Ω µstrip
17
3
50 Ω µstrip
T1
VCC
C11
22 pF
2
3
J6
LB LO
J4
WB RF OUT
18
Note: The die flag is the
chip's main ground.
L1
3.9 nH
50 Ω µstrip
C3
4.3 pF
19
1
J3
HB LO
R1
1 kΩ
GND
IN
24
C12
1.3 pF
4
C2
4.3 pF
C6
5.6 pF
L3
2.2 nH
GND
L2
2.2 nH
C1
1 nF
MODE B
2
50 Ω µstrip
50 Ω µstrip
GND
J1
I SIG N
C7
12 pF
GND
50 Ω µstrip
VCC
5
J2
I SIG P
MODE A
5
VCC
50 Ω µstrip
P1-1
1
2
P1-3
3
CON3
Rev A4 041026
P2-1
P1
1
MODE D
P2-2
2
MODE C
P2-3
3
MODE B
P2
GC
VCC
GND
GC
P2-4
MODE A
4
CON4
5-133
RF2705
Evaluation Board Layout
Board Size 2.250” x 2.250”
Board Thickness 0.032”, Board Material FR-4, Multi-Layer
5-134
Assembly
Top
Mid
Back
Rev A4 041026
RF2705
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD’s qualification process is Electroless Nickel, immersion Gold. Typical thickness is
3µinch to 8µinch Gold over 180µinch Nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and
tested for optimized assembly at RFMD; however, it may require some modifications to address company specific
assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land Pattern
A = 0.69 x 0.28 (mm) Typ.
B = 0.28 x 0.69 (mm) Typ.
C = 2.50 (mm) Sq.
2.50 (mm)
Typ.
0.50 (mm) Typ.
Pin 24
B
B
B
B
B
B
Pin 18
Pin 1
A
A
A
A
0.50 (mm) Typ.
A
A
C
A
A
A
A
A
A
1.25 (mm)
Typ.
2.50 (mm)
Typ.
0.57 (mm) Typ.
B
B
B
B
B
B
Pin 12
0.57 (mm) Typ.
1.25 (mm)
Typ.
Figure 1. PCB Metal Land Pattern (Top View)
Rev A4 041026
5-135
RF2705
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the
PCB Metal Land Pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all
pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask
clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.79 x 0.38 (mm) Typ.
B = 0.38 x 0.79 (mm) Typ.
C = 2.60 (mm) Sq.
2.50 (mm)
Typ.
0.50 (mm) Typ.
Pin 24
B
B
B
B
B
B
Pin 18
Pin 1
A
A
A
A
0.50 (mm) Typ.
A
A
C
A
A
A
A
A
A
1.25 (mm)
Typ.
2.50 (mm)
Typ.
0.57 (mm) Typ.
B
B
B
B
B
B
Pin 12
0.57 (mm) Typ.
1.25 (mm)
Typ.
Figure 2. PCB Solder Mask Pattern (Top View)
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of
the device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown
has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
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Rev A4 041026