RF3321 Preliminary 2 REVERSE PATH HIGH OUTPUT POWER PROGRAMMABLE GAIN AMPLIFIER Typical Applications • Euro-DOCSIS/DOCSIS Cable Modems • Home Networks • CATV Set-Top Boxes • Automotive/Mobile Multimedia • Telephony Over Cable • Coaxial and Twisted Pair Line Driver Product Description -A- The RF3321 is a variable gain amplifier for use in CATV reverse path (upstream) applications. It is designed to be DOCSIS-compliant for use in cable modems. The gain control covers a 56dB range and is serially programmable via three-wire digital bus for compatibility with standard baseband chipsets. Amplifier shutdown and transmit disable modes are hardware-controlled. The device operates over the frequency band of 5MHz to 65MHz for use in current U.S. and European systems. The amplifier delivers up to +69dBmV at the output of the balun. Gain is controllable in accurate 1dB steps. The device is provided in a thermally enhanced, exposed die flag package. 3.90 + 0.10 4.90 + 0.20 0.25 + 0.05 0.05 + 0.05 0.65 NOTES: 1. Shaded lead is pin 1. 2. Lead coplanarity - 0.10 with respect to datum "A". 3. Lead standoff is specified from the lowest point on the package underside. Note 3 1.40 + 0.10 6.00 + 0.20 8° MAX 0° MIN LINEAR CATV AMPLIFIERS 3 EXPOSED DIE FLAG 3.302 0.60 + 0.15 0.24 0.20 2.286 Optimum Technology Matching® Applied Si BJT üSi Bi-CMOS GaAs HBT GaAs MESFET SiGe HBT Si CMOS Package Style: SSOP16 EDF Slug Features • Differential Input and Output SHDNB 1 Power Control 16 GND • 31dB Maximum Voltage Gain 15 NC • -25dB Minimum Voltage Gain TX EN 2 NC 3 14 NC • 5MHz to 65MHz Operation VIN 4 13 VOUT • Sophisticated Power Management VINB 5 12 VOUTB • DOCSIS 1.1 RF Compliant VCC1 6 11 SDA VCC1 7 10 CS RAMP 8 9 SCLK Gain Control and Serial Bus Ordering Information RF3321 RF3321 PCBA Functional Block Diagram Rev A10 010516 Reverse Path High Output Power Programmable Gain Amplifier Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 2-1 RF3321 Preliminary Absolute Maximum Ratings Parameter LINEAR CATV AMPLIFIERS 3 Supply Voltage (VCC1) Supply Voltage (VCC2) Input RF Level Operating Ambient Temperature Storage Temperature Humidity Maximum Power Dissipation Maximum TJ Parameter Rating Unit -0.5 to +5.5 -0.5 to +7.5 12 -40 to +85 -40 to +150 80 0.5 150 VDC VDC dBm °C °C % W °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit Overall Condition VCC1 =5V, VCC2 =7V, TXEN=SHDNB=1, VIN =38dBmV (rms) differential, output impedance=75Ω through a 2:1 transformer. Typical performance is at TA =+25°C, VCC =5V. DC Specifications Supply Voltage 1 (VCC1) Supply Voltage 2 (VCC2) Supply Current Maximum Gain, SV1 Maximum Gain, SV2 Low Gain, SV1 Low Gain, SV2 Transmit Disable Shut Down Logic High Voltage Logic Low Voltage Logic Leakage Current 4.75 6.65 5.0 7.0 5.25 7.35 V V 85 135 75 55 25 5 100 150 90 70 35 mA mA mA mA mA mA V V µA Gain Control Word=56, VCC2 =5V or 7V Gain Control Word=56, VCC2 =5V or 7V Gain Control Word<28, VCC2 =5V or 7V Gain Control Word<28, VCC2 =5V or 7V TXEN=0, VCC2 =5V or 7V SHDNB=0, VCC2 =5V or 7V -23 dB dB MHz Gain Control Word=56, VCC2 =5V or 7V Gain Control Word=0, VCC2 =5V or 7V Intended operating range is 5MHz to 65MHz. 40 69 dBmV(rms) dBmV(rms) -56 65 -50 dBmV dBc 1.0 1.1 dB -35 -30 Minimum Gain -50 -45 Transmit Disabled -75 -70 TX EN Enable Time 0.5 1.0 dBmV/ 160kHz dBmV/ 160kHz dBmV/ 160kHz µS 2 0.8 1 -1 Main chip supply Output stage supply AC Specifications Voltage Gain Maximum Minimum Bandwidth 29 31 -25 100 Maximum Input Level Maximum Output Level Output Harmonic Distortion Output Step Size Output Noise Maximum Gain TX EN Transient Duration 2-2 0.8 2.4 3.0 µS Into 75Ω load at balun output (CW), VCC2 =7V VCC2 =5V Output Level=68dBmV (rms) (CW) Maximum Gain, VCC2 =5V or 7V VCC2 =5V or 7V VCC2 =5V or 7V TXEN=0, VCC2 =5V or 7V Time for gain to reach 99% of final value. See Note 1. See Note 1. Rev A10 010516 RF3321 Preliminary Parameter Specification Min. Typ. Max. Unit 10 5 300 mVP-P mVP-P Ω Condition AC Specifications, cont’d Input Impedance 20 7 75 Ω 28 °C/W Chip output impedance is nominally 300Ω. Differential to single-ended output conversion to 75Ω is performed in a balun with a 2:1 turns ratio, corresponding to a 4:1 impedance ratio. Differential Thermal ThetaJC Note 1: The enable time is determined by the value of the capacitor on pin 8 (RAMP). A higher capacitor value will increase the enable time, but will reduce the transient voltage . Rev A10 010516 2-3 3 LINEAR CATV AMPLIFIERS Output Switching Transients Maximum Gain Minimum Gain Output Impedance RF3321 Pin 1 Function SHDNB 2 TX EN 3 4 NC VIN Preliminary Description Interface Schematic Chip shutdown pin. Forcing a logic low causes all circuits to switch off and gain settings to be lost. Signal path enable pin. Logic high turns on signal path. Logic low turns off signal path, but leaves serial bus active. Not connected. Input pin. This should be externally AC-coupled to signal source. VCC 550 Ω 3 550 Ω LINEAR CATV AMPLIFIERS 500 Ω 500 Ω VIN 5 VINB 6 7 8 9 10 11 12 VCC1 VCC1 RAMP SCLK CS SDA VOUTB VINB Complementary input pin. This should be externally coupled to signal See pin 4. source. For single-ended use, this pin should be AC-coupled to ground. This pin is connected to VCC1. Same as pin 6. External capacitor to ground controls start-up time. Serial bus clock input. Serial bus enable. Serial bus data input. Open collector output. Connect to VCC2 via balun primary. VOUT VOUTB 300 Ω RE 13 14 15 16 PKG BASE VOUT NC NC GND GND Open collector output. Connect to VCC2 via balun primary. See pin 12. Same as pin 3. Same as pin 3. Connect to ground. Die is mounted on a heat sink slug that should be connected to ground. Device grounds are internally bonded to the slug. Serial Bus Block Diagram D6 D Q D5 D Q D4 D Q D3 D Q D2 D Q D1 D Q CK CLR CK CLR CK CLR CK CLR CK CLR CK CLR D D D D D D D0 D Q CK CLR CS POR SDA D Q CK CLR Q CK CLR Q CK CLR Q CK CLR Q CK CLR Q CK CLR Q CK CLR SCLK 2-4 Rev A10 010516 RF3321 Preliminary Table 1. Serial Interface Control Word Format Bit Mnemonic Description MSB 6 5 4 3 2 1 LSB 0 D6 D5 D4 D3 D2 D1 D0 Sleep Mode (Software Shutdown) Gain Control, Bit MSB Gain Control, Bit 4 Gain Control, Bit 3 Gain Control, Bit 2 Gain Control, Bit 1 Gain Control, Bit LSB 3 Serial Bus Timing Diagram TDATAH,TDATAL TDS TWH TDH TEH LINEAR CATV AMPLIFIERS TES TC CS SCLK SDA (Data) D0 D1 D2 D3 D4 D5 D6 Table 2. Timing Data Parameter SCLK Pulsewidth SCLK Period Setup Time, SDA versus S CLK Setup Time, CS versus S CLK Hold Time, SDA versus S CLK Hold Time, CS versus S CLK SCLK Pulsewidth, High SCLK Pulsewidth, Low Symbol Min TWH TC TDS TES TDH TEH TDATAH TDATAL 50 100 10 10 20 20 50 50 Typ Max Units ns ns ns ns ns ns ns ns Table 3. Programming State Enter Sleep Mode Exit Sleep Mode Enter Shutdown Exit Shutdown TX Enable TX Disable Rev A10 010516 TX SHDND MSB6 X X X X H L H H L H X X L H* X H* X X H=High Voltage Logic L=Low Voltage Logic X=Don’t Care *Gain Control Data Must be Re-Sent 2-5 RF3321 Preliminary Application Schematic SHDNB 1 TXEN 2 16 Power Control 15 3 14 4 13 5 12 6 11 VCC2 10 nF VIN 3 4:1 VOUT 10 nF LINEAR CATV AMPLIFIERS VINB VCC1 7 Gain Control and Serial Bus 9 8 220 pF 2-6 10 PACKAGE BASE 100 pF SDA CS SCLK Rev A10 010516 RF3321 Preliminary Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) R7 R8 Q1 J3-1 R1 100 kΩ VCC R2 100 kΩ NC CS SDA SCLK SHDNB TXEN 7 8 9 10 11 12 NC NC NC VCC 13 14 15 16 17 18 NC NC VCC NC NC GND 19 20 21 22 23 24 GND GND GND GND GND GND 25 GND J1-6 TXEN 1 1 2 2 3 3 J1-5 SHDNB 1 1 2 2 3 3 VCC J6 RF IN 3 4 2 5 1 6 R4 75 Ω L2 (Ferrite) 30 Ω L1 (Ferrite) 30 Ω 1 VCC 9V 2 VCC2 3 VCC1 4 GND 3 VCC L3 (Ferrite) 30 Ω VCC C2 1 nF VCC1 + C1 10 µF (10 V) GND C3 1 nF 16 Power Control 15 C7 15 pF 13 VCC1 5 12 6 11 7 C5 0.1 µF Gain Control and Serial Bus 9 8 Notes: 3321400C 1. 4-layer board. 2. Underside of package must solder to ground. 3. Place C5 and C6 as close to pin as possible. 4. C1 and C10 are tantalum, size code Y. 5. All other components are 0603 size. 6. Replace R6 with 0 Ω resistor if 75 Ω connector is used. 10 PACKAGE BASE R6 24 Ω T2 4:1 VCC C4 1 nF VCC2 14 3 4 C6 220 pF Rev A10 010516 C10 10 µF (10 V) GND 2 T1 1:1 JP1 + C11 1 nF 1 R5 75 Ω L5 (Ferrite) 30 Ω VCC2 J4 J5 NC L4 (Ferrite) 30 Ω J2 J3 LINEAR CATV AMPLIFIERS CS SDA SCLK J5-1 J1 1 2 3 4 5 6 C8 15 pF 3 4 2 5 1 6 J7 RF OUT C9 100 pF SDA CS SCLK 2-7 RF3321 Preliminary Evaluation Board Layout Board Size 2.5” x 2.5” Board Thickness 0.058”, Board Material FR-4, Multi-Layer LINEAR CATV AMPLIFIERS 3 2-8 Rev A10 010516 RF3321 Preliminary Gain versus Frequency 30.0 Gain versus Supply Voltage (VCC1) at Gain Control Word = 56 29.2 29.1 20.0 29.0 Gain Control Word = 25 Gain Control Word = 0 0.0 5 MHz 42 MHz 65 MHz 28.9 Gain Control Word = 56 Voltage Gain (dB) -10.0 28.8 28.7 3 28.6 28.5 -20.0 LINEAR CATV AMPLIFIERS Voltage Gain (dB) 10.0 28.4 -30.0 28.3 -40.0 0 50 100 150 200 28.2 4.70 250 4.80 4.90 Frequency (MHz) Gain versus Supply Voltage (VCC1) at Gain Control Word = 25 0.0 5.00 5.10 5.30 Gain versus Supply Voltage (VCC2) at Gain Control Word = 56 29.2 5 MHz 42 MHz 65 MHz -0.2 29.1 -0.4 29.0 5 MHz 42 MHz 65 MHz Voltage Gain (dB) -0.6 Voltage Gain (dB) 5.20 Supply Voltage VCC1 (V) -0.8 -1.0 -1.2 28.9 28.8 28.7 28.6 -1.4 28.5 -1.6 28.4 -1.8 -2.0 4.70 4.80 4.90 5.00 5.10 5.20 5.30 Supply Voltage VCC1 (V) 28.3 6.65 6.75 6.85 6.95 7.05 7.15 7.25 7.35 Supply Voltage VCC2 (V) Gain versus Supply Voltage (VCC2) at Gain Control Word = 25 0.0 5 MHz 42 MHz 65 MHz -0.2 -0.4 Voltage Gain (dB) -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 6.65 6.75 6.85 6.95 7.05 7.15 7.25 7.35 Supply Voltage VCC2 (V) Rev A10 010516 2-9 RF3321 Preliminary LINEAR CATV AMPLIFIERS Gain versus Gain Control Word at 42 MHz 20.0 20.0 10.0 10.0 Voltage Gain (dB) 30.0 0.0 -10.0 -20.0 0.0 -10.0 -20.0 -30.0 -30.0 0 10 20 30 40 50 0 10 20 Gain Control Word 30 40 50 Gain Control Word Gain versus Gain Control Word at 65 MHz Second Harmonic versus Frequency and Output Level -30 30.0 65 MHz 42 MHz 5 MHz 20.0 Voltage Gain (dB) -40 Second Harmonic (dBc) 3 Voltage Gain (dB) Gain versus Gain Control Word at 5 MHz 30.0 10.0 0.0 -10.0 -50 -60 -70 -20.0 -30.0 -80 0 10 20 30 40 30 50 Gain Control Word 35 40 45 50 55 60 Output Level (dBmV) Third Harmonic versus Frequency and Output Level -50 65 MHz 42 MHz 5 MHz Third Harmonic (dBc) -55 -60 -65 -70 -75 -80 30 35 40 45 50 55 60 Power Out (dBmV) 2-10 Rev A10 010516 RF3321 Preliminary -1 dB Compression Point at Gain Control Word = 56 -1 dB Compression Point at Gain Control Word = 29 72.0 44.0 Gain Control Word = 56 Gain Control Word = 29 43.0 Trend Trend 70.0 66.0 64.0 41.0 40.0 3 39.0 38.0 37.0 62.0 36.0 60.0 33.0 35.0 37.0 39.0 Power In (dBmV) Rev A10 010516 41.0 43.0 45.0 35.0 38.0 39.0 40.0 41.0 42.0 43.0 44.0 45.0 46.0 47.0 Power In (dBmV) 2-11 LINEAR CATV AMPLIFIERS 68.0 Power Out (dBmV) Power Out (dBmV) 42.0 RF3321 Preliminary Evaluation Kit LINEAR CATV AMPLIFIERS 3 General Description The RF3321 PCBA is a fully assembled evaluation board of the RF3321 reverse path high output power programmable gain amplifier, useful for providing a demonstration of the RF3321’s functionality. The RF3321 PCBA is a digitally controlled variable gain amplifier capable of driving a 75Ω source. The RF3321 is designed to send cable modem data with QPSK or QAM modulated format at frequencies between 5MHz and 65MHz. The gain is controlled by an 7-bit serial data word which adjusts the output gain from -25dB to +31dB. The kit includes a fully functional evaluation board along with a serial data cable and software. The cable connects directly to the parallel port of a standard PC. The software is used to control the serially programmable gain through a simple, easy to understand user interface. Input and output to the evaluation board is provided through 50Ω SMA connectors. The input and output of the evaluation board is matched to 50Ω and connected through a balun for single-ended operation. This allows easy connection to test equipment, but the evaluation board can easily be converted to a 75Ω input and output, or for differential input and output. The output circuit is matched using a 24Ω series resistor which is used to bring the load impedance up to 75Ω when using standard 50Ω test equipment. This will introduce a loss which must be accounted for in all measurements (see measurement section and evaluation board schematic for more detail.) PCBA Details Input Circuit The input to the RF3321 is differential and the impedance is 75Ω; However, for ease of testing, the evaluation board has been changed to single-ended and the impedance has been matched to 50Ω. If a 75Ω input is required, simply replace the 50Ω SMA connector with a 75Ω F-style connector and remove R4 and R5. device to 75Ω. This introduces a voltage loss of 3.5dB which must be accounted for in all measurements. Some spectrum analyzers have a setting to account for this method of 75Ω testing (e.g., on a Rhode & Schwartz spectrum analyzer the input can be set to '”75Ω RAZ” and the loss is accounted for automatically). A more accurate way of making this measurement is to use a 75Ω spectrum analyzer, or use a matching transformer or minimum loss pad. This ensures that the source impedance seen by the equipment is also 75Ω. If a 75Ω output is required, simply replace the 50Ω SMA connector (J7) with a 75Ω Fstyle connector and replace R5 with a 0Ω jumper. The evaluation board is tested with a Coilcraft balun; however, additional baluns may be used as long as care is taken in modifying the decoupling capacitors around the balun. These capacitors can greatly affect the harmonic suppression. Other baluns may be used but should be tested for second and third order harmonic suppression. Transmit Enable The transmit enable can be set to “continuous on” by placing the TXEN jumper in the up position (up position when viewing the top of the evaluation board with the 25-pin connector closest to the viewer) and placing the associated GND/VCC jumper in the “VCC” position. The transmit enable can be set to “continuous off” by placing the GND/VCC jumper in the “GND” position. If a computer controlled signal is used (J1), place the TXEN jumper in the down position. GND VCC TX EN Continuous ON A GND VCC TX EN Continuous OFF B GND VCC TX EN Software Controlled C Figure 1. TX Enable Configuration Output Circuit The output of the RF3321 is differential and the impedance is 300Ω. In normal applications this is converted into a single-ended 75Ω output using a 2:1 (voltage ratio) transformer with a center-tap on the secondary which supplies power to the output stage. The evaluation board is configured for use with 50Ω test equipment. This has been achieved with a 24Ω resistor in series with the output to increase the load seen by the 2-12 Rev A10 010516 RF3321 Shutdown Enable Shutdown enable can be set to be “continuous on” (chip enabled) by placing the SHDN jumper in the up position and placing the associated GND/VCC jumper in the “VCC” position. Shutdown enable can be set to “continuous off” (chip disabled) by placing the associated GND/VCC jumper in the “GND” position. If a computer controlled signal is used (J1), place the SHDN jumper in the down position. VCC GND SHDN Continuous OFF A VCC GND SHDN Continuous ON B VCC GND SHDN Software Controlled C Figure 2. SHDN Enable Configuration VCC Settings VCC1 should be set to 5.0VDC. VCC2 should be set to 7.0VDC. Evaluation Board Setup Equipment Needed • Signal Generator • Spectrum Analyzer • Power Supply (5.0V@300mA) • RF3321 PCBA • Serial Cable (included with kit) • Standard PC • Three-Wire Bus Software Optional Equipment • Variable Low-Pass or Band-Pass Filters • Power Meter • Second Signal Generator with Modulation for ACPR and IP2, IP3 Testing • Arbitrary Wave Generator • Two-Channel Oscilloscope Unzip the file using WinZip 7.0 or higher (http:// www.winzip.com). Unzip to a temporary directory and run RF3321.exe. The 7-bit Gain Control Word (GCW) in the data latch determines the gain setting in the RF3321. The gain control data (SDA) load sequence is initiated by a falling edge on CS. The SDA is serially loaded (LSB first) into the 7-bit shift register at each rising edge of the clock. While CS is low, the data latch holds the previous data word allowing the gain level to remain unchanged. After seven clock cycles the new data word is fully loaded and CS is switched high. This enables the data latch and the loaded register data is passed to the gain control block with the updated gain value. Also at this CS transition, the internal clock is disabled, thus inhibiting new serial input data. Software and Cable Figure 3 shows the cable configuration. Connect the cable into the LPT1 port of the computer running the software. Connect the other end of the cable to the 25pin connector of the evaluation board. Executing the software (RF3321.exe) will produce the screen shown in Figure 4. The user may set the gain of the evaluation board by sliding the gain control switch to the desired gain setting. Pressing the Preset Gain Value buttons automatically sets the gain of the unit to the value shown on the button. The Automatic Gain Adjustment when set to “Cycle” will automatically cycle through all of the gain steps (0-56) in seconds (at the rate set by the user). The user may place the unit in sleep, shutdown and transmit enable/disable modes by checking the corresponding box. The bit pattern being sent to the PCBA is shown at the bottom of the screen. See README_3321.txt file for proper pin/signal mapping for the 25 pin interface. Software Setup To install the software, you need a computer with the following. • 133MHz Pentium processor • 16MB RAM • Hard Drive with 5MB free space • Free 25-pin LPT port • VGA Monitor The software may be downloaded from www.rfmd.com by following these steps. Select the “Product Support” tab; Select “Evaluation Board Information”; Select “RF3321”. Rev A10 010516 2-13 3 LINEAR CATV AMPLIFIERS Preliminary RF3321 Preliminary RF3321 PCBA Cable Ground 6 TX Enable Line 5 SHUTDOWN Line 4 CLK Line 3 Data Line 2 CS Line LINEAR CATV AMPLIFIERS 3 18 25 Pin D-Connector (Back View) Figure 3. Cable Configuration Hardware Setup Gain and Harmonic Distortion Test Setup To test the gain of the RF3321 PCBA, connect a lowpass or band-pass filter to the output of the signal generator. Use a filter just above the frequency you want to test. The filter is used to attenuate any harmonics output by the signal generator. Connect the signal generator to the power meter and measure the power. Compare with modulation enabled and disabled to make sure the meter was measuring average rather than peak power. No more than 0.2dB difference in power should be observed. An offset on the signal generator may be needed to match the level shown on the power meter. The signal generator should then be connected directly to a spectrum analyzer. Make sure the output of the signal generator is the same as the input read by the spectrum analyzer. Adjust the offset of the spectrum analyzer until the signal out is the same as the signal in on the spectrum analyzer. Turn off the RF and modulation. Check positioning of the jumpers on the board. Refer to the PCBA section of this application note to verify proper positions. Connect the output of the signal generator to J6: RFIN of the PCB. Connect J7: RFOUT to the spectrum analyzer. Ensure that Rev A10 010516 Figure 4. On-Screen Display you are accounting correctly for the losses in the 75Ω to 50Ω conversion at the output of the device; there is an output voltage loss of 3.5dB for the evaluation board in its standard configuration (see output stage circuit description). Connect one end of the serial cable into the computer and the other end into J1 of the PCB. Connect +5.0VDC into V+ and ground into GND(JP1). Turn on the DC power and turn on RF from the signal generator. Set the GCW to 56 and make sure TX Enable is checked. The amplified signal should be displayed on the spectrum analyzer. The harmonics can also be viewed with this setup. As you change the GCW from 56 to 0 (in steps of one), there will be a 1dB change in the output of the PCB. 2-14 ACPR Test Setup To test the ACPR of the RF3321 PCBA set modulation to: • QPSK • 2Bits/Sym • 160ksps • α=0.25 • PRBS-20bit Data Set signal generator to: • 45MHz, • -13.0dBm output power, • 0dB offset. Connect 50MHz coaxial filter to output, then to output cable. Zero and calibrate the power meter. Connect signal generator to power meter and set offset on signal generator until power meter reads -13.0dBm. Make sure power meter reads the same (±0.2dBm) with modulation enabled and disabled to verify power meter is measuring average power rather than peak power. Check positioning of the jumpers on the board. Refer to the PCBA section of this application note to verify proper positions. Connect the output of the signal generator to J6: RFIN of the PCB. Connect J7: RFOUT to the power meter. Connect one end of the serial cable into the computer and the other end into P1 of the PCB. Connect +5.0VDC into VCC and ground into GND. Turn on the DC power and turn on RF and modulation from the signal generator. Set the GCW to 56 and make sure TX Enable is checked. Measure and record channel power at RFOUT using the power meter (accounting for 75/50 conversion losses). Connect RFOUT to spectrum analyzer and adjust offset of the spectrum analyzer until the channel power displayed by the spectrum analyzer is equal to the channel power recorded in the previous step (Channel bandwidth = 200kHz). Now use the spectrum analyzer to measure relative ACP (this way the uncertainties in the spectrum analyzer power measurement are immaterial). The ACP is measured in 200kHz channel bandwidths at a 220kHz offset (i.e., from 20kHz to 220kHz outside the channel). As you increase the input power, you will notice a degradation of the ACP upper and lower bands. Rev A10 010516 RF3321 Transmit Turn-On and Turn-Off Transients Use an Arbitrary Waveform Generator set to a 3V square wave, 5% duty cycle, 120Hz as the input to the transmit enable. Set a signal generator to 10MHz, -13.0dbm output power, 0dB offset. Connect output of the signal generator to J6, RFIN of the PCB. Remove the TXEN jumper and connect the arbitrary wave generator square wave output to the center pin of the TXEN 3-pin header. Connect the output of the evaluation board to the oscilloscope (channel 1). Connect the TXEN signal from the arbitrary wave generator to channel 2 of the oscilloscope and trigger off of the rising edge. As the TXEN line is sent, the oscilloscope will trigger and capture the pulsed RFOUT signal. This will be displayed on the oscilloscope. Measure the amount of time between 90% of the TXEN turn-on to where the output signal reaches 90% of full turn-on. This is defined as the transmit turn-on time. To measure the transient pulse, replace the signal generator input with a 50Ω terminator and repeat the steps above. Measure the size of the transient. This can be affected by the CRAMP capacitor (C6), and the output balun and capacitor values around the balun. Larger values of CRAMP will decrease the transient voltage and increase the TX enable time. PCB Layout Considerations The RF3321 Evaluation board can be used as a guide for the layout in your application. Care should be taken in laying out the RF3321 in other applications. The RF3321 will have similar results if the following guidelines are taken into consideration: • Make sure underside of package is soldered to a good ground on the PCB. • Move C2, C7, C8, and C9 as close to T1 as possible. • Keep input and output traces as short as possible. • Ensure a good ground plane by using multiple vias to the ground plane. • Use a low noise power supply along with decoupling capacitors 2-15 3 LINEAR CATV AMPLIFIERS Preliminary Preliminary RF3321 Special Handling Information for Shrunk Small Outline Package (SSOP1-EPP) Products These packages are considered JEDEC Level 5 for moisture sensitivity and require special handling to assure reliable performance. The exposed copper slug on the bottom of the package improves both thermal and electrical performance. Since the RFIC is mounted directly on the thermal slug, and the slug is soldered directly on the PCB, the thermal resistance to the PCB is minimized. Also, the RF ground for the amplifier is established through this copper slug as it is soldered to the ground plane on the PCB. This offers the least inductance ground path available. LINEAR CATV AMPLIFIERS 3 Care must be taken when soldering these packages to the PCB. They are currently considered JEDEC Level 5 for moisture sensitivity. Therefore the parts must be handled in a dry environment prior to soldering, as is specified in the JEDEC specification. Specifically, RFMD recommends the following procedure prior to assembly: 1. Dry-bake the parts at 125°C for 24 hours minimum. Note: the shipping tubes cannot withstand 125°C baking temperature. 2. Parts delivered on tape and reel are already drybaked and dry-packed. These may be stored for up to one year, but must be assembled within 48 hours after opening the bag. 3. Assemble the dry-baked parts within two days of removal from the oven. 4. During this two-day period, the parts must be stored in humidity less than 60%. IMPORTANT! If the two-day period is exceeded, then this procedure must be repeated prior to assembly. Rev A10 010516 2-16