SCES581 − JULY 2004
D Available in Texas Instruments NanoStar
D
D
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
and NanoFree Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
One Unbuffered Inverter (SN74LVC1GU04)
and One Buffered Inverter (SN74LVC1G04)
Suitable for Commonly Used Clock
Frequencies:
− 15 kHz, 3.58 MHz, 4.43 MHz, 13 MHz,
25 MHz, 26 MHz, 27 MHz, 28 MHz
Max tpd of 2.4 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
NC
GND
X1
1
6
2
5
3
4
Y
VCC
X2
NC − No internal connection
YEP OR YZP PACKAGE
(BOTTOM VIEW)
X1
GND
DNU
3 4
2 5
1 6
X2
VCC
Y
DNU − Do not use
description/ordering information
The SN74LVC1GX04 is designed for 1.65-V to 5.5-V VCC operation. This device incorporates the
SN74LVC1GU04 (inverter with unbuffered output) and the SN74LVC1G04 (inverter) functions into a single
device. The LVC1GX04 is optimized for use in crystal oscillator applications.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40 C to 85°C
85 C
−40°C
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
TOP-SIDE
MARKING‡
SN74LVC1GX04YEPR
Reel of 3000
___ _
SN74LVC1GX04YZPR
Reel of 3000
SN74LVC1GX04DBVR
Reel of 250
SN74LVC1GX04DBVT
Reel of 3000
SN74LVC1GX04DCKR
Reel of 250
SN74LVC1GX04DCKT
CX4_
D2_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
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1
SCES581 − JULY 2004
description/ordering information (continued)
The X1 and X2 can be connected to a crystal or resonator in oscillator applications. The device provides an
additional buffered inverter (Y) for signal conditioning (see Figure 3). The additional buffered inverter improves
the signal quality of the crystal oscillator output by making it rail to rail.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff (Y output only). The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUT
X1
OUTPUTS
X2
Y
H
L
H
L
H
L
logic diagram (positive logic)
6
X1
3
4
Y
X2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to Y output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES581 − JULY 2004
recommended operating conditions (see Note 4)
Operating
VCC
Supply voltage
Data retention only
Crystal oscillator use
VIH
VIL
High-level input voltage
VI
Input voltage
VO
Output voltage
Low-level input voltage
VCC = 1.65 V to 5.5 V
VCC = 1.65 V to 5.5 V
High-level output current
∆t/∆v
Input transition rise or fall rate
5.5
1.5
V
2
0.75 × VCC
V
0.25 × VCC
V
V
X2, Y
0
Y output only, Power-down mode, VCC = 0 V
0
VCC
5.5
V
−4
−8
−16
VCC = 3 V
mA
−24
−32
4
VCC = 2.3 V
Low-level output current
1.65
UNIT
5.5
VCC = 4.5 V
VCC = 1.65 V
IOL
MAX
0
VCC = 1.65 V
VCC = 2.3 V
IOH
MIN
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
32
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
10
20
ns/V
10
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCES581 − JULY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 mA
IOH = −4 mA
MIN
1.65 V to 5.5 V
VCC − 0.1
1.2
1.65 V
IOH = −8 mA
IOH = −16 mA
VOH
2.3 V
IOL = 100 mA
IOL = 4 mA
0.1
1.65 V
0.45
2.3 V
0.3
VI = 5.5 V or GND
0.4
3V
X1, Y
ICC
Ci
VI = 5.5 V or GND
VI or VO = 5.5 V
0.55
0 to 5.5 V
0
VI = 5.5 V or GND,
VI = VCC or GND
IO = 0
V
0.55
4.5 V
IOL = 32 mA
X1 input
3.8
1.65 V to 5.5 V
IOL = 24 mA
II
Ioff
2.3
4.5 V
IOH = −32 mA
UNIT
V
2.4
3V
IOL = 8 mA
IOL = 16 mA
MAX
1.9
VI = 5.5 V or GND
IOH = −24 mA
VOL
TYP†
VCC
1.65 V to 5.5 V
3.3 V
±5
mA
±10
mA
10
mA
7
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
tpd
TO
(OUTPUT)
X1
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
X2
1
4
0.8
2.6
0.6
2.4
0.5
2
Y‡
3.5
10
2.2
6
2
5
1.5
3.5
UNIT
ns
‡ X2 − no external load
switching characteristics over recommended operating free-air temperature range, CL = 30 pF or
50 pF (unless otherwise noted) (see Figure 2)
FROM
(INPUT)
PARAMETER
tpd
TO
(OUTPUT)
X1
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
X2
1.1
7
0.8
4
0.8
3.7
0.8
3
ns
Y‡
3.8
18
2
7.4
2
7.8
2
5
ns
‡ X2 − no external load
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
22
• DALLAS, TEXAS 75265
22
VCC = 3.3 V
TYP
24
VCC = 5 V
TYP
35
UNIT
pF
SCES581 − JULY 2004
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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SCES581 − JULY 2004
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
CL
(see Note A)
VLOAD
Open
S1
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VOH
VM
Output
VM
VOL
tPHL
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VM
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
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SCES581 − JULY 2004
APPLICATION INFORMATION
Figure 3 shows a typical application of the SN74LVC1X04 in a Pierce oscillator circuit. The buffered inverter
(SN74LVC1G04 portion) produces a rail-to-rail voltage waveform. The recommended load for the crystal shown in
this example is 16 pF. The value of the recommended load (CL) can be found in the crystal manufacturer’s data sheet.
C 1C 2
and C1 ≅ C2. Rs is the current-limiting resistor and the value
Values of C1 and C2 are chosen so that C +
L
C1 ) C2
depends on the maximum power dissipation of the crystal. Generally, the recommended value of Rs is specified in
the crystal manufacturer’s data sheet and, usually, this value is approximately equal to the reactance of C2 at
resonance frequency, i.e., R s + X C . RF is the feedback resistor that is used to bias the inverter in the linear region
2
of operation. Usually, the value is chosen to be within 1 MΩ to 10 MΩ.
SN74LVC1GU04
Portion
SN74LVC1G04
Portion
Y
X2
X1
CLOAD
RLOAD
RF ≅ 2.2 MΩ
CL ≅ 16 pF
C1 ≅ 32 pF
Rs ≅ 1 kΩ
C2 ≅ 32 pF
a) Logic Diagram View
Figure 3. Oscillator Circuit
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7
SCES581 − JULY 2004
APPLICATION INFORMATION
6
1
NC
Y
CLOAD
GND
X1
2
5
3
4
RLOAD
VCC
X2
RF ≅ 2.2 MΩ
CL = 16 pF
C1 ≅ 32 pF
Rs ≅ 1 kΩ
C2 ≅ 32 pF
b) Oscillator Circuit in DBV or DCK Pinout
Figure 3. Oscillator Circuit (Continued)
practical design tips
D The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This
decreases the closed-loop gain of the oscillator circuit. The value of Rs can be decreased to increase the
closed-loop gain, while maintaining the power dissipation of the crystal within the maximum limit.
D Rs and C2 form a low-pass filter and reduce spurious oscillations. Component values can be adjusted,
based on the desired cutoff frequency.
D C2 can be increased over C1 to increase the phase shift and help in start-up of the oscillator. Increasing C2
may affect the duty cycle of the output voltage.
D At high frequency, phase shift due to Rs becomes significant. In this case, Rs can be replaced by a capacitor
to reduce the phase shift.
8
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SCES581 − JULY 2004
APPLICATION INFORMATION
testing
After the selection of proper component values, the oscillator circuit should be tested using these components.
To ensure that the oscillator circuit performs within the recommended operating conditions, follow these steps:
1. Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its
equivalent parallel-resonant resistance.
2. When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the
circuit oscillates at the appropriate frequency at the lowest VCC and highest VCC.
3. Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements.
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9
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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