SAMES SA2532K

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AN1500A
APPLICATION NOTE
SINGLE CHIP TELEPHONE DEMO BOARD
SA2532K
1 Scope
This application note describes the use of the SA2532K Single Chip Telephone IC developed specifically to meet
with India’s Department of Telecommunication (DOT) Specification for the Electronic Telephone Instruments. This
application note is based on the use of the multi-purpose demo board DB1500I with the SA2532K IC
2 Key Features
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High performance telephone with speech circuit, DTMF/Pulse dialer and tone ringer
Very few external low cost components
CMOS technology, far less sensitive to EMC
EMC proof single sided layout, provision for EMC blocking capacitors installed
Internally set real AC impedance to reduce external components
Sidetone programmable by two resistors and one capacitor
Ring frequency discrimination
Line loss compensation selectable by jumper
2 different flash timings selectable by 2 flash keys
31 digit last number redial
Sliding cursor protocol and pause key
One-touch repeat dialing
1 direct memory
Tone / Pulse switch
Modular connectors for handset and line cord, line connector a/b- terminals selectable by jumper
Layout prepared for 16kHz blocking filters
19-key SPST Keyboard on board
Tone LED output Indicator
Several hook transistor configurations
Over-voltage and over-current circuit options
AN1500A
PDS038-SA2532K-001
Rev. C
21-03-00
AN1500A
TABLE OF CONTENTS
1
SCOPE................................................................................................................................................................. 1
2
KEY FEATURES ................................................................................................................................................. 1
3
OTHER APPLICABLE DOCUMENTS AND PAPERS ........................................................................................ 4
4
REVISION STATUS............................................................................................................................................. 4
5
SA2532K PIN LAYOUT . ..................................................................................................................................... 4
6
GENERAL DESCRIPTION .................................................................................................................................. 5
7
DEMO BOARD CONFIGURATION..................................................................................................................... 5
7.1 SETTING A/B LINE CONNECTION........................................................................................................................ 6
7.2 CONNECTING A HANDSET ................................................................................................................................ 6
7.3 SETTING DIALING MODE ................................................................................................................................... 6
7.4 SETTING LINE LOSS COMPENSATION (AGC)...................................................................................................... 6
7.5 AC IMPEDANCE ............................................................................................................................................... 6
8 DESCRIPTION OF KEYBOARD FUNCTIONS................................................................................................... 7
8.1 NUMERIC KEYS ............................................................................................................................................... 7
8.2 FLASH KEYS (R,R2) ........................................................................................................................................ 7
8.3 LAST NUMBER REDIAL KEY (LNR) .................................................................................................................... 7
8.4 PAUSE KEY (PAUSE)...................................................................................................................................... 7
8.5 TONE / PULSE SWITCHING ............................................................................................................................... 7
8.6 ENTER/M5...................................................................................................................................................... 7
9 USING THE SA2532K ......................................................................................................................................... 8
10
SLIDING CURSOR PROTOCOL AND PAUSE INSERTION .......................................................................... 9
11
AC IMPEDANCE OF THE SA2532K ............................................................................................................... 9
11.1 DEMO BOARD MEASUREMENTS: ....................................................................................................................... 9
11.1.1
Definition:............................................................................................................................................... 9
11.1.2
Measurement:...................................................................................................................................... 10
12
SIDETONE CANCELLATION........................................................................................................................ 10
12.1 DUAL SOFT CLIPPING: ................................................................................................................................... 11
12.2 SIDE TONE BALANCE NETWORK:..................................................................................................................... 11
12.3 EXAMPLE: ..................................................................................................................................................... 11
13
THE DOUBLE WHEATSTONE PRINCIPLE ................................................................................................. 11
13.1 SIDETONE CANCELLATION.............................................................................................................................. 12
13.2 AC IMPEDANCE ............................................................................................................................................. 12
14
FURTHER ADJUSTMENTS .......................................................................................................................... 13
14.1 FREQUENCY RESPONSE SHAPING: TRANSMIT ................................................................................................. 13
14.1.1
Microphone gain setting....................................................................................................................... 13
14.1.2
Tx frequency shaping: ......................................................................................................................... 13
14.2 FREQUENCY RESPONSE SHAPING: RECEIVE ................................................................................................... 14
14.2.1
Receive gain setting: ........................................................................................................................... 14
14.2.2
Rx frequency shaping.......................................................................................................................... 14
14.2.3
Metering pulses filtering....................................................................................................................... 14
15
OFF-HOOK CONDITIONS & DC MASK ...................................................................................................... 15
15.1 LINE CURRENT PATH...................................................................................................................................... 15
15.2 DC MASK PATH ............................................................................................................................................. 15
15.2.1
Setting for low DC mask: ..................................................................................................................... 15
15.3 SPEECH MODE .............................................................................................................................................. 16
15.4 DTMF DIALING ............................................................................................................................................. 16
15.5 PULSE DIALING.............................................................................................................................................. 16
15.6 PRE-DIGIT, INTER-DIGIT ,INTER-TONE AND ACCESS PAUSES ............................................................................ 17
16
HOOK TRANSISTOR OPTIONS ................................................................................................................... 17
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AN1500A
16.1 ELECTRICAL REQUIREMENTS .......................................................................................................................... 17
16.2 SINGLE BIPOLAR TRANSISTOR ........................................................................................................................ 17
16.3 BIPOLAR DARLINGTON TRANSISTOR ............................................................................................................... 18
16.4 VMOS-FET WITH SURGE PROTECTION .......................................................................................................... 18
16.5 VMOS-FET WITH OVERCURRENT PROTECTION.............................................................................................. 18
16.6 CURRENT LIMITING........................................................................................................................................ 19
16.7 OVERVOLTAGE PROTECTION OF THE PCB:..................................................................................................... 19
16.8 DC-MASK FOR VARIOUS HOOK TRANSISTOR ARRANGEMENTS .......................................................................... 20
17
SHUNT- AND RINGER TRANSISTORS ..................................................................................................... 20
18
ON-HOOK CONDITIONS .............................................................................................................................. 20
19
18.1 QUIESCENT CURRENT PATH ........................................................................................................................... 21
RINGING MODE ............................................................................................................................................ 21
20
19.1 RINGING FREQUENCY COMPARATOR .............................................................................................................. 21
OSCILLATOR INPUT .................................................................................................................................... 21
21
EMC & RFI ISSUES ....................................................................................................................................... 21
21.1 TECHNOLOGY: .............................................................................................................................................. 21
21.2 LAYOUT HINTS: ............................................................................................................................................. 21
21.3 EMC BLOCKING PARTS: ................................................................................................................................ 22
21.4 BLOCKING OF AGND: ................................................................................................................................... 22
22
BOARD SCHEMATIC .................................................................................................................................... 23
23
BOARD LAYOUT........................................................................................................................................... 24
24
PART LIST ..................................................................................................................................................... 25
25
APPLICATIONS ............................................................................................................................................. 26
26
LIABILITY AND COPYRIGHT STATEMENT ................................................................................................ 27
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3 Other applicable documents and papers
1.
2.
3.
4.
5.
6.
Data Sheet SA2532KA/B
Pin-out Comparison SA2531 - SA2532
Application Note for Speaker Phone: Application Note SAN2202
Application Note for uC interface : Application Note SAN3010
Application Note for the Extraction of Power : Application Note SAN3020
Application note for using Dynamic Mic : Application Note SAN3021
4 Revision status
AN1500 Application Note (this document):
AN1500 Demo Board Schematic
DB1500I Demo Board Layout
Rev.: B
Rev.: 1.0
5 SA2532K Pin Layout .
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LS
1
28 RI
RO1
2
27 LI
RO2
3
26 VSS
VDD
4
25 CS
AGND
5
24 M2
STB
6
23 M1
CI
7
MO
8
LLC
9
20 R1
HS/DPN 10
19 R2
OSC 11
18 R3
MODE OUT 12
17 R4
C4 13
16 C1
C3 14
15 C2
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SA2532K
22 MODE
21 FCI
AN1500A
6 General Description
The SA2532K device was developed to provide “plug & play” solution for the Indian DOT, emphasizing high
performance voice transmission and reception. In spite of the fact that voice transmission and reception are the
most vital features in telephony, they are very often ignored or given lower priority compared with some more or
less useless non-voice features. No compromises were accepted during the design phase of the SA2532K, which
is based on the SA2531/2 speech circuit and which supersedes even the hardest PTT requirements worldwide.
The dialler part is based on a long history of producing a wide range of dialer circuits with user-friendly features in
compliance with various national PTT regulations. This knowledge enabled us to develop a specific product to meet
with DOT type approval.
The last piece in the puzzle to complete the full picture of the first CMOS single chip POT was the tone ringer. A
ring frequency discrimination circuit was implemented to avoid false “bell-tinkle” during pulse dialing from a parallel
telephone. The 3-tone melody generator provides the ringing signal.
Note: all the subsequent component numbering is referenced to the AN1500 schematic, shown in pt.22
7 Demo board configuration
The SA2532K is the rare combination of advanced technology and down-to-earth simplicity providing easy and
uncomplicated design effort for the telephone manufacturer. No fussing around: Simply go by the straight forward
guidelines supplied by a highly experienced application group. No technology stress but appealing functionality.
See Fig. 1 for configuration locations:
Sidetone Network
J2: Dial Mode
J1 :Line terminal selection
Selection
Handset Connector
Line connector
J3: line loss compensation
selector
Ringer Capsule
Connector
Fig. 1: Demo board configuration
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AN1500A
7.1 Setting a/b line connection
J1 allows selection of a/b line terminals to
easily adapt the demo board to various
PTT line connections:
inner two pins (default)
outer two pins (optional)
J1
J1
7.2 Connecting a handset
A handset connected at Z2 should have the following
connections:
Handset
remark: observe polarity of the electret microphone
7.3 Setting dialing mode
By J2, a selection of 3 different dialing modes can be
made, 2 pulse (=LD) dialing modes and a DTMF
dialing mode.
If LD Mode is selected then it is possible to switch
into MF mode by pressing the ! key but the mode
will return to LD after a hookswitch operation or after
a Recall (flash). In LD mode pulsing is at 10 pulses
per second.
LD Mode
make/break
ratio 1:2
J2
LD Mode
make/break
ratio 2:3
J2
MF Mode
J2
7.4 Setting line loss compensation (AGC)
Line loss compensation = line current dependent
gain setting of Tx and Rx amplifiers can be set by
jumper setting to 3 different modes : high, low and
no LLC (=default).
LLC 45 to 75mA
J3
LLC 20 to 50mA
J3
no LLC
J3
7.5 AC impedance
The Characteristic or output impedance of the SA2532K is set internally to 600Ω. No further components are
required. For a complex impedance refer to pt 11.
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8 Description of keyboard functions
The user-friendly operating procedures comply with different PSTN and PABX systems worldwide. By choosing
between the total of 19 keys it is possible to fit the SA2532K into most telephone designs.
The keyboard is connected to 8 pins of the SA2532K (C1...C4, R1...R4) by a n*m SPST keyboard matrix. To
extend two of the rows, a diode (D9 and D10) are added. This arrangement allows detection of 19 keys on a 4*4
matrix.
8.1 Numeric keys
The numeric keys (1..0,!,#) are standard number dial keys for both DTMF and pulse dialing (!and # only DTMF).
Additionally the !key can be used for temporary MF switching.
8.2 Flash keys (R,R2)
Selection of flash timing can be made by selecting one of the 2 flash keys :R1= 100ms and R2= 270ms.
8.3 Last number redial key (LNR)
The last number redial facility allows redialing of the last manually entered number by one keystroke. LNR is
repeatable after each off-hook. The LNR key also supports the sliding cursor protocol (see pt. 10) to allow
convenient redialing with PABX systems.
8.4 Pause key (PAUSE)
This key is to insert a pause in a digit string. Each pause is 2 seconds if inserted within the first 5 digits otherwise a
wait function will halt dialling until a PS or LNR key is depressed.
8.5 Tone / Pulse switching
When any of the LD dialing modes is selected (see pt. 7.3), a switch to temporary MF can be performed by
pressing the ! key to get into DTMF mode and one of the flash (R)-keys to get back to pulse dialing. Once in MF
mode the mode output LED is active.
Remark: temporary MF can only be activated, when the initial dialing mode selected by J2 (see pt. 7.3) is in one of
the pulse dialing modes.
8.6 Enter/M5
The ENTER key is used to program the memory (M5). Pressing ENTER followed by the key M5 opens the memory
location for storing the number.
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9 Using the SA2532K
The DB1500I demo board is delivered with an SA2532K installed and the key functions are according to the chip
are illustrated below.
C1
C2
C3
C4
R1
MUTE
1
2
3
R2
4
5
6
7
R3
8
9
0
*
R4
#
PAUSE
R
R2
LNR
ENTER
M5
Fig. 2: SA2532K keyboard labels
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AN1500A
10 Sliding cursor protocol and pause insertion
To accommodate easy and uncomplicated redialing behind a PABX, a sliding cursor protocol is implemented:
if a manually entered digit string matches the contents of the LNR memory, pressing LNR will only dial out the
remaining digits :
example: desired number 0123456 (where 01 is the access code)
off-hook, manual entry = 01 -wait for dial tone
-23456 - line is busy
(LNR contents is 0123456)
off-hook, manual entry = 01 -wait for dial tone
- press LNR key:
LNR dials out the remaining digits: 23456
-on-hook
11 AC impedance of the SA2532K
The SA2532K is designed for applications requiring a characteristic impedance of 600 Ohms, no connection should
be made to CI (pin 7) if a real impedance is required. Should a complex impedance be required a capacitor of
approximately 1/10 of the complex part of the impedance should be connected to CI. Every complex impedance
consists of a real and complex part. The ac impedance of the SA2532K is calculated by
ZAC = ZSYN + Z1
Where :
Z1 = the external resistor connected between pin 1(LS) and pin 27 (LI) . This resistor is also used by the device for
current monitoring and sets the DC resistance. To maintain correct operation the value of this resistor should be
set to 30 Ohm.
ZSYN = the internally synthezised impedance.
For real impedances
ZSYN = 19 * Z1
ZAC = (19*ZSYN) + Z1
ZAC = 20 * Z1 = 600 Ohm
If a impedance lower than ZAC is required, then a external parallel impedance should be added between LS and
VSS. To calculate the resulting AC impedance, any parallel impedance path between LS and VSS should be
considered. For example, if a bipolar line transistor is used, the resistance from the transistors base to VSS (ZP) is
in the order of 10K (R10). If a MOSFET is used then ZP is in the order of 100K which is negligible.
ZAC = 600//ZP
Care must be taken when selecting the value of ZP since the value chosen should be such that the line transistor is
driven into full saturation.
11.1 Demo board measurements:
11.1.1 Definition:
return loss is defined as:
where:
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returnloss = 20 * log
Zref + Zx
Zref − Zx
Zref = the reference AC impedance (= the line termination)
Zx = the AC impedance of the telephone under test
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AN1500A
11.1.2 Measurement:
Echo return loss (according to BAPT223
ZV5) is measured by bridge balance
measurement as shown in Fig.3:
R1 and R2 must be matched to 0.1%,
the measuring equipment must be
isolated from earth and should have an
input resistance of >25kΩ.
Capacitors C1 and C2 must be >10µF.
The Telephone under test is supplied by
a (high ohmic) current source and
measurements are taken in speech
mode with a connected handset.
Fig. 3: Return loss measurement setup
Calculation of results:
The sending level, measured in “cal”-position of switch SW is tuned to ps=-10dB950mV= 300mVrms,thus the sinewave
generator’s level is -4dB950mV = 600mVrms.The receive level (=pe) is measured in “meas”-position of switch SW.
The echo return loss is then calculated by:
or
ardB = ps - pe
ardB = 20* log (ps / pe)
(ps, pe levels in dB950mV)
(ps, pe levels in mVrms)
f [Hz]
0
300
600
900
1200
1500
1800
2100
2400
2700
3000
3300
3600
3900
12
14
600 Ohms
16
220+820//115nF
Echo return loss [dB]
270+750//150nF
18
20
22
24
Fig.4 shows some typical
results, measured with the
DB1500I demo board with
Zref= 600Ω, Zref= 220Ω +
820Ω//115nF and Zref=
270Ω + 750Ω//150nF.
The board was configured
as shown in the schematic,
using a single bipolar
(2SA1210) line transistor.
26
28
30
Fig. 4: typ. return loss measurement results with the DB1500I demo board
12 Sidetone cancellation
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AN1500A
The side tone is probably one of the most important parameters, if not the most important parameter. It determines
very much the overall instinctive performance of a telephone since it has direct influence on other parameters. In a
subjective test the two most inherent parameters are distortion and side tone, or other parameters directly
influenced by those two, e.g. echo, acoustic stability, clearness, etc.
During the design of the SA2532K family considerable effort was put into the system definition of the side tone
cancellation. It was clear that even the highest side tone cancellation could give an unpleasant harsh distortion at
very large signal levels if no efficient limiter was provided. This led to the designing of what turned out to be the
best “soft clipping” circuit yet developed, surpassing any solution used in a telephone so far.
The encounter is a side tone which is easy to calculate and which gives a well defined cancellation virtually
independent of other parameters like return loss (ac impedance) and dynamic range (absolute input signal levels).
12.1 Dual Soft clipping:
The dual soft clipping circuit prevents harsh distortion and acoustic shock in both directions by limiting the
maximum output of the Tx/Rx amplifiers at a level which still maintains a non-distorted signal (see VAGC levels in
data sheet).
If the output of the amplifier is already at the soft clip level and the input level is further increased, then the
amplifier’s gain is reduced, so that the output level remains non-distorted at the soft clip level. Even fast input signal
peaks are detected because of the fast attack time (see tATTACK) of the soft clip circuit. Instabilities are prevented by
using a long decay time (see tDECAY in data sheet).
12.2 Side tone balance network:
The side tone balance network is simply calculated as:
ZBAL = ZLINE x 10
12.3 Example:
For a line termination of
270Ω+750Ω//150nF
the resulting sidetone balance network would be:
2k7 + 7k5//15nF
Within the AN2201 application, this would apply to R13= 2k7
R14= 7k5
C4 = 15nF
13 The Double Wheatstone principle
The family of SA2532K single chip telephones are using a double Wheatstone bridge for return loss and side tone
cancellation. This unique configuration makes it very easy and uncomplicated to set the side tone network.
Fig. 5 explains the principle of the Double Wheatstone bridge: For easier understanding the block diagram is split
into two separate diagrams, which only show the relevant components.
The components shown in the block diagram represent the following components in the DB1500I schematic:
ZLine:
Z1:
Z2:
Zsyn:
Zbal:
Rref,Zref:
11/27
the PTT´s AC impedance (external)
R11 = 30Ω
R12 = 300Ω
Q3
the sidetone network
internal resistors
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AN1500A
13.1 Sidetone cancellation
Perfect sidetone cancellation is achieved, when the sidetone balance network is matched to the line impedance by
a factor of 10, which is equal to the matching of the resistors Z2 and Z1.
With ideal matching, no differential potential of the transmitted signal occurs at nodes RI and STB and the output of
the RX amplifier is 0.
13.2 AC impedance
An internal amplifier controls the impedance of Zsyn by matching LI to an internal reference. Part of this internal
reference is accessible by pin CI. When no external component is connected at that pin, the AC impedance of the
circuit is synthesized to 600Ω.
When a capacitor is connected at CI, the AC impedance of the chip becomes complex. For correct adaption, the
capacitance of CCI should be 1/10 of the line’s complex part.
Fig. 5: Double Wheatstone bridge principle
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14 Further Adjustments
14.1 Frequency response shaping: Transmit
Fig. 6: Tx signal path
Transmit frequency response shaping is performed by 3 resistors for gain setting and 3..4 capacitors for frequency
shaping:
14.1.1 Microphone gain setting
The electret handset microphone is supplied from the constant voltage at LI (#27), filtered by R20 and
C14 (see fig 6). R21 and R23 are the bias resistors of the electret microphone. Transmit gain is set by both
selecting the proper microphone type (sensitivity) and by varying R21 & R23. Reasonable values for these resistors
are in the range of 1...2.5kΩ (each), which results in a gain adjustment range in the order of 6..8dB.
14.1.2 Tx frequency shaping:
Transmit frequency shaping can be done by C11,C13 (high pass) and C12( low pass). R22 can be installed to
attenuate the microphone signal without affecting the frequeny response curve,
M1(#23) and M2 (#24)are differential inputs of the microphone amplifier. Please note the proper connection of the
M1 and M2 inputs in respect to the positive and negative side of the microphone.
To find the correct values, a SLR (sending loudness ratings) measurement with the specific handset used in the
customer’s application must be made.
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14.2 Frequency response shaping: Receive
Fig. 7: Rx signal path
The receive signal is applied at the Rx amplifier input, RI (#28) and STB (#6) and is available at the differential
outputs RO1 and RO2.
14.2.1 Receive gain setting:
Rx gain can be set by both the sensitivity of the earpiece and the value of R25.
14.2.2 Rx frequency shaping
Receive frequency shaping is done by C15 (low pass) at the Rx amplifier output. C17 impedes the DC path through
RO1, RO2.
To find the correct values, a RLR (receive loudness ratings) measurement with the specific handset used in the
customer’s application must be made.
14.2.3 Metering pulses filtering
If filtering of metering pulses (typ. 12 or 16kHz ) is required (for example in Germany) two blocking filters can be
installed:
LBF1 , CBF1 as notch filter at the line input and
LBF2 ,CBF2 as notch filter at the Rx amplifier input
Note:
since CBF1 is connected at the line side, it must be a .../250V capacitor and LBF1 must be able to drive the
maximum line current (≈100mA) without saturation.
LBF2 and CBF2 however, can be low voltage, low current components .
The application AN1500, shown with two resonators, gives adequate attenuation of the metering pulses signal. The
benefit of this application is, that only one filter (LBF1,CBF1) is used on the high voltage/high current side, while the
second notch filter (LBF2,CBF2) is connected at a low voltage/low current node, enabling use of low cost
components.
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15 Off-Hook conditions & DC mask
15.1 Line current path
When going off-hook, SW1/1 short
circuits the leakage supply resistor
R1 and enables a low-ohmic path
from line into the telephone. At the
same time SW1/2 supplies the base
of Q2 via R7 and R8 and signals a
“off-hook” state to the IC´s
HS/DP-pin (#10). The base/gate of
Q1 is pulled down by Q2 and the
SA2532K is started up. VLI (pin #27)
is regulated to the specified voltage
by shunt regulation from Q3.
Line current flows through the
following path:
La -- RB1 -- Q1 -- R11 -- Q3 -- VSS -RB1 -- Lb
Fig. 8: DC mask & line current path
15.2 DC mask path
The DC characteristics (DC loop resistance) of the application is determined by the following conditions:
Va,b = VLI + VR11 + VCE,Q1 + 2x(Vf,RB1)
• VLI :
• VR11:
• VCE,Q1:
• 2x(Vf,RB1):
The voltage at LI (#27) is shunt-regulated to 4.5V by Q3.
VR11 = Iline * R11,
where: R11=30Ω
changing the value of R11 is not recommended, since it affects the following parameters:
AC impedance
Tx and Rx gains
DTMF level
AGC switching positions
This parameter is mostly affected by the type of hook transistor configuration used, see pt.16
for details
Generally, the rectifier bridge must be installed to meet the specification for independence of
polarity. Vf is typ. 0,7....0,8V (20...100mA). If lower forward voltages are required, an active
(MOSFET) bridge must be used.
15.2.1 Setting for low DC mask:
The standard application regulates the voltage at LI to ≈4.5VDC for line currents >10mA, determining the absolute
level of the DC mask. Lower line currents cause a slope-down of VLI, enabling operation down to 5mA . The
resulting DC mask fits into most countries´ DC mask specs. Some countries however, like Denmark or Norway
require a very low DC mask at line currents below ≈20mA line current. The constant voltage level at LI can be
lowered to about 4.3V by connecting a 16kΩ-resistor from CI (#7) to Vss (#26). With this adaption, the DC mask is
15/27
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lowered by only ≈0.2V for line currents >17mA. At lower line currents however, as required for these countries, the
DC mask is lowered significantly, since slope-down of LI occurs already at line currents <17mA..
DC mask: Denmark
15
13
11
Ua,b [V]
9
CI = 16k
CI = n.c.
7
DC mask UL
DC mask LL
5
3
1
-1 0
5
10
15
20
25
30
35
40
I line [mA]
Fig. 9 : Example for low DC mask: Denmark
Fig.10 shows a typical example for a low DC mask setting compared with the DC-mask specs for Denmark (ETS
300 001: March 1996) : the solid line indicates the DC mask with a 16kΩ resistor connected at CI, while the dotted
line shows the DC mask of the original AN1500 A0 version with a single PNP hook transistor (ref. pt.16).
Note: When connecting a resistor at CI, AC impedance, DTMF level, Tx/Rx gains and LLC gain curves are slightly
changed. Therefore, after installing a resistor at CI, the above parameters must be readjusted.
15.3 Speech mode
In speech mode, shunt regulation (by Q3) is active and line current flows as described in pt 15.1. At the same time,
both Tx and Rx amplifiers and 2 wire-4 wire conversion circuits are active.
15.4 DTMF dialing
During DTMF dialing the same line conditions as in Speech mode apply, except that speech is muted in both
directions and a confidence tone is sent to the Rx amplifier.
The DTMF signal is modulated to the line by controlling the shunt transistor, Q3. During inter-digit pauses speech is
also muted.
15.5 Pulse dialing
With pulse dialing, the line has to be interrupted during “break” periods and short circuited during “make” periods.
For example, “LD 60/40 10pps” means: break/make ratio is 60:40 with 10 pulses per second =
The dialing pulse is a 60ms break (line interrupt) followed by a 40ms make (line short circuit).
Dialing number “1” will result in one dialing pulse, total time = 100ms.
Dialing number “0” will result in 10 dialing pulses, total time = 10*100ms = 1sec.
Line break pulses are performed by Q1 being switched off. The on-off control signal is output from the HS/DP pin
(#10) switching Q2 (and in turn Q1) on and off.
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Make pulses are performed by Q3 with Q1 being switched on. The base of Q3 (=pin CS, #25) is pulled to VSS,
resulting in VLI = VBE ≈ 0.7V.
CS is pulled low during the complete dialing period of one digit, which means in worst case (dialing number “0”) the
circuit cannot be supplied from line and must be buffered by the VDD-cap, C9. Therefore C9 must be big enough to
supply the active circuit for 1 second.
15.6 Pre-digit, Inter-digit ,inter-tone and access pauses
During pulse and DTMF dialing, several pauses must be added (see also: data sheet):
•
•
•
•
pre-digit pause (PDP):
inter-digit pause (IDP):
inter-tone pause (ITP):
access pause (AP):
Pause between CS=low and first break (pulse dialing only)
Pause between pulse dialed out numbers, from last “make” to next PDP
Pause between DTMF dialed out numbers
manually inserted pause in a digit string (see pt. 7.8)
16 Hook Transistor options
The following tables give an overview of the advantages and disadvantages of 3 different types of hook transistor
arrangements: single bipolar PNP, PNP darlington and MOSFET. Any of these configurations can be installed on
the demo board. Just check for corresponding part name on the PCB layout.
16.1 electrical requirements
Both hook transistor (Q1) and driver transistor (Q2) must be >=200V types, Q1 must have an IC >100mA. If single
PNP configuration is used, the transistor must have a gain
IC
≥ 100
IB
at IC=100mA. The driver transistor (Q2) must
have enough gain to be in full saturation at high line currents ( if driving a bipolar hook transistor ).
recommended types:
Q1
2SA1210, MPSA92,BSS92 (depending on configuration)
BSP92 (SMD)
KSA1156Y
Q2
2N5551
MPSA43
BF820 (SMD)
16.2 Single bipolar transistor
Schematic
+
• lowest DC mask at low currents
• just one transistor
• Transistor type must have a gain
IC
≥ 100
IB
at IC=100mA
• high on-resistance at high
currents slightly affects gains and
DTMF level
• 10kΩ base resistor (R4) affects
AC impedance
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16.3 Bipolar darlington transistor
Schematic
+
• low cost
• high DC mask at low currents
may be tight to spec limits for
some PTTs
• 2 transistors
• 10kΩ base resistor (R4) affects
AC impedance
16.4 VMOS-FET with surge protection
(surge protection = R3 =20Ω may also be used with bipolar hook transistor options)
Schematic
+
•
•
•
•
•
powerless switching
low on-resistance
low DC-mask
excellent surge protection
gate resistor (R5) does not affect
AC impedance
-
• MOS handling required
• higher cost than bipolars
• few vendors
Principle: the source voltage is limited to ≈10V (D6; see schematic) in off-hook state . High voltage peaks induced
at line will generate a high positive voltage drop across R3, lifting the gate voltage over the source voltage and thus
cause the (P-channel) Transistor to shut off.
16.5 VMOS-FET with overcurrent protection
(overcurrent protection =R3,Q5 may also be used with bipolar hook transistor options)
Schematic
+
•
•
•
•
•
powerless switching
low on-resistance
lowest DC-mask
adjustable overcurrent protection
gate resistor (R5) does not affect
AC impedance
•
•
•
•
MOS handling required
higher cost than bipolars
few vendors
extra (low cost) transistor
required
Principle: the line current generates a voltage drop across R3. If this voltage drop is >0.7V, C-E of Q5 is on and
shuts Q1 off by short circuiting its Gate/Source voltage.
installed = 0.7V/3.9 Ω= 180mA
The shutoff current is calculated by
Ishutoff = 0.7V / R3 ;
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AN1500A
TP7
10u
C2
15k
R3
R8
30
R6
10
Q6
22k
R5
220k
R1
TP2
100
R7
10V
BC327
Q5
MPSA43
Q9
MPSA92
Q7
Q8
TP10
QMPSA92
QMPSA92
R4
820 2W
16.6 Current Limiting
Q3
150k
R2
QMPSA43
1000k
R10
Fig. 9 : Example of current limiting circuit
Principle: the line current generates a voltage drop across R6. If this voltage drop is >0.7V the Q6 switches on
effectively shutting off Q9. The 2W resistor R4 is used to dissipate the power generated as a result of the current
through and voltage across C-E of Q9. Ishutoff = 0.7V / R6
16.7 Overvoltage protection of the PCB:
Additionally to the protection measures described in pt. 16.4 and 16.5 it is highly advised to install an additional
surge protection device directly at the a- and b- terminals.
The maximum C-E breakdown voltages of the line and driver transistors are:
transistor type (line)
BSS 92,BSP92
MPS-A 92
2 SA 1209
2 SA 1210
VCEO ,V(BR)DSS
200V
300V
160V
200V
transistor type (driver)
MPS-A42, KSP42
MPS-A43,KSP43
2N5551
VCEO
300V
200V
160V
The clamping voltage of a 150V-varistor can be up to 400V at 5 Amp. clamping current. In other words, it may not
be able to protect the line transistor at very high surge spikes.
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16.8 DC-mask for various hook transistor arrangements
9
Fig. 9 shows a typical DC
mask graph for the optional
hook
transistor
arrangements: MOSFET with
overcurrent
pro-tection,
MOSFET
with
surge
protection, single PNP and
PNP darlington .
The X-scale shows line
current in mA and the Yscale shows the voltage
across the a- and bterminals.
Check with your application’s
PTT require- ments to find
the arrangement that fits best
into the specification.
8
Ua,b [V]
7
6
MOSFET with surge protection
5
single PNP (2SA1210)
bipolar darlington
MOSFET with current protection
4
3
2
0
5
10
15
20
25
30
35
40
45
50
(see also: pt 15.2.1: setting
for low DC mask)
I Line [mA]
Fig. 11: DC mask for various
hook transistor options
17 Shunt- and Ringer Transistors
Q3 is used to shunt excess line current to VSS to maintain a constant voltage on LI (#27). It is also used for DTMF
line modulation and short circuits the speech part during pulse dialing (ref. Fig.8).
The transistor must be capable of driving >100mA and have a typ. gain B >=100.
Q4 is used to switch the piezo ringer on and off, it can be any NPN single or darlington transistor capable of driving
100mA at 25V UCE.
recommended types:
Q3
Q4
BC547
BC517 (Darlington)
BCV27 (SMD- Darlington)
BC327-16
BCX 51-16 (SMD)
18 On-hook conditions
In on-hook state the circuit is supplied by a very small current to maintain retention of stored numbers and ringing
melody. The hook transistor is off and the HS pin (#10) is forced to zero by R8 and R9//Q2B,E. The IC is powered
down, only a very small current flows from line to maintain VDD and thus retention of stored memories and ringing
melody. The DC resistance of the application in this state is >5MΩ (= the value of R1).
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18.1 Quiescent current path
La -- R1 (determines on hook DC resistance) -- RB1 -- R15 -- VDD (C9 // D1)
VSS -- RB1 -- Lb
If the telephone is disconnected from line memories are not lost since C9 keeps charging VDD for a limited period of
time. The absolute time span depends on the quality (internal discharge) of C9 and the leakage resistance of D1.
19 Ringing mode
In on-hook state the circuit is supplied by a very small current to maintain the retention of stored numbers and the
ringing melody
Frequency discrimination assures that the tone ringer is activated only when a valid ring signal is applied and not
when pulse dialing from a parallel telephone (false “bell-tinkle”).
19.1 Ringing frequency comparator
The ring signal is checked at pin FCI (#21) for a valid ringing frequency. As soon as a signal is applied to the line
the internal “ring frequency detector” will start, provided that the signal level at FCI is above the trigger threshold (≈
2/3 VDD) . If the frequency is within the specified range the melody generator will send a bitstream out of MO (#8),
charging the piezo ringer via Q4 and discharging it via D5 and an internal high voltage transistor. As soon as a nonvalid or missing ring signal is detected, the bitstream is stopped and the circuit returns to standby.
Ringing signal path
La -- C1 -- R2 -- RB1 -- C8//D4 (charges piezo ringer supply) -- C8//D4 (charges VDD)
VSS -- RB1 -- Lb
another path exists from C1 -- D2 -- R3 to FCI // C2 // R4 for the ringing frequency detector input.
20 Oscillator input
A 3.58MHz ceramic resonator (recommended type MuRata CSA 3.58MHz ) must be connected at OSC (#11). The
parallel capacitor C10 is to trim the oscillation frequency (not required with the recommended resonator type).
The exact resonant frequency should not be measured at the OSC input directly, because the capacitive load of the
Oscilloscope probe will shift the oscillation frequency.
DTMF frequencies are derived from the resonant frequency, if these frequencies (see DTMF frequency standards
or data sheet) are not centered, the oscillator must be trimmed.
21 EMC & RFI issues
EMC (electromagnetic compatibility) and RFI (radio frequency interference) is a major concern in most PTT
approvals. And due to the upcoming digital networks (GSM, CDMA, DECT) also a feature which can be “heard” by
the user. Therefore it is a major headache for telephone designers, since EMC testing is generally done with
finished designs and failing EMC tests may result in adding expensive components, like coils, chokes etc.
Much can be done by considering EMC from the very beginning ! The most important factors are IC technology,
layout and placement of EMC blocking components:
21.1 Technology:
Due to SAMES unique CMOS technology the circuits show far less sensitivity to RFI than bipolar circuits which
makes EMC a much easier task.
21.2 Layout hints:
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As a common rule, VSS ground planes should be as large as possible. “Bottlenecks” and long distances in the
ground path should be avoided.
Additionally, long distances between LI (#27) and the Emitter of the shunt transistor (Q3) should be avoided.
Therefore, Q3 should be placed near the IC pins :
collector = pin #26 =Vss,
base
= pin #25 = CS,
emitter = pin #27 = LI.
21.3 EMC blocking parts:
Connections for blocking components, preferably ceramic capacitors (far less cost than coils) should be already
considered in the layout design. These capacitors should be connected as close to the IC (or line/handset
connector) pins as possible with a low-ohmic connection to VSS . SMD caps have best performance for EMC
blocking because of short leads and they can be placed directly underneath the IC at the solder junction.
If the use of SMD components is not possible, leaded ceramic capacitors can be connected at top PCB side as
shown in the demo board’s layout. Refer to EC1..EC7 on both schematic and layout.
The actual number of required EMC blocking components in the customer’s design cannot be predicted, since
EMC performance is influenced by many other factors, like telephone assembly, wire lengths etc.
21.4 Blocking of AGND:
For SA2532K EMC designs, it is very effective to block the AGND-pin (#5) with an inductor of ≈150nH or
higher. This small inductance can be installed without extra cost by a printed coil with ≈8..10mm diameter and
≥5 turns (see PCB layout).
How to calculate the inductance of a printed spiral coil:
L[nH ] ≈
10.75 • n 2 (d o + d i )
where:
n = number of turns
do = outer diameter in cm
di = inner diameter in cm
 d − di 
1 + 2.72 o

 do + di 
Example:
The printed coil used in the DB1500I layout has the following dimensions
(see Fig.12):
do= 8.2 mm
2
di = 2.6 mm
n = 5.5
L[nH ] ≈
10.75 • 5.5 (0.82 + 0.26)
 0.82 − 0.26 
1 + 2.72

 0.82 + 0.26 
= 146 nH
Fig. 10:printed coil on DB1500I
PCB for EMC protection
Note: Instead of a printed coil, a helical air-coil (7mm diameter, 7..9mm length, 5..7 turns) made by a piece of
copper wire may also be used.
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22 Board Schematic
IC 2
2
JM P
1
a
B R IDG E
LIN E
C 12
b
3
+ C 14
A
100u/25V
M 1 23
1 LS
10n
4
2K 2
R 20
R3
330K
D2
12V
21 FCI
S W 1_a
8
R 21
1K 1
R 22
X
X
27 LI
Z2
1
4
3
2
M 2 24
10n
2 ON
VR1
VDR
C 11
2
4
6
8
C 13
B
D
F
H
7
30
1A
3 C
5 E
7 G
3
6
R4
220K
C2
10N
R 11
J1
2
4
5
3
5
1
Q 1B
LA
C
LC
W
O FF
4
M P SA 92
Z1
4
Q 1A
M P SA 92
A
3
R2
2K 2
C1
680n/250V
R1
2
5M 1
1
IC 1
R 23
1K 1
M1
M2
F1
F2
H A ND S E T
+ C6
R 13
1K 8
D6
Q3
B C 327
25 C S
7 CI
10V
R 14
7K 5
C4
15nF
Q4
C1
C2
C3
C4
R1
R2
R3
R4
D5
B
D
2
4
1
JU M P E R
1N 4148
510
R 18
R inger
10 H S /DP
8 MO
22 M OD E
J2
1 A
C
3
+ C8
10u/25V
3
24V
X
R 25
TO NE
10nF
B C 547B
D4
+ C 16
C7
R 17
100K
1
B
A G ND 5
M OD E _O UT 12
100U /6V
R9
1M
Z3
X
R 15
330K
J3
A
C
B
D
16
15
14
13
20
19
18
17
1K
R8
150K
R7
220K
Q2
M P SA 45
2
RO2
LE 1
5
7
6 ON
C 15
R 26
8
S W 1_b
6 S TB
+
O FF
3
RO1
SA2532K
c
B
C 17
10u
28 R I
C5
R 10
10K
1U /10V
R 13
100K
10u/36V
R 12
300
LE D 2
S1
M UTE
S2
1
S3
2
S4
3
S5
4
S6
5
S7
6
S8
7
9 LLC
2
O S C 11
4
JU M P E R
V
D
D
4
2
D 10
V
S
S
26
C
D 11
C 10
+
5V 6
C9
470u/16V
22p
S9
8
S 10
9
S 11
0
S 12
*
S 13
#
S 14
P A U SE
S 15
R1
S 16
R2
S 17
LN R
1
2
3
M UTE
4
5
6
PAUSE
7
8
9
R1
*
0
#
R2
C
LNR
X1
3.58 M Hz
K eypa d Layou t
2S A 1210
Q _c
R _c
12V
D _b
b
SAM ES Telecom
100K
Q _b
a
R 1_b
100K
B S S 92
R 2_b
20
Q 2_a
b
B C 557
Sch. SA2532KA/B
Pn#
Rev : B
Single Chip Telephone Application Circuit
R 10C
10K
R 10B
100K
2
3
sa m e s
c
c
2. M O SFET
c
Q 1_a
D _a
R 1_a
100K 12V
23/26
a
R 10A
10K
1. M O SFET w ith current lim it
1
b
3.9
R 2_a
a
D
B S S 92
Line Transistor Options
3. Single PNP
4
Sh 01 of 01
5
6
Date : 3rd M arch 1997
7
8
D
AN1500A
23 Board Layout
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24 Part list
Designator
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
CBF1
CBF2
D1
D2
D3
D4
D5
D6
D7-D9
D10
D11
EC1-EC6
IC1
IC2
J1
J2
J3
J4
J5, J6
LBF1
LBF2
LE1
LED1
LED2
Q1
Q1A,B
Q1C
Q2
Q3
Q4
Q5
R1
R2
R3
R4
25/27
Part Type
680n/250v
10n
1u
10u/35v
10u/30V
470u/16v
10n
10n
100u/25v
10n
100u/25v
10u
.../250V
..../10V
12V
12V
24V
1N4148 (or LED)
10V
1N4148
1N4148
5v6
1n
SA252K
DF06
Line
Mode
LLC
(short circuited)
not fitted
not fitted
not fitted
BSS92
MPSA92
2SA1210
MPSA45
BC327
BC547B
BC557
5.1M
2K2
330k
220k
sames
Description
Ringer Capacitor
Anti aliasing filter, ring frequency detector
not fitted (hookswitch filter)
not fitted (sidetone network)
DC-AC separation, RX amplifier
DC-AC separation, RX amplifier
not fitted
Filter and buffer for ringer supply
Vdd supply capacitor
Oscillator fine tuning
TX response shaping, DC-AC separation
TX response shaping (low pass) (not fitted)
TX response shaping, DC-AC separation
Electret handset microphone supply filter
RX Response shaping (not fitted)
Analogue ground filter
DC-AC separation RX Output
Metering pulses blocking filter (not fitted)
Metering pulses blocking filter (not fitted)
Gate voltage protection for MOSFET transistor (not fitted)
Ringer voltage clamping, FCI input protection
not fitted
Ringer voltage limitation
Piezo ringer discharge (LED for ring indicator)
Surge protection
not fitted
Keyboard
Vdd limitation
EMC blocking capacitors (not fitted)
Single Chip Telephone
Rectifier bridge
Line connector pin selection
Dialling mode selector
Line Loss compensation selector
not fitted
Simulate on-resistance of keypad
Metering pulses blocking filter, must not be in saturation at Iline max
Metering pulses blocking filter
EMC filter (printed on PCB)
n/a
LED Tone Indicator (SA2532K)
Hook transistor for Mosfet option (not fitted)
Hook transistor for PNP Darlington option
Hook transistor for single PNP option (not fitted)
Driver transistor for Q1
Line current shunt transistor
Ringer driver transistor
Current limiter transistor (not fitted)
Leakage current limitation
Ringing impedance
FCI input protection and voltage divider
Voltage divider
AN1500A
Designator
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21, R23
R22
R24
R25
R26
S1-S17
SW1
VR1
X1
Z1
Z2
Z3
Part Type
not fitted
not fitted
220k
150k
1M
10k
30
300
2k7
3k3
330k
not fitted
100k
510R
not fitted
2K2
1K1
not fitted
short circuited
short circuited
1K
SPST
SW-HOOK
150V
3.58MHz
LINE
Handset
Ringer
Description
Line Current sensing resistor for Q5
Pull-up resistor, HS input current limitation
Base resistor for Q2
Base shunt resistor for Q2
Base/gate series resistor for Q1
Sensing resistor for DC-mask and Line current
Side tone balance bridge resistor
Side tine network
Side tone network
Leakage current supply during On-Hook
Ringing impedance
Pull-up resistor for Q4
Low pass filter for ringer capacitance
Series resistor for LED1
Filter for electret hanset microphone supply
Supply for electret microphone
TX Frequency response shaping
RX Frequency response shaping
RX Frequency response shaping
Series resistor for LED2
Keypad Switches
Telephone Hook switch
Varistor, surge protection
Ceramic resonator
AMP modular connector
AMP modular connector
Piezo ringer connector
25 Applications
Applications based on the SA2531/2 are continuously updated. Ask your local distributor or SAMES sales office for
available papers.
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26 Liability and Copyright Statement
Disclaimer:
The information contained in this document is confidential and proprietary to South African
Micro-Electronic Systems (Pty) Ltd ("SAMES”) and may not be copied or disclosed to a third party, in whole or in
part, without the express written consent of SAMES. The information contained herein is current as of the date of
publication; however, delivery of this document shall not under any circumstances create any implication that the
information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to
inform any recipient of this document of any changes in the information contained herein, and SAMES expressly
reserves the right to make changes in such information, without notification,even if such changes would render
information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any
circuit designed by reference to the information contained herein, will function without errors and as intended by the
designer.
South African Micro-Electronic Systems (Pty) Ltd
P O Box 15888,
Lynn East,
0039
Republic of South Africa,
33 Eland Street,
Koedoespoort Industrial Area,
Pretoria,
Republic of South Africa
Tel:
Fax:
Tel:
Fax:
012 333-6021
012 333-3158
Web Site : http://www.sames.co.za
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Int +27 12 333-6021
Int +27 12 333-3158