K4S56163LC-R(B)F/R CMOS SDRAM 16Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, TCSR & PASR) Revision 1.4 December 2002 Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM 4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 2.5V power supply. The K4S56163LC is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri- • LVCMOS compatible with multiplexed address. cated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for • All inputs are sampled at the positive going edge of the system a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION clock. • Burst read single-bit write operation. Part No. Max Freq. K4S56163LC-R(B)F/R75 133MHz(CL=3) 105MHz(CL=2) K4S56163LC-R(B)F/R1H 105MHz(CL=2) K4S56163LC-R(B)F/R1L 105MHz(CL=3)*1 K4S56163LC-R(B)F/R15 66MHz(CL=2/3)*2 • Special Function Support. -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh). • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25°C ~ 70 °C). • 54balls CSP (-RXXX - Pb, -BXXX - Pb Free). 54 CSP Pb (Pb Free) Notes : 1. In case of 40MHz Frequency, CL1 can be supported. 2. In case of 33MHz Frequency, CL1 can be supported. I/O Control Data Input Register Bank Select 4M x 16 4M x 16 Sense AMP 4M x 16 Output Buffer 4M x 16 Row Decoder Row Buffer Refresh Counter LWE LDQM DQi Column Decoder Col. Buffer LCBR LRAS Address Register ADD LVCMOS -R(B)R ; Super Low Power, Operating Temperature ; -25°C~85°C. -R(B)F ; Low Power, Operating Temperature ; -25 °C~85 °C. FUNCTIONAL BLOCK DIAGRAM CLK Interface Package Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 9 8 7 6 5 54Ball(6x9) CSP 4 3 2 1 A 2 3 7 8 9 VSS DQ15 V SSQ VDDQ DQ0 V DD DQ14 DQ13 VDDQ V SSQ DQ2 DQ1 C DQ12 DQ11 V SSQ VDDQ DQ4 DQ3 C D DQ10 DQ9 VDDQ V SSQ DQ6 DQ5 D e B B E DQ8 NC VSS V DD LDQM DQ7 E F UDQM CLK CKE CAS RAS WE F G A12 A11 A9 BA0 BA1 CS G H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 V DD D D1 1 A D/2 H J E E/2 *2: Top View A A1 Max. 0.20 Encapsulant b z *1: Bottom View < Top View*2 > #A1 Ball Origin Indicator Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A 12 Address BA 0 ~ BA 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQM Data Input/Output Mask D Q0 ~ 15 Data Input/Output V DD /V SS Power Supply/Ground VDDQ /V SSQ Data Output Power/Ground SAMSUNG Week K4S56163LC-XXXX [Unit:mm] Symbol Min Typ Max A 0.90 0.95 1.00 A1 0.30 0.35 0.40 E - 8.10 - E1 - 6.40 - D - 15.10 - D1 - 6.40 - e - 0.80 - b 0.40 0.45 0.50 z - - 0.10 Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN , V OUT -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V D D, VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Notes : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 70 °C) Parameter Symbol Min Typ Max Unit VD D 2.3 2.5 2.7 V V DDQ 1.65 - 2.7 V Input logic high voltage VI H 0.8 x V DDQ - V DDQ + 0.3 V 1 Input logic low voltage VIL -0.3 0 0.3 V 2 Output logic high voltage VO H V DDQ -0.2 - - V IO H = -0.1mA Output logic low voltage V OL - - 0.2 V I OL = 0.1mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ VDDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ V OUT ≤ V DDQ. CAPACITANCE (V D D = 2.5V, TA = 23 °C, f = 1MHz, VREF Pin =0.9V ± 50 mV) Symbol Min Max Unit CCLK 2.0 4.0 pF CIN 2.0 4.0 pF Address CADD 2.0 4.0 pF D Q0 ~ DQ15 COUT 3.5 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM Note Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 70°C) Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode I CC1 Burst length = 1 tRC ≥ t R C(min) IO = 0 mA ICC2 P CKE ≤ V IL (max), tCC = 10ns Precharge Standby Current in non power-down mode I CC2NS Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current -75 -1H -1L -15 75 70 65 60 0.5 IC C 2PS CKE & CLK ≤ V IL (max), tCC = ∞ ICC2 N Active Standby Current in power-down mode Version Test Condition ICC3 P I CC3NS CKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns mA 1 mA 15 mA CKE ≥ V IH (min), CLK ≤ VIL (max), tCC = ∞ Input signals are stable 10 CKE ≤ V IL (max), tCC = 10ns 6 mA 6 CKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 25 mA CKE ≥ V IH (min), CLK ≤ VIL (max), tCC = ∞ Input signals are stable 25 mA I CC4 IO = 0 mA Page burst 4Banks Activated tC C D = 2CLKs 115 95 95 85 mA 1 I CC5 tRC ≥ tR C(min) 165 155 150 125 mA 2 TCSR Range -R(B)F Self Refresh Current Note 0.5 IC C 3PS CKE & CLK ≤ V IL (max), tCC = ∞ ICC3 N Unit I CC6 CKE ≤ 0.2V -R(B)R Max 45°C Max 70°C 4 Banks 500 750 2 Banks 400 550 1 Bank 350 420 4 Banks 360 630 2 Banks 260 430 1 Bank 200 300 °C 3 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S56163LC-R(B)F** 4. K4S56163LC-R(B)R** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL =V DDQ /V SSQ) Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM AC OPERATING TEST CONDITIONS (V DD = 2.5V ± 0.2V, TA = -25 °C to 70 °C) Parameter Value Unit 0.9 x V DDQ / 0.2 V 0.5 x VDDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time VDDQ Vtt=0.5 x VDDQ 500Ω 50Ω V O H (DC) = V DDQ-0.2V, IO H = -0.1mA V OL (DC) = 0.2V, I OL = 0.1mA Output 500Ω Output Z0=50Ω 30pF 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted) Parameter Version Symbol - 75 -1H -1L -15 Unit Note Row active to row active delay tRRD (min) 15 19 19 30 ns 1 RAS to CAS delay tRCD (min) 19 19 24 30 ns 1 tRP (min) 19 19 24 30 ns 1 tRAS (min) 45 50 60 60 ns 1 Row precharge time Row active time tRAS (max) Row cycle time t R C(min) Last data in to row precharge tR D L(min) Last data in to Active delay 100 ns 1 2 CLK 2,3 tDAL (min) tRDL + tRP - 3 Last data in to new col. address delay tC D L(min) 1 CLK 2 Last data in to burst stop tBDL (min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 4 ea 5 Number of valid output data 65 70 us 84 CAS latency=3 2 CAS latency=2 1 CAS latency=1 - 90 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) are required to complete both of last data wite command(tRDL) and precharge command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM AC CHARACTERISTICS(AC operating conditions unless otherwise noted) Parameter - 75 Symbol Min CAS latency=3 CLK cycle time CAS latency=2 tC C 9.5 tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min -1L Max 9.5 1000 - CAS latency=3 CAS latency=2 Max 7.5 CAS latency=1 CLK to valid output delay -1H 9.5 Min - 15 Max 9.5 1000 - 12 Min Unit Note ns 1 ns 1,2 ns 2 Max 15 1000 25 15 1000 30 5.4 7 7 9 7 7 8 9 - - 20 24 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 - - 2.5 2.5 CLK high pulse width tC H 2.5 3 3 3.5 ns 3 CLK low pulse width tCL 2.5 3 3 3.5 ns 3 Input setup time tSS 2.0 2.5 2.5 3.5 ns 3 Input hold time t SH 1.0 1.5 1.5 2.0 ns 3 CLK to output in Low-Z t SLZ 1 1 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 tSHZ CAS latency=1 5.4 7 7 9 7 7 8 9 - - 20 24 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Note : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product c ontained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X L H H H X X H H L BA0,1 L H H X X X Bank Active & Row Addr. H X L L H H X V Read & Column Address Auto Precharge Disable H X L H L H X V Write & Column Address Auto Precharge Disable Auto Precharge Enable X L H L L X H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H Exit L H H X X X V V V Burst Stop Bank Selection Precharge All Banks Clock Suspend or Active Power Down Precharge Power Down Mode L DQM H No Operation Command H X X H X X X L H H H A11, A 12, A9 ~ A 0 Note 1, 2 3 3 3 3 H Auto Precharge Enable A10 /AP X V Row Address L H L H 4, 5 Column Address (A 0 ~ A8) 4, 5 X V L X H 4 Column Address (A 0 ~ A8) 4 6 X X X X X X V X X X 7 Notes : 1. OP Code : Operand Code A 0 ~ A 12 & BA0 ~ BA 1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode. 4. BA0 ~ BA1 : Bank select addresses. If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). Rev. 1.4 Dec. 2002