WIDEBAND FM/FSK IF RECEIVER S1T8531 INTRODUCTION 16-SOP-225 The S1T8531 is a wideband FM / FSK receiver designed for wideband FSK data and analog FM applications. It is fabricated using Samsung’s ASP5HB 0.5um advanced BiCMOS process. The S1T8531 contains high gain IF amplifier with received signal strength indicator (RSSI), a wideband FM quadrature demodulator, a baseband filter amplifier and a high speed data slicer with sample & hold function. The IF amplifier has 100dB small signal gain and 2MHz through 40MHz bandwidth. The wideband FM quadrature demodulator has demodulation bandwidth greater than 1MHz. The baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter. The data slicer is a comparator that is designed to square up the data signal with data rates up to 2Mbps. FEATURES • Operating voltage range : 2.2 to 5.5V • Typical supply current : 5.5mA at 3.6V • Operating frequency range : 2MHz to 40MHz • High Gain (100dB) and Wideband (2MHz to 40MHz) IF Amplifier • Quadrature Demodulator with Greater than 1MHz Bandwidth • High Speed Data Slicer Operating Upto 2Mbps with Sample & Hold • RSSI Dynmic range : Typ : 60dB APPLICATION • Wideband FM / FSK Wireless Communication Systems ORDERING INFORMATION Device Package Operating Temperature +S1T8531X01-S0B0 16-SOP-225 - 10°C to + 70°C + : New Product 1 S1T8531 WIDEBAND FM/FSK IF RECEIVER BLOCK DIAGRAM IFIN IFIP GND2 SHEN RSSI DSO SHO DSIN 16 15 14 13 12 11 10 9 Sample Hold A RSSI 5pF 1 1 2 3 4 5 GND1 VCC1 QIN VCC2 QOUT 6 7 BIN BOUT PIN CONFIGURATION 2 GND1 1 16 IFIN VCC1 2 15 IFIP QIN 3 14 GND2 VCC2 4 13 SHEN QOUT 5 12 RSSI BIN 6 11 DSO BOUT 7 10 SHO DSIP 8 9 DSIN S1T8531 8 DSIP WIDEBAND FM/FSK IF RECEIVER S1T8531 PIN DESCRIPTION Pin Name Schematic Description 1 GND1 Ground. (Pin1 and Pin14 are connected internally) 2 VCC1 Supply. (Pin2 and Pin4 are connected internally) 3 QIN Quadrature demodulator tank input. VCC 3 4 VCC2 Supply. (Pin2 and Pin4 are connected internally) 5 QOUT Quadrature demodulator output. VCC 5 6 7 BIN BOUT Baseband filter buffer amplifier input. Baseband filter buffer amplifier output. VCC 6 8 9 7 DSIP DSIN Data slicer positive input. Data slicer negative input. VCC 8 9 3 S1T8531 WIDEBAND FM/FSK IF RECEIVER PIN DESCRIPTION (Continued) Pin Name 10 SHO Schematic Description Sample and hold output. 7 11 DSO Data slicer output. VCC 11 12 RSSI RSSI output. VCC 12 13 SHEN VCC Sample and hold enable input. High signal input enable sample and hold function and low signal input disable sample and hold function . 13 14 GND2 15 16 IFIP IFIN Ground. (Pin1 and Pin14 are connected internally) VCC 15 16 4 IF amplifier differential inputs. DC blocking is required. WIDEBAND FM/FSK IF RECEIVER S1T8531 ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit VCC 6 V Ta -10 to + 70 °C TSTG -55 to + 150 °C Symbol Value Unit Power Supply Voltage VCC 2.2 to 5.5 V Voltage applied to any pin VIN - 0.3 to Vcc + 5.5 V Maximum Supply Voltage Operating temperature Storage Temperature RECOMMENDED OPERATING CONDITIONS Parameter 5 S1T8531 WIDEBAND FM/FSK IF RECEIVER ELECTRICAL CHARACTERISTICS ( Vcc = 3.6V, IF = 10.7MHz, fdev = ± 75kHz, fmod = 10kHz,Ta = 25°C, IFin = -47dBm unless otherwise noted. ) Characteristic Symbol Test Condition Min Typ Max Unit Icc - - 5.5 7.0 mA IF Input Frequency IFfreq - 2 10.7 40 MHz 20dB SINAD Sensitivity (Note 2) VSEN - - -95 -81 dBm IF Amplifire Bandwidth (Note 1) BWIF - 2 - 40 MHz IF Amplifier Voltage Gain (Note 1) ∆G IF - 95 101 - dB IF Amplifier Input Impedance (Note 1) RIIIF - - 1.5 - kΩ Quadrature Demodulator Output Voltage Vo(DEM) - 100 150 200 mVrms Demodulator Bandwidth (Notes 1 and 2) BWDEM - 0.6 1 - MHz Baseband Filter Buffer Amplifier Bandwidth BWAMP - 1 2 - MHz Baseband Filter Buffer Amplifier Voltage Gain DG AMP - -3 0 +3 dB BWDS - 1 2 - Mbps RSSI - 50 60 - dB Vo(RSSI) - 0.5 - 2.0 V Current consumption Data Slicer Maximum Operating Frequency (Notes 1 and 2) RSSI Dynamic Range RSSI Output Level NOTES: 1. Not 100% AC tested but guaranteed by design and characterization. 2. Measured result on evaluation board with proper impedance matching. 6 WIDEBAND FM/FSK IF RECEIVER S1T8531 FUNCTIONAL DESCRIPTION General The S1T8531 is a wideband FM / FSK receiver designed for use in analog FM and digital FSK systems such as 900MHz / 2.4GHz ISM band analog / digital cordless phones and wideband data links with data rates up to 2Mbps. It contains IF amplifier, quadrature detector, baseband filter amplifier and data slicer with sample and hold function. IF Amplifier The IF amplifier section is composed of seven differential stage with total gain of 100dB at 10.7MHz. The input impedance at 10.7MHz is 1.5kΩ. For 10.7MHz ceramic filter applications, an external 430Ω resistor must be placed between IFP(Pin15) and IFN(pin16) to provide the equivalent load impedance of 330Ω that is required by the filter. Quadrature Demodulator The quadrature demodulator requires tank circuit with loaded Q depending on detection bandwidth. Following figure shows external components required for 10.7MHz operation. QUAD IN QUAD OUT 3 5 47pF 4.255uH Rdamp VCC Baseband Filter Buffer Amplifier3 Baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter. Following figure shows the external components required. Cutoff frequency = 1 / [2π*SQRT(R1R2C1C2)] Quality factor = SQRT(R1R2C1C2) / (R1C2 + R2C2) The component value of R1 should contain the quadrature detector output resistance. C1 Vout Vin R1 C2 R2 6 7 BUF IN BUF OUT 7 S1T8531 WIDEBAND FM/FSK IF RECEIVER Data Slicer with Sample and Hold The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the baseband filter output can be DC coupled to the data slicer DS-INP(Pin 9). The S1T8531’s data slicer incorporates an sample and hold used to derive the data slicer reference voltage by means of an external integration circuit. The sample and hold is “ON“ during reception of the preamble data pattern, and is otherwise “OFF“ in TDD (Time Division Duplex) system. The external integration circuit is formed by an RC low pass circuit placed between SHO (Pin 10) and ground. The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift close to the threshold voltage, the time constant is longer. ‘The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the settling time. When the sample and hold is “OFF“ the output (SHO) is in high impedance state with extremely low leakage current. ‘Following figure shows the internal block diagram. DS INP 8 DS INN 9 SHO 10 SHEN 13 11 DS OUT +1 The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommeded that an external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of ground and supply currents in the S1T8531 which might desensitize the chip. The data slicer can be used as a carrier detector also. Following figure shows application example. In this case, sample and hold should be off. 8 9 11 12 RSSI Reference Voltage 8 Carrier Detect WIDEBAND FM/FSK IF RECEIVER S1T8531 TEST CIRCUIT VCC IF Input Data RSSI Output 1u 50Ω 10n 100n 100n 1.8kΩ 1n 10n 16 15 IFN IFP 14 13 12 11 10 9 GND SHEN RSSI DSO SHO DSIN S1T8531 GND VCC 1 2 QIN 3 VCC QOUT BIN BOUT DSIP 4 5 6 7 8 68p 1n 39kΩ 100n 100p 20kΩ 15kΩ VCC 20kΩ Audio Output 9 S1T8531 WIDEBAND FM/FSK IF RECEIVER APPLICATION CIRCOUT IF2 BNC VCC R15 330 R14 0 R13 0 Sample &hold diable Sample &hold enable C18 100n C19 56p VCC2 C13 100n R12 56K 1 C17 10nF R16 10K TP5 RSSI 1 T2 10.7MHz R11 10K C16 120p 1 C20 10n C15 C14 10nF 10nF 16 15 TP4 DSOUT VCC2 R10 1.8K 14 13 12 11 10 C10 C11 C12 1u 3.3n 56p 9 IFIP GND2 SHEN RSSI DSO SHO DSIN IFN S1T8531 VCC2 QOUT BIN BOUT DSIP GND1 VCC1 QIN 1 GND 2 3 4 5 6 7 8 R8 1 C1 3.3n C2 56p R1 51 R7 39K VCC2 L1 CX1 CX1 R2 R6 Quad. coil C3 3.3nF C4 56p VCC C6 56p R3 51 R5 20K R4 20K VCC2 * Changable value for each application 10 C5 100n VCC Analog Digital C7 68p 100p C8 100p 220p TP2 BUFOUT C9 4.7n 820p *C7 68p *C8 100p 1 AUDIOOUT TP3 1 TP1 QUADOUT R9 5.6K *C9 4.7n 15K VCC1 1 POWER 1 51 VCC1 POWER * Quadrature Coil Quad. coil Ext. coil L1 360u 2.7u CX1 120p 56p CV1 N/A 1-3p R2 7.5K 2.4K