S3C820B 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C-SERIES MICROCONTROLLERS Samsung’s S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C820B MICROCONTROLLER The S3C820B single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung’s newest CPU architecture. — Four programmable I/O ports, excluding one BUZ pin, for a total of 32 pins. The S3C820B is the microcontroller which has 64K-byte mask-programmable ROM and 192K-byte mask ROM for font data. — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). Using a proven modular design approach, Samsung engineers developed the S3C820B by integrating the following peripheral modules with the powerful SAM87 core: — Watch timer for real time. — Eight bit-programmable pins for external interrupts. — One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. The S3C820B is a versatile microcontroller for data bank or dictionary. It is currently available in a 128pin QFP package. 1-1 PRODUCT OVERVIEW S3C820B FEATURES CPU LCD Controller/Driver • • 65 segments and 18 common terminals • Internal resistor circuit for LCD bias • Voltage doubler • All dot can be switched on/off SAM87 CPU core Memory • 64K-byte internal program memory (ROM) • 192K-byte internal memory (ROM) for font data • 272-byte internal register file (Excluding LCD RAM) • 6144-byte data RAM Instruction Set • 78 instructions • IDLE and STOP instructions added for power-down modes Instruction Execution Time • 1.5 µs at 4 MHz fx (minimum) • 183 µs at 32,768 Hz fxt Timers and Timer/Counters • One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function • One 8-bit timer/counter (Timer 0) with three operating modes; Interval, Capture and PWM • One 16-bit timer/counter (Timer 1) with two 8-bit timer/counter modes; Interval Power-Down Modes • Idle mode (CPU clock stops) • Stop mode (main oscillation and CPU clock stops) Interrupts • Five interrupt levels and 15 interrupt sources Operating Temperature Range • 15 vectors (15 sources have a dedicated vector address) • • Fast interrupt processing feature (for one selected interrupt level) Operating Voltage Range I/O Ports • Four 8-bit I/O ports (P0–P3) for a total of 32-bit programmable pins • Eight input pins for external interrupts • One output only pin for BUZ Watch Timer • Interval time: 3.91 ms, 1s at 32,768 Hz • Four frequency outputs to BUZ pin and BUZ pin • Clock source generation for LCD 1-2 – 40 °C to + 85 °C • 2.2 V to 4.5 V at 1 MHz fx • 2.7 V to 4.5 V at 4 MHz fx Package Type • 128-pin QFP S3C820B PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 (A8-A15) P1.0-P1.7 (AD0-AD7) Port 0 Port 1 RESET TEST Internal Bus Basic Timer XIN XOUT Port 2 I/O Port and Interrupt Control Main OSC Port 3 XTIN XTOUT BUZ BUZ Sub OSC SAM8 CPU LCD Driver/ Controller Watch Timer 64K-byte ROM T0 314-Byte Register File Voltage Doubler P2.0-P2.3 (AS, DW, DR, DM) P2.4-P2.7 (T0, T0CK, CLO, BUZ) P3.0/TB/INT0 P3.1/TA/INT1 P3.2/T1CK/INT2 P3.3/INT3 P3.4/INT4 P3.5/INT5 P3.6/INT6 P3.7/INT7 COM0-COM8 COM9-COM17 SEG0-SEG64 VLC0 BIAS CA CB TA Timer 0 T0CK Timer 1 TB T1CK 192K-byte Font ROM 6144-Byte Data RAM Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C820B 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 S3C820B (128-QFP-1420) P1.4/AD4 P1.3/AD3 P1.2/AD2 P1.1/AD1 P1.0/AD0 P3.0/TB/INT0 P3.1/TA/INT1 P3.2/T1CK/INT2 P3.3/INT3 P3.4/INT4 P3.5/INT5 P3.6/INT6 P3.7/INT7 P2.0/AS P2.1/DW P2.2/DR P2.3/DM P2.4/T0 P2.5/T0CK P2.6/CLO P2.7/BUZ BUZ CA CB VLC0 BIAS 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P1.7/AD7 P1.6/AD6 P1.5/AD5 Figure 1-2. Pin Assignment (128-Pin QFP Package) 1-4 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 S3C820B PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions P0.0–P0.7 I/O I/O port with nibble-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; also configurable as external interface address lines A8–A15. 3 35–28 A8–A15 P1.0–P1.7 I/O Same general characteristics as port 0; also configurable as external interface address/data lines AD0–AD7. 3 43–36 AD0–AD7 P2.0–P2.3 I/O I/O port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-ups. Lower nibble pins 0–3 are configurable for external interface signals. 5 52–55 AS, DW, DR, DM P2.4–P2.7 I/O P2.4/capture input, interval/PWM output (T0) P2.5/timer 0 clock input (T0CK) P2.6/system clock output (CLO) P2.7/buzzer signal output (BUZ) 6 56–59 T0, T0CK, CLO, BUZ P3.0–P3.7 I/O I/O port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-up; P3.0–P3.7 are alternately used for external interrupt input (noise filters, interrupt enable and pending control); P3.0/timer B clock output (TB)/INT0 P3.1/timer 1/A clock output (TA)/INT1 P3.2/timer 1/A clock input (T1CK)/INT2 4 44–51 TB/INT0, TA/INT1, T1CK/INT2, INT3–INT7 T1CK I/O Timer A external clock input pins. 4 46 P3.2/INT2 TB TA I/O Timer B and 1/A clock output pins. 4 44 45 P3.0/INT0 P3.1/INT1 AS, DW, DR, DM I/O Output pins for external interface control signals. AS: address strobe DW: data memory write DR: data memory read DM: data memory select 5 52–55 P2.0–P2.3 T0 I/O Capture input or interval/PWM output. 6 56 P2.4 T0CK I/O Timer 0 clock input. 6 57 P2.5 1-5 PRODUCT OVERVIEW S3C820B Table 1-1. Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions CLO I/O Clock output 6 58 P2.6 BUZ I/O Output pin for buzzer signal. 6 59 P2.7 BUZ O Inverted buzzer signal output. – 60 – INT0–INT7 I/O External interrupt input pins. 4 44–51 P3.0/TB, P3.1/TA, P3.2/T1CK, P3.3–P3.7 AD0–AD7 I/O Address low and data ports. 3 43–36 P1.0–P1.7 A8–A15 I/O Address high output ports. 3 35–28 P0.0–P0.7 COM0–COM8 O LCD common signal output. 7 73–65 – COM9– COM17 O LCD common signal output. 7 11–19 – SEG0– SEG64 O LCD seg signal output. 8 10–1 128–74 – CA, CB – Capacitor terminal for voltage doubling. – 61, 62 – VLC0 – LCD power supply. – 63 – BIAS O Bias voltage level for LCD driving. – 64 – RESET I System reset pin 2 27 – XTIN, XTOUT – Crystal oscillator pins for sub clock. – 25, 26 – TEST I Test signal input (must be connected to VDD). – 24 – XIN, XOUT – Main oscillator pins – 23, 22 – VDD, VSS – Power input pins – 20, 21 – 1-6 S3C820B PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-up Resistor P-Channel In In N-Channel Schmitt Trigger Figure 1-3. Pin Circuit Type 1 Figure 1-4. Pin Circuit Type 2 (RESET RESET) VDD Pull-up Resistor Pull-up Enable VDD Data I/O Open-drain Output Disable VSS Input Figure 1-5. Pin Circuit Type 3 (Ports 0, 1) 1-7 PRODUCT OVERVIEW S3C820B PIN CIRCUIT DIAGRAMS (Continued) VDD Pull-up Resistor Pull-up Enable VDD Data I/O Output Disable External Interrupt Input Noise Filter VSS Input Figure 1-6. Pin Circuit Type 4 (Port 3) 1-8 S3C820B PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS (Continued) VDD Pull-up Resistor Pull-up Enable Select VDD Port 2 (Low Byte) Data External Interface (AS, DW, DR, DM) M U X Data I/O Output Disable VSS Input Figure 1-7. Pin Circuit Type 5 (Ports 2.0–2.3) VDD Pull-up Resistor Pull-up Enable VDD Data I/O Output Disable VSS Input Figure 1-8. Pin Circuit Type 6 (Ports 2.4–2.7) 1-9 PRODUCT OVERVIEW S3C820B PIN CIRCUIT DIAGRAMS (Continued) VLC0 VLC1 COM Out VLC4 VSS Figure 1-9. Pin Circuit Type 7 (COM0–COM17) VLC0 VLC2 SEG Out VLC3 VSS Figure 1-10. Pin Circuit Type 8 (SEG0–SEG64) 1-10 S3C820B 15 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C820B electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a Reset — I/O capacitance — A.C. electrical characteristics — Input timing for external interrupts (port 0, P2.3–P2.0) — Input timing for RESET — Oscillation characteristics — Oscillation stabilization time 15-1 ELECTRICAL DATA S3C820B Table 15-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – – 0.3 to + 5.5 V Input voltage VIN Ports 0, 1, 2, and 3 – 0.3 to VDD + 0.3 V Output voltage VO All output pins – 0.3 to VDD + 0.3 V Output current High IOH One I/O pin active – 18 mA All I/O pins active – 60 One I/O pin active + 30 Total pin current for ports 0–3 + 100 Output current Low IOL mA Operating temperature TA – – 40 to + 85 °C Storage temperature TSTG – – 65 to + 150 °C 15-2 S3C820B ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.2 V to 4.5 V) Parameter Symbol Conditions Min Typ Max Unit – VDD V VIH1 All input pins except VIH2 and VIH3 0.8 VDD VIH2 RESET 0.8 VDD VDD VIH3 XIN, XTIN VDD – 0.5 VDD VIL1 All input pins except VIL2 and VIL3 VIL2 RESET VIL3 XOUT, XTOUT Output High voltage VOH VDD = 3.0 V; IOH = – 1 mA All output pins Output Low voltage VOL Input High leakage current Input High voltage Input Low voltage 0 – 0.2 VDD 0.2 VDD 0.5 VDD – 1.0 – – VDD = 3.0 V; IOL= 2 mA All output pins – – 1.0 ILIH1 VIN = VDD; all input pins except XIN, XOUT, XTIN, and XTOUT – – 1 ILIH2 VIN = VDD; XIN, XOUT, XTIN, and XTOUT ILIL1 VIN = 0 V; all input pins except XIN, XOUT, XTIN, and XTOUT ILIL2 VIN = 0 V; XIN, XOUT, XTIN, and XTOUT Output High leakage current ILOH VOUT = VDD All output pins – – 1 Output Low leakage current ILOL VOUT = 0 V All output pins – – –1 Input Low leakage current µA 20 – – –1 – 20 15-3 ELECTRICAL DATA S3C820B Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 2.2 V to 4.5 V) Parameter Symbol Conditions Min Typ Max Unit V Middle output VOM1 VMN = VLCD – (N/5) COM0–17 VM1 – 0.2 VM1 VM1 + 0.2 voltage VOM2 × VLCD SEG0–64 VM2 – 0.2 VM2 VM2 + 0.2 VOM3 N = 1, 2, 3, and 4 SEG0–64 VM3 – 0.2 VM3 VM3 + 0.2 COM0–17 VM4 – 0.2 VM4 VM4 + 0.2 VOM4 |VLCD–VCOMi| voltage drop (i = 0–17) VDC VLCD = 3.0 V to 6.0 V – 15 µA per common pin – – 120 mV |VLCD–VSEGx| voltage drop (x = 0–64) VDS VLCD = 3.0 V to 6.0 V – 15 µA per common pin – – 120 mV LCD driving voltage VLCD – 3.0 – 6.0 V RL1 VIN = 0 V; TA = 25 °C; VDD = 3.0 Ports 0, 1, 2, and 3 30 80 200 kΩ RL2 VIN = 0 V; TA = 25 °C; VDD = 3.0 300 500 800 Pull-up resistors RESET only LCD voltage dividing resistor RLCD VLCD = 3.0 V to 6.0 V TA = 25 °C 40 60 80 kΩ Supply current IDD1 VDD = 3.0 V ± 10% 2 MHz crystal – 1.5 3.5 mA IDD2 Idle mode; VDD = 3.0 V ± 10% 2 MHz crystal 0.5 1.5 IDD3 VDD = 3.0 V ± 10% 32 kHz crystal 30 70 IDD4 Idle mode; VDD = 3.0 V ± 10% 32 kHz crystal 6 12 IDD5 Stop mode; VDD = 3.0 V ± 10% XTIN = 0 V 0.5 1 (note) µA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, voltage doubler, or external output current loads. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 15-4 S3C820B ELECTRICAL DATA Table 15-3. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 2.2 – 4.5 V Data retention supply current IDDDR – – 5 µA Release signal set time tSREL 0 – – µs Oscillator stabilization wait time tWAIT – 216/fx (1) – ms – (2) – VDDDR = 2.2 V – Released by RESET Released by interrupt NOTES: 1. fx is the main oscillator frequency. 2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON. Idle Mode (Basic Timer Active) ~ ~ Normal Operating Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction 0.8 VDD tWAIT Interrupt Request Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt 15-5 ELECTRICAL DATA S3C820B Oscillation Stabilization Time RESET Occurs ~ ~ Normal Operating Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR tSRL Execution of STOP Instrction RESET 0.8 VDD 0.2 VDD tWAIT Figure 15-2. Stop Mode Release Timing When Initiated by a RESET 15-6 S3C820B ELECTRICAL DATA Table 15-4. Input/Output Capacitance (TA = – 40 °C to + 85 °C, VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS – – 10 pF Output capacitance COUT Min Typ Max Unit ns I/O capacitance CIO Table 15-5. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Interrupt input, High, Low width tINTH, tINTL P3.0–P3.7 VDD = 3 V 500 700 – RESET input Low width tRSL Input VDD = 3 V 2000 – – Min Typ Max Unit 2 VDD – 0.5 2 VDD 2 VDD + 0.5 V Table 15-6. Voltage Doubler Output (TA = – 40 °C to + 85 °C) Parameter Voltage Doubler Output Symbol VBIAS Conditions VDD = 3 V ± 10 % only tINTL tINTH 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 15-3. Input Timing for External Interrupts (P3.0–P3.7) 15-7 ELECTRICAL DATA S3C820B tRSL RESET 0.3 VDD Figure 15-4. Input Timing for RESET Table 15-7. Main Oscillation Characteristics (TA = – 40 °C + 85 °C, VDD = 2.2 V to 4.5 V) Oscillator Crystal Clock Circuit XIN XOUT C1 XOUT C1 15-8 Typ Max Unit CPU clock oscillation frequency 0.4 – 4 MHz CPU clock oscillation frequency 0.4 – 4 MHz XIN input frequency 0.4 – 4 MHz Frequency, VDD = 3 V 0.4 – 2 MHz C2 External clock RC Min C2 Ceramic XIN Conditions XIN XOUT XIN XOUT S3C820B ELECTRICAL DATA Table 15-8. Sub Oscillation Characteristics (TA = – 40 °C + 85 °C, VDD = 2.2 V to 4.5 V) Oscillator Crystal Clock Circuit XIN XOUT C1 Min Typ Max Unit CPU clock oscillation frequency 32 32.768 35 kHz XTIN input frequency 32 – 500 kHz C2 External clock XIN Conditions XOUT Table 15-9. Main Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 3.0 V ± 10 %) Oscillator Test Condition Min Typ Max Unit Crystal fx > 400 kHz – – 80 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 50 ms External clock XIN input High and Low width (tXH, tXL) 25 – 700 ns 1/fx tXL tXH XIN VDD - 0.5 V 0.5 V Figure 15-5. Clock Timing Measurement at XIN 15-9 ELECTRICAL DATA S3C820B Table 15-10. Sub Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 3.0 V ± 10 %) Oscillator Crystal External clock Test Condition Min Typ Max Unit – – 1.0 2 s 1 – 18 µs XIN input High and Low width (tXH, tXL) 1/fxt tXTL tXTH XTIN VDD - 0.5 V 0.5 V Figure 15-6. Clock Timing Measurement at XTIN 15-10 S3C820B ELECTRICAL DATA Instruction Clock fx (Main oscillation frequency) 666 kHz 4 MHz 2 MHz 1 MHz 333 kHz 167 kHz 400 kHz 8.32 kHz 2 3 2.2 2.4 2.7 4 5 4.5 Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency ( n = 1, 2, 8, 16) Figure 15-7. Operating Voltage Range 15-11 S3C820B MECHANICAL DATA 16 MECHANICAL DATA OVERVIEW The S3C820B microcontroller is currently available in a 128-pin TQFP package. 22.00 ± 0.30 0-8 20.00 ± 0.20 + 0.10 14.00 ± 0.20 0.10 MAX #128 #1 0.50 0.20 0.50 ± 0.20 128-QFP-1420 (0.75) 16.00 ± 0.30 0.15 - 0.05 + 0.10 - 0.05 0.05 MIN (0.75) 0.10 MAX 2.10 ± 0.10 2.40 MAX 0.10 MAX 0.50 ± 0.20 NOTE: Dimensions are in millimeters. Figure 16-1. 128-Pin TQFP Package Mechanical Data 16-1