UCC2585 UCC3585 PRELIMINARY Low Voltage Synchronous Buck Controller FEATURES DESCRIPTION • Resistor Programmable 1.25V to 4.5V VOUT The UCC2585/UCC3585 synchronous Buck controller provides flexible high efficiency power conversion for output voltages as low as 1.25V with guaranteed ±1% DC accuracy. Output currents are only limited by the choice of external logic level MOSFETs. With an input voltage range of 2.5V to 6.0V it is the ideal choice for 3.3V only, battery input, or other low voltage systems. Applications include local microprocessor core voltage power supplies for desktop and Notebook computers, and high speed GTL bus regulation. Its fixed frequency oscillator is capable of providing practical PWM operation to 700kHz. • 2.5V to 6V Input Supply Range • 1% DC Accuracy • High Efficiency Synchronous Switching • Drives P-channel (High Side) and N-channel (Low Side) MOSFETs With its low voltage capability and inherent “always on” operation, the UCC2585/UCC3585 causes VOUT to track VIN once VIN has exceeded the threshold voltage of the external P channel MOSFET. Tracking can be tailored for any application with a single resistor or disabled by connecting TRACK to VIN. For dual supply rail microprocessors this feature negates the need for external diodes to insure supply voltage tracking between the +3.3V and lower voltage microprocessor core supplies. • Lossless Programmable Current Limit • Logic Compatible Shutdown • Programmable Frequency • Start-up Voltage Tracking Protects Dual Rail Microprocessors (continued) TYPICAL APPLICATION DIAGRAM VIN C8 0.47µF R3 27.4k R1 10k + + C1 150µF C2 150µF 15 VIN CLSET 8 R5 3 C7 147pF 1 ENB 2 COMP PDRV 12 R2 549k Q1 IRF7404 L1 4.7µF ISENSE 11 R6 3 4 VFB NDRV 14 VOUT Q2 IRF7401 + + C9 220µF C4 3.2N 10 SD TRACK 6 3 SS N/C 9 16 CT PWRGND 13 7 ISET + C10 220µF C11 220µF R12 32k R10 36k C5 0.22µF C6 470pF GND 5 R11 82k R4 100k RTN RTN UDG-98024 07/99 UCC2585 UCC3585 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Analog Pins Minimum and Maximum Forced Voltage (Reference to GND) . . . . . . . . . . . . . . . . . . . –0.3V to +6.3V Digital Pins Minimum and Maximum Forced Voltage (Reference to GND) . . . . . . . . . . . . . . . . . . . . .–0.3V to 6.3V Power Driver Output Pins Maximum forced current . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0A Operating Junction Temperature . . . . . . . . . . –55°C to +125°C Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C DIL-16, SOIC-16, SSOP-16 (TOP VIEW) J, N, D, and M Packages Note: Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of, the specified terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns. APPLICATIONS • Low Voltage Microprocessor Power such as PowerPC 603 and 604 ENB 1 16 CT COMP 2 15 VIN SS 3 14 NDRV VFB 4 13 PWRGND GND 5 12 PDRV TRACK 6 11 ISENSE ISET 7 10 SD CLSET 8 9 N/C • High Power 5V or 3.3V to 1.25V–4.5V Regulators • GTL Bus Termination DESCRIPTION (cont.) The UCC2585/UCC3585 drives a complementary pair of power MOSFET transistors, P-channel on the high side, and N-channel on the low side to step down the input voltage at up to 90% efficiency. secutive faults, or latch-off after fault detection, allowing maximum application flexibility. The current limit threshold is programmed with a single resistor selected to match system MOSFET characteristics. A programmable two-level current limiting function is provided by sensing the voltage drop across the high side P channel MOSFET. This circuit can be configured to provide pulse-by-pulse limiting, timed shutdown after 7 con- The UCC2585/UCC3585 also includes undervoltage lockout, a logic controlled enable, and softstart functions. The UCC2585/UCC3585 is offered in the 16 pin surface mount and through hole packages. 2 UCC2585 UCC3585 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the UCC3585, and TA = –40°C to 85°C for the UCC2585. TA = TJ. VIN = 3.3V, ENB, ISENSE = VIN, VFB = 1.25V, COMP = 1.5V, CT = 330pF, RISET = 100k, RTRACK = 10k, RCLSET = 10k. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Supply Section Supply Current – Total (Active) Supply Current – Shutdown 2.3 ENABLE = 0V 3.5 mA µA 10 25 VIN Turn On Threshold (UVLO) 2.35 2.60 V VIN Turn On Hysteresis 450 550 mV V Voltage Amplifier Section Input Voltage (Internal Reference) TA = 0°C to 70°C, VIN = 3.0V to 3.6V, Note 1 1.238 1.250 1.262 Input Voltage (Internal Reference) VIN = 3.0V to 3.6V, IND/MIL Temp, Note 1 1.228 1.250 1.273 Open Loop Gain COMP = 0.5 to 2.5V 65 80 Output Voltage High I(COMP) = –50µA Output Voltage Low I(COMP) = 50µA 3.00 3.25 0.10 Output Source Current Output Sink Current V dB V 0.25 V –100 –175 µA 0.4 1.0 mA Oscillator/PWM Section Initial Accuracy TJ = 25°C 405 450 495 kHz Initial Accuracy Over Temperature 390 450 510 kHz 1.8 2.1 2.4 V 0.3 0.4 CT Ramp Peak to Valley CT Ramp Valley Voltage PWM Maximum Duty Cycle COMP = 3V, Measured on PDRV PWM Minimum Duty Cycle COMP = 0.2V, Measured on PDRV PWM Delay to Outputs COMP = 2.5V Tracking Current Measured on TRACK, VTRACK = 1.6V Enable High Threshold Measured on ENABLE (Note 3) V 100 % 0 45 10 12 % ns 15 2.8 µA V Enable Low Threshold Measured on ENABLE Softstart Charge Current SS = 0V –10 –14 0.5 –18 µA V Measured Between VIN and ISENSE 100 125 150 mV 11 14 16 µA 8 13 18 µA –100 –140 µA 0.55 0.90 V Current Limit Section Pulse to Pulse Threshold CLSET Current SD Sink Current SD = 2V SD Source Current SD = 2V Restart Threshold Measured on SDOWN 0.40 Output Driver Section (PDRV, NDRV) Pull Up Resistance –100mA (Source) TA = 25° C 6 Ω Pull Down Resistance 100mA (Sink) TA = 25° C 4 Ω Deadtime Delay Note 2 150 Note 1. Measured on COMP with the Error Amp in a Unity Gain (voltage follower) configuration. Note 2. 50% point of PDRV Rise to NDRV Rise and 50% point of NDRV Fall to PDRV Fall. Note 3. Enable High Threshold = VIN –0.5. 3 200 250 ns UCC2585 UCC3585 BLOCK DIAGRAM TRACK ISET CLSET 6 7 8 PRECISION BIAS SET CURENT LIMIT ADJ UVLO 2V 10µA VIN 15 TRACK 1.25V UVLO CURRENT LIMIT 11 ISENSE DRIVER 1.25V REF ENB 1 12 PDRV ENABLE TRACK VIN –0.8V COMP VFB ANTI SHOOT THRU PWM 2 RD Q PWM LATCH 10µA 4 S 1.25V SS Q 3 9 14 NDRV REVERSE PRECISION BIAS NC DRIVER UVLO SOFTSTART COMPLETE 13 PWRGND OVER CURRENT COUNTER SHUTDOWN TIMER SOFTSTART COMPLETE REVERSE CURRENT LOGIC CLK OSCILLATOR H = NO OVERCURRENT REVERSE 10µA 16 5 10 CT GND SD DISABLE DRIVERS L = NO SHUTDOWN H = LATCHED SHUTDOWN CAP = TIMED SHUTDOWN UDG-98008 PIN DESCRIPTIONS Use capacitor values greater than 100pF in order to minimize the effects of stray capacitance. The oscillator is capable of reliable operation in excess of 1MHz. CLSET: CLSET is used to program the pulse by pulse and overcurrent shutdown levels for the UCC1585. A resistor is connected between CLSET and VIN to set the thresholds. The threshold follows the following relationship: ENB: A LOGIC1 (VIN–0.5V) on this input will activate the Output drivers. A logic zero (0.5V) will prevent switching of the output drivers. Do not allow ENB to remain between these levels steady state. 1. 25 • RCLSET RISET lcl = RDS (on ) GND: Reference level for the IC. All voltages and currents are with respect to GND. COMP: Output of the Voltage type error amplifier. Loop compensation components are connected between COMP and VFB. ISENSE: ISENSE performs two functions. The first is to monitor the voltage dropped across the high side P channel MOSFET switch while it is conducting. This information is used to detect over current conditions by the current limit circuitry. The second function of ISENSE is to measure current through the lowside N-channel MOSFET. When the current flow through this MOSFET is drain to source, (i.e. reversed), this FET is turned off for the remainder of the switching cycle. CT: A high quality ceramic capacitor connected between this pin and ground sets the PWM oscillator frequency by the following relationship: F= 1 (6700 • CT ) 4 UCC2585 UCC3585 PIN DESCRIPTIONS (cont.) ISET: A resistor is connected between ISET and ground to program a precision bias for many of the UCC2585/UCC3585 circuit blocks. Allowable resistor values are 90kΩ to 110kΩ. 1.25V is provided to ISET via a buffered version the internal bandgap voltage reference. The resultant current is 1.25V / RISET.This current is mirrored directly over to CLSET to program the over current thresholds. A second use for this current is to set a basis for the charging current of the oscillator. SS: A low leakage capacitor connected between SS and GND will provide a softstart function for the converter. The voltage on this capacitor will slowly charge on startup via an internal current source. The output of the Voltage error amplifier (COMP) tracks this voltage thereby limiting the controller duty ratio. NDRV: High current driver output for the low side MOSFET switch. A 3Ω to 10Ω series resistor between NDRV and the MOSFET gate may be inserted to reduce ringing on this pin. In some layout situations, a low VF diode may be required from this pin to ground to keep the pin from ringing more than 0.5V below ground. PDRV: High current driver output for the high side P channel MOSFET switch. A 3Ω to 10Ω series resistor between PDRV and the MOSFET gate may be inserted to reduce ringing on this pin. In some layout situations, a low VF diode may be required from this pin to ground to keep the pin from ringing more than 0.5V below ground. TRACK: A resistor is connected between TRACK and output voltage of the converter to set the start-up profile of the power converter. Certain dual supply rail microprocessors require that a maximum voltage differential between the supply rails is not exceeded. Failure to do so results in large currents in the microprocessor through the ESD (electrostatic discharge) protection devices. This can result in chip failure. The UCC2585/UCC3585 is designed such that it is “normally on” before VIN reaches the 2.0V (nom.) UVLO threshold. That is, the high side P channel MOSFET switch driver output is actively held low allowing the MOSFET to conduct current to the output as soon as VIN is high enough to exceed the gate turn on threshold. The resistor from TRACK to VOUT sets the voltage level on VOUT at which the P channel MOSFET is turned off. The tracking cutoff voltage follows the following relationship: PWRGND: High current return path for the MOSFET drivers. PWRGND and GND should be terminated together as close to the IC package as possible. SD: This pin can configure current limit to operate in any one of three different ways. 1) A forced voltage of less than 250mV on SD inhibits the shutdown function causing pulse by pulse limiting. 2) A capacitor from SD to GND provides a controller-converter shutdown timeout after 7 consecutive overcurrent signals are received by the current limit circuitry. An interval 10µA (typ) current source discharges the SD capacitor to the 0.5V (typ) restart threshold. The shutdown time is given by: TSHUT = VOUT (max) = 1. 25 V + 12 µ A • (RTRACK ) [C SD • (VIN − 0 .5)] 10 µ A , This is necessary for very low output voltage applications (< 2.0V), where overvoltage may occur if the Pchannel MOSFET is not disabled before the UVLO threshold is reached. For applications with VOUT greater than 2.0V, TRACK can be disabled by tying TRACK to VIN. where CSD is the value of the capacitor from SD to GND, and VIN is the chip supply voltage (on pin 15). At this point, a softstart cycle is initiated, and a 100µA current (typ) quickly recharges SD to VIN. During softstart, pulse by pulse limiting is enabled, and the 7 cycle count is delayed until softstart is complete (i.e. charged to approximately VIN volts). VFB: Inverting input to the Voltage type error amplifier. The common mode input range for VFB extends from GND to 1.5V. VIN: Supply voltage for the UCC2585/UCC3585.Bypass with a 0.1µF ceramic capacitor (minimum) to supply the switching transient currents required by the external MOSFET switches. 3) A forced voltage of greater than 1V on SD will cause the UCC2585/UCC3585 to latch OFF after 7 overcurrent signals are received. After the controller is latched off, SD must drop below 250mV to restart the controller. 5 UCC2585 UCC3585 APPLICATION INFORMATION Some of today’s microprocessors require very low operating voltages. In some cases, as low as 1.8V of supply voltage are required in addition to already available 3.3V system voltage. Following is an illustration of a design using the UCC3585 as the power controller. δ= VOUT 1.8 = = 0.545 VIN 3 .3 2) Select the output inductor to meet ripple current requirements. For this design, the allowable ripple current in the output inductor is selected to be 10% of the full load output current. The design criteria are as follows: • Input Voltage (VIN) 3.3V DC L1 = • Output Voltage (VOUT) 1.8V DC • Output Ripple Voltage (VOUT) 18mV (VIN − VOUT ) • δ = 4 .6 µH FS • 0 .1 • IOUT A Pulse Engineering SMT inductor (PE-53682) is 4.7µH has a DC resistance (RL1) of 8.3mΩ and will dissipate 0.1W under full load operation. • Output Current (IOUT) 3.5A DC Other features include The resulting ∆IOUT is now: • Output Tracking ∆ IOUT = • Switching Frequency (FS) 350kHz • 100% Surface Mount (VIN − VOUT ) 4 .7 • 10 −6 δ = 0 .5 A FS • 3) Next, the output capacitors are determined based upon the output ripple criteria. Assuming the ripple is limited by the equivalent series resistance, or ESR, of the capacitors and not the impedance of the capacitors at the switching frequency, then the output capacitor selection is based upon ESR, size and voltage considerations. The first few steps in the design are to define the power stage (Schematic Fig. 1). 1) The normal operating duty cycle (δ) of the regulator is approximately VIN C8 0.47µF R3 27.4k R1 10k + + C1 150µF C2 150µF 15 VIN CLSET 8 R5 3 C7 147pF 1 ENB 2 COMP PDRV 12 R2 549k Q1 IRF7404 L1 4.7µF ISENSE 11 R6 3 4 VFB NDRV 14 VOUT Q2 IRF7401 + + C9 220µF C4 3.2N 10 SD TRACK 6 3 SS N/C 9 16 CT PWRGND 13 7 ISET + C10 220µF C11 220µF R12 32k R10 36k C5 0.22µF C6 470pF GND 5 R11 82k R4 100k RTN RTN UDG-98024 Figure 1. Application circuit schematic. 6 UCC2585 UCC3585 APPLICATION INFORMATION (cont.) ESR = ∆ VOUT 0 .018 = = 0 .026 Ω ∆ IOUT 0 .5 and a body diode turn OFF switching time (tOFF2) of 59ns. In this topology, the N Channel MOSFET, Q2, is turned OFF prior to the turn ON of Q1, so when Q2 is turned OFF, current is being re-routed from the channel of the device into the intrinsic body diode. Therefore Q2’s intrinsic body diode incurs switching loss during the turn OFF interval. A 220µF, 6.3V Sprague 594D capacitor has an ESR of 75mΩ. Three of these in parallel will result in an overall ESR of 25mΩ. (C9, C10, and C11 in Fig. 1). Since the output ripple current is so low, the capacitor’s ripple current rating of 1.45A is not a concern. The conduction loss in Q2 is: To check the assumption that the capacitor’s impedance at the switching frequency is dominated by the ESR and not the capacitor’s capacitance value, calculate the impedance and compare it to the ESR. PD Q 2ON = ID Q 2 RMS 2 • RDS ON Q 2 = 0. 2W The gate drive losses will be PD Q 2 GATE = QG 2 • VIN • FS = 55 mW 1 1 ZC = = = 2mΩ 2π • FS • C 2π • 350k • 220 µ And the body diode turn OFF loss: PD Q 2 D _ OFF = The ESR of the capacitor is 37 times that of the impedance of the capacitor at the switching frequency, so the earlier assumption was valid. The total power loss for Q2 is the sum of these three: PD Q 2 TOTAL = 0 . 4W 4) Before selecting the switching MOSFETs, the current that will be flowing through them must first be determined. ID PK = IOUT + 7) Thus far the power loss in the two MOSFETs and the output inductor total 1.0W. The average input current is: ∆ IOUT = 3 .8 A 2 IINAVG = The RMS of this current in Q1 is ID Q1RMS = ID PK VOUT • IOUT + PLOSS = 2 . 2A VIN The peak to peak ripple in the input capacitors is the peak current less the average input current during Q1’s ON time, and equal to the average input current during Q1’s OFF time. The RMS value of this current is then: δ = 2 .8 A And in Q2 ID Q 2RMS = ID PK 1 − δ = 2 .5 A IIN _ CAPRMS = (ID PK − IINAVG ) 2 • δ + (IINAVG ) 2 • (1 − δ ) = 1.9 A 5) Since this regulator must be able to operate from a 3.3V source, the MOSFETs used must have a gate threshold level of no more than 2V. 8) After the input capacitor’s input ripple current is known, select the input capacitors. Again, Sprague 594D Solid Tantalum capacitors are chosen. A single 150µF, 10V capacitor has a ripple current rating of 1.35A RMS. Two in parallel (C1 and C2) will have a combined capability of 2.7A, and a total ESR of 40mΩ. The losses in the capacitors are: For Q1, an IRF7404 is selected. It has an RDS(on) of 0.04Ω, a total gate charge (QG1) of 50nC, and a turn OFF (tOFF1) time of 65ns. The conduction loss in Q1 will be: PD Q1 ON = ID Q1 RMS 2 • RDS ON Q1 = 0.593 W PDIN _ CAP = IIN _ CAPRMS The gate drive losses will be PD Q1 GATE = QG1 • VIN • FS = 58 mW 2 • ESR = 0 .14W Adding the capacitor loss to that previously found, the total losses are now 2.1W. And finally the turn OFF losses are estimated PD Q1 OFF = 1 •V • I • TOFF 2 • FS = 0 .13 W 2 IN D PK 9) The overall efficiency of the power train is then 1 • V • I Q1 • TOFF 1 • FS = 0 .14W 2 IN D PK E FF = The total power loss for Q1 is the sum of these three: PD Q1 TOTAL = 0 .5 W VOUT • IOUT = 0 .84 VOUT • IOUT + 2 .1 The losses are dominated by the MOSFETs Q1 and Q2. One way to improve the efficiency would be to reduce the conduction loss in Q1, either by choosing a device with a 6) Q2 has been selected to be an IRF7401, which has an RDS(ON) of 0.03Ω, and a total gate charge (QG2) of 48nC 7 UCC2585 UCC3585 APPLICATION INFORMATION (cont.) lower RDS(on) or by paralleling it with another MOSFET. The conduction losses in Q2 may be improved by the same technique, but will prove detrimental in switching losses. To lower the switching losses, Q2 may be paralleled with a Schottky diode. In this manner, the switching loss may be absorbed by the Schottky, instead of the MOSFET. 11) The voltage divider is next determined to give us the proper output voltage. First select one of the divider resistors R11 = 82k. The other resistor becomes: R10 = R11 • 12) The equation for the error amplifier in this configuration is: 10) After the power stage design is completed, attention is given to the feedback loop. The LC filter gain is described by the equation (10A) below: (where ω= j2πf) For a gain of 5 and a zero at 2kHz R 2 = 15 • R10 = 180 k There will be a double pole at: 1 2π L1 • COUT and = 2 .8 kHz C7 = and a zero at the point where the impedance of the output capacitors equals the ESR: FZ = 1 2π • RESR • COUT VIN VRAMP 1 = 440 pF 2π • fp • R 2 The overall voltage loop gain now has a crossover at 34kHz with a phase margin of about 73 degrees. = 9 .6 kHz 13) Select the RISET resistor, R3, to be 100k. (The range of value should be between 90k and 110k.) Then choosing the current limit trip point to be 130% of IOUT, the current limit set resistor is then found by the relationship The modulator gain is given by K PWM = 1 +R2 J 2π • f • C 7 = R10 K EA Where COUT is the combined capacitance of C9, C10, and C11 and RESR is the ESR of the capacitors. FP = VOUT − R11 = 36 k VREF =1.65 R3 = where VRAMP is the peak to peak amplitude of the oscillator ramp found on the CT pin. The overall open loop gain is shown in Fig. 2. 1.3 • IOUT • RDS( on )Q1 • RISET = 27. 2k 1. 25 Note that the RDS(on) value used should include the effects of temperature. 100 10 80 AMPLIFIER GAIN 60 GAIN (dB) GAIN (dB) 0 -10 -20 -30 40 20 0 OVERALL LOOP GAIN -20 -40 -40 10 100 1000 10000 FREQUENCY (Hz) -60 100000 10 Figure 2. Modulator and filter frequency response. (10A) KLC = 100 1000 10000 FREQUENCY (Hz) 100000 Figure 3. Error amp and closed loop frequency response. 1 + ω • RESR • COUT L1 1 + ω 2 • L1 • COUT + ω RL 1 • COUT + RESR • COUT + RLOAD 8 UCC2585 UCC3585 APPLICATION INFORMATION (cont.) 14) During normal power on of the UCC3585, the gate of Q1 is held low (Q1 turned ON) until the VCC input to the IC reaches the 2V Under Voltage Lockout (UVLO) voltage. At UVLO, the UCC3585 wakes up and switching begins on Q1 and Q2. With a 1.8V output however, the output will reach 2V before regulation begins! This is where the tracking function comes into use. By selecting an appropriate resistive divider from the output, we can select the point below UVLO at which Q1 will be shut off. Upon reaching UVLO, the UCC3585 will then begin to regulate normally. PHASE (DEGREES) 180 135 ERROR AMP 90 OVERALL LOOP 45 With a 1.8V nominal output voltage, select the tracking turn off point to be 1.6V. R3 = 0 10 1.6 − 1. 25 = 29 k Ω 12 µ 100 1000 10000 FREQUENCY (Hz) 100000 Figure 4. Error amp and closed loop frequency response. Note that the tracking function ONLY makes a difference below UVLO. If VOUT were to be 2V or above, then the tracking pin should be tied to VIN. POWER ON PROFILE WITHOUT "TRACK AND HOLD" 15) A capacitor on the SD pin will allow the converter to shutdown in the event seven consecutive over current pulses occur. If a timing shutdown interval of 1ms is chosen as the shutdown time, TSD, then the value of the capacitor is: C4= 1 1 (VIN – 0.5 ) • + ICHG IDICHG VOUT (V) TSD 2.0 1.5 1.0 = 3 . 2 nF 0.5 1.0 Where ICHG and IDISCHG are 100µA and 10µA respectfully. 2.0 VIN (V) 2.5 TS = 476 pF 6000 80 17) The softstart capacitor is selected for a 5ms startup time. Knowing that a 10µA current source will charge the capacitor to 2.5V, the softstart capacitor is given by: 60 RT kΩ A 470pF capacitor will result in a switching frequency of 354kHz. C5 = 1.5 Figure 5. Power on profile. 16) The next step is to find the value of timing capacitor. C6 = POWER ON PROFILE WITH "TRACK AND HOLD" TSS • ICHG 5 m • 10 µ = = 20 nF V SS 2 .5 40 20 1.2 1.4 1.6 1.8 2.0 VTR (V) Figure 6. Tracking resistor value as a function of turn off voltage. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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