SPICE Device Model Si7446DP Vishay Siliconix N-Channel 30-V (D-S), Fast Switching MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71720 24-May-04 www.vishay.com 1 SPICE Device Model Si7446DP Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1.89 V On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 759 A VGS = 10 V, ID = 19 A 0.0061 VGS = 4.5 V, ID = 17 A 0.0086 Static Drain-Source On-State Resistancea rDS(on) Ω Forward Transconductancea gfs VDS = 15 V, ID = 19 A 55 S Diode Forward Voltagea VSD IS = 4.3 A, VGS = 0 V 0.83 V VDS = 15 V, VGS = 5 V, ID = 19 A 14 Dynamicb Total Gate Chargeb Qg Gate-Source Chargeb Qgs Gate-Drain Chargeb Qgd Turn-On Delay Timeb td(on) 18 tr 37 Rise Timeb Turn-Off Delay Timeb b td(off) Fall Time tf Source-Drain Reverse Recovery Time trr 36 nC 12 VDD = 15 V, RL = 15 Ω ID ≅ 1A, VGEN = 10 V, RG = 6 Ω 39 ns 108 IF = 2.3 A, di/dt = 100 A/µs 49 Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71720 24-May-04 SPICE Device Model Si7446DP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71720 24-May-04 www.vishay.com 3