TI UCC28070

UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Two-Phase Interleaved CCM PFC Controller
FEATURES
APPLICATIONS
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
High-Efficiency Server and Desktop Power
Supplies
Telecom Rectifiers
•
DESCRIPTION
The UCC28070 is an advanced power factor
correction device that integrates two pulse-width
modulators (PWMs) operating 180° out of phase.
This Natural Interleaved PWM operation generates
substantial reduction in the input and output ripple
currents, and the conducted-EMI filtering becomes
easier and less expensive. A significantly improved
multiplier design provides a shared current reference
to two independent current amplifiers that ensures
matched average current mode control in both PWM
outputs while maintaining a stable, low-distortion
sinusoidal input line current.
The UCC28070 contains multiple innovations
including current synthesis and quantized voltage
feed-forward to promote performance enhancements
in PF, efficiency, THD, and transient response.
Features including frequency dithering, clock
synchronization, and slew rate enhancement further
expand the potential performance enhancements.
The UCC28070 also contains a variety of protection
features including output over-voltage detection,
programmable peak-current limit, in-rush current
detection, under-voltage lockout, and open-loop
protection.
Typical Application Diagram
VIN
L1
D1
+
VOUT
COUT
–
12V to 21V
To CSB
CCDR
1 CDR
DMAX 20
RRDM
2 RDM
RT 19
3 VAO
SS 18
RA
RB
4 VSENSE
GDB 17
5 VINAC
GND 16
RIMO
6 IMO
RSYN
7 RSYNTH
T1
RS
RDMX
RRT
CSS
M1
VCC 15
GDA 14
L2
8 CSB
VREF 13
9 CSA
CAOA 12
D2
To CSA
10 PKLMT
CAOB 11
RS
From Ixfrms
CZV
RPK1
CPV
CZC
T2
RA
CZC
CREF
CPC
CPC
M2
RPK2
RZV
RZC
RZC
RB
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
PRODUCT PREVIEW
•
Interleaved Average Current-Mode PWM
Control with Inherent Current Matching
Advanced Current Synthesizer Current
Sensing for Superior Efficiency and PF
Highly-Linear Multiplier Output with Internal
Quantized Voltage Feed-Forward Correction
for Near-Unity PF
Programmable Frequency (up to 300 kHz)
Programmable Maximum Duty-Cycle Clamp
Programmable Frequency Dithering Rate and
Magnitude for Enhanced EMI Reduction
– Magnitude: Up to 30 kHz
– Rate: Up to 30 kHz
External Clock Synchronization Capability
Enhanced Load and Line Transient Response
through Voltage Amplifier Output Slew-Rate
Correction
Programmable Peak Current Limiting
Bias-Supply UVLO, Over-Voltage Protection,
Open-Loop Detection, and PFC-Enable
Monitoring
External PFC-Disable Interface
Open-Circuit Protection on VSENSE and
VINAC pins
Programmable Soft Start
20-Lead TSSOP Package
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
ORDERING INFORMATION
PART NUMBER
PACKAGE
PACKING
UCC28070PW
Plastic, 20-Pin TSSOP (PW)
70-Pc. Tube
UCC28070PWR
Plastic, 20-Pin TSSOP (PW)
2000-Pc. Tape and Reel
ABSOLUTE MAXIMUM RATINGS (1) (2) (3) (4)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
LIMIT
UNIT
Supply voltage: VCC
22
V
Supply current: IVCC
20
mA
Voltage: GDA, GDB
−0.5 to VCC+0.3
V
Gate drive current – continuous: GDA, GDB
+/− 0.25
Gate drive current – pulsed: GDA, GDB
+/− 0.75
Voltage: DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA, CSB,
CAOA, CAOB, PKLMT, VREF
−0.5 to +7
PRODUCT PREVIEW
Current: VREF, VAO, CAOA, CAOB, IMO
mA
10
Operating junction temperature, TJ
−40 to +125
Storage temperature, TSTG
−65 to +150
Lead temperature (10 seconds)
(2)
(3)
(4)
V
−0.5
Current: RT, DMAX, RDM, RSYNTH
(1)
A
°C
260
These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at
these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability.
All voltages are with respect to GND.
All currents are positive into the terminal, negative out of the terminal.
In normal use, terminals GDA and GDB are connected to an external gate driver and are internally limited in output current.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
RATING
Human Body Model (HBM)
2,000
Charged Device Model (CDM)
500
UNIT
V
DISSIPATION RATINGS
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
PACKAGE
125 °C/Watt
20-Pin TSSOP
(1)
(2)
(1)
and
(2)
TA = 25°C POWER
RATING
800 mW
TA = 85°C POWER RATING
(1)
320 mW
(1)
Thermal resistance is a strong function of board construction and layout. Air flow reduces thermal resistance. This number is only a
general guide.
Thermal resistance calculated with a low-K methodology.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VCC Input Voltage (from a low-impedance source)
MAX
VUVLO + 1 V
VREF Load Current
UNIT
21
V
2
mA
VINAC Input Voltage Range
0
3
IMO Voltage Range
0
3.3
PKLMT, CSA, & CSB Voltage Range
0
3.7
RSYNTH Resistance (RSYN)
15
750
RDM Resistance (RRDM)
30
330
2
Submit Documentation Feedback
V
kΩ
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range −40°C < TA < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 67.5
kΩ, RRDM = RSYN = 100 kΩ, RIMO = 16 kΩ, CCDR = 625 pF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Bias Supply
VCCSHUNT
VCC shunt voltage
(1)
21
23
25
V
VSENSE = 0 V
7
VCC current, enabled
VSENSE = 3 V (no switching)
8
TBD
100
µA
4
TBD
mA
10.2
10.6
VCC current, UVLO
VUVLO
IVCC = 10 mA
VCC current, disabled
VCC = 7 V
VCC = 9 V
UVLO turn-on threshold
Measured at VCC (rising)
UVLO hysteresis
Measured at VCC (falling)
VREF enable threshold
Measured at VCC (rising)
9.8
1
mA
V
TBD
8
TBD
Linear Regulator
VREF voltage, no load
IVREF = 0 mA
5.9
6
6.1
VREF voltage, full load
IVREF = −2 mA
5.8
6
6.1
VREF voltage, over line
11 V < VCC < 20 V, IREF = 0 mA
5.9
6
6.1
Enable threshold
Measured at VSENSE (rising)
0.65
0.75
0.85
V
VEN
Enable hysteresis
0.15
PRODUCT PREVIEW
PFC Enable
V
External PFC Disable
Disable threshold
Measured at SS (falling)
Hysteresis
VSENSE > 0.85 V
Output phase shift
Measured between GDA and GDB
Timing regulation voltages
Measured at DMAX, RT, & RDM
TBD
0.6
V
0.15
Oscillator
VDMAX,VRT,
and VRDM
fPWM
DMAX
fDM
fDR
ICDR
(1)
TBD
180
TBD Degree
3
V
RRT = 250 kΩ, RDMX = 225 kΩ,
VRDM = 0 V, VCDR = 6 V
27
30
33
RRT = 25 kΩ, RDMX = 22.5 kΩ,
VRDM = 0 V, VCDR = 6 V
270
300
330
Duty-cycle clamp
RRT = 75 kΩ, RDMX = 67.5 kΩ,
VRDM = 0 V, VCDR = 6 V
TBD%
95%
TBD%
Minimum programmable off-time
RRT = 25 kΩ, RDMX = 22.5 kΩ,
VRDM = 0 V, VCDR = 6 V
TBD
133
TBD
Frequency dithering magnitude
RRDM = 313 kΩ, RRT = 75 kΩ
2.5
3
3.5
Change in fPWM
RRDM = 31 kΩ, RRT = 25 kΩ
27
30
33
Frequency dithering rate
CCDR = 2.2 nF, RRDM = 100 kΩ
3
Rate of change in fPWM
CCDR = 0.22 nF, RRDM = 100 kΩ
30
Dither rate current
Measure at CDR (sink and source)
10
Dither disable threshold
Measured at CCDR (rising)
PWM switching frequency
kHz
5
ns
kHz
µA
TBD
V
Excessive VCC input voltage and/or current damages the device. This clamp will not protect the device from an unregulated supply. If
an unregulated supply is used, a series-connected fixed positive voltage regulator such as a UA78L15A is recommended. See the
Absolute Maximum Ratings section for the limits on VCC voltage and current.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
3
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range −40°C < TA < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 67.5
kΩ, RRDM = RSYN = 100 kΩ, RIMO = 16 kΩ, CCDR = 625 pF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Clock Synchronization
VCDR
SYNC enable threshold
Measured at CDR (rising)
SYNC propagation delay
VCDR = 6 V, Measured from RDM (rising) to
GDx (rising)
SYNC threshold (Rising)
VCDR = 6 V, Measured at RDM (rising)
SYNC threshold (Falling)
VCDR = 6 V, Measured at RDM (falling)
0.4
Positive pulse width
0.2
SYNC pulses
Maximum duty cycle
(2)
5
TBD
V
50
TBD
ns
1.2
1.5
0.7
V
µs
75
%
Voltage Amplifier
PRODUCT PREVIEW
gMV
ISRC
VSENSE voltage
In regulation, TA = 25°C
2.97
3
3.03
VSENSE voltage
In regulation
2.94
3
3.06
VSENSE input bias current
In regulation
250
TBD
VAO high voltage
VSENSE = 2.9 V
5
5.2
VAO low voltage
VSENSE = 3.1 V
0.05
TBD
VAO transconductance
2.8 V < VSENSE < 3.2 V, VAO = 3 V
70
VAO sink current, overdriven limit
VSENSE = 3.5 V, VAO = 3 V
30
VAO source current, overdriven
VSENSE = 2.5 V, VAO = 3 V, SS = 3 V
VAO source current,
overdriven limit + ISRC
VSENSE = 2.5 V, VAO = 3 V
Slew-rate correction threshold
Measured as VSENSE (falling) / VSENSE
(regulation)
Slew-rate correction hysteresis
Measured at VSENSE (rising)
Slew-rate correction current
Measured at VAO, in addition to VAO
source current.
Slew-rate correction enable threshold
Measured at SS (rising)
VAO discharge current
VSENSE = 0.5 V, VAO = 1 V
SS source current
4.8
V
nA
V
µS
−30
µA
−130
92
93
95
6
TBD
%
mV
−100
µA
4
V
10
µA
VSENSE = 0.9 V, SS = 1 V
−10
µA
Adaptive source current
VSENSE = 1.1 V, SS = 1 V
−1
mA
Adaptive SS disable
Measured as VSENSE – SS
0
mV
SS sink current
VSENSE = 0.5 V, SS = 0.2 V
0.9
mA
Soft Start
ISS
(2)
4
0.5
Due to the programmability of the maximum PWM switching duty cycle (DMAX), the maximum duty cycle of a synchronization pulse must
be reasonably (~5-10%) less than 2 x DMAX -1.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range −40°C < TA < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 67.5
kΩ, RRDM = RSYN = 100 kΩ, RIMO = 16 kΩ, CCDR = 625 pF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Over Voltage
VOVP
OVP threshold
Measured as VSENSE (rising) / VSENSE
(regulation)
OVP hysteresis
Measured at VSENSE (falling)
OVP propagation delay
Measured between VSENSE (rising) and
GDx (falling)
Zero-power detect threshold
Measured at VAO (falling)
104
106
108
100
TBD
%
mV
0.5
µs
Zero-Power
VZPWR
TBD
Zero-power hysteresis
0.75
V
0.15
Multiplier
kMULT
Gain constant
IIMO
Output current: zero
VAO > 1.5 V
16
17
18
VAO = 1.2 V
15
17
19
VINAC = 0.9 VPK, VAO = 0.8 V
-0.2
0
0.2
VINAC = 0 V, VAO = 5 V
-0.2
0
0.2
0.6
0.7
0.8
µA
µA
(3)
VLVL1
Level 1 threshold
VLVL2
Level 2 threshold
1
VLVL3
Level 3 threshold
1.2
VLVL4
Level 4 threshold
VLVL5
Level 5 threshold
VLVL6
Level 6 threshold
1.95
VLVL7
Level 7 threshold
2.25
VLVL8
Level 8 threshold
2.6
1.4
Measured at VINAC (rising)
PRODUCT PREVIEW
Quantized Voltage Feed Forward
V
1.65
Current Amplifiers
CAOx high voltage
TBD
CAOx low voltage
gMC
TBD
CAOx transconductance
0.1
50
µA
−50
CAOx source current, overdriven
Input common mode range
0
Input offset voltage
IMO = 0 V
Phase mismatch
Measured as Phase A’s input offset minus
Phase B’s input offset
CAOx pull-down current
VSENSE = 0.5 V, CAOx = 0.2 V
V
µS
100
CAOx sink current, overdriven
(3)
6
3.6
−1
−3
−5
TBD
0
TBD
0.5
0.9
V
mV
mA
The Level 1 threshold represents the “zero-crossing detection” threshold above which VINAC must rise to initiate a new input half-cycle,
and below which VINAC must fall to terminate that half-cycle.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
5
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range −40°C < TA < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 75 kΩ, RDMX = 67.5
kΩ, RRDM = RSYN = 100 kΩ, RIMO = 16 kΩ, CCDR = 625 pF, CSS = CVREF = 0.1 µF, CVCC = 1 µF, (unless otherwise noted)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Synthesizer
VRSYNTH
VSENSE = 3 V, VINAC = 0 V
Regulation voltage
3
VSENSE = 3 V, VINAC = 2.85 V
Synthesizer disable threshold
0.15
Measured at RSYNTH (rising)
VINAC input bias current
V
5
TBD
250
TBD
nA
3.3
3.33
V
TBD
100
ns
Peak Current Limit
Peak current limit threshold
PKLMT = 3.30 V, measured at CSx (rising)
Peak current limit propagation delay
Measured between CSx (rising) and GDx
(falling) edges
3.27
PWM Ramp
VRMP
PWM ramp amplitude
4
PWM ramp offset voltage
TA = 25°C, RRT = 75 kΩ
TBD
PWM ramp offset temperature
coefficient
0.7
TBD
V
mV/ °C
−2
PRODUCT PREVIEW
In-Rush Current Detection
In-rush detection threshold
Measured as VSENSE - VINAC
0
In-rush detection hyst.
mV
20
Gate Drive
GDA, GDB output voltage, high,
clamped
VCC = 20 V, CLOAD = 1 nF
GDA, GDB output voltage, High
CLOAD = 1 nF
GDA, GDB output voltage, Low
Rise time GDx
11.5
13
15
10
10.5
11.5
CLOAD = 1 nF
0.2
0.3
1 V to 9 V, CLOAD = 1 nF
18
30
Fall time GDx
9 V to 1 V, CLOAD = 1 nF
12
25
GDA, GDB output voltage, UVLO
VCC = 0 V, IGDA, IGDB = 2.5 mA
1.6
2
V
ns
V
Thermal Shutdown
Thermal shutdown threshold
160
Thermal shutdown recovery
140
°C
DEVICE INFORMATION
TSSOP-20 Top View, PW Package
6
CDR
1
20
DMAX
RDM
2
19
RT
VAO
3
18
SS
VSENSE
4
17
GDB
VINAC
5
16
GND
IMO
6
15
VCC
RSYNTH
7
14
GDA
CSB
8
13
VREF
CSA
9
12
CAOA
PKLMT
10
11
CAOB
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
TERMINAL FUNCTIONS
PIN #
I/O
DESCRIPTION
CDR
1
I
Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs
the rate of oscillator dither. Connect the CDR pin to the VREF pin to disable dithering.
RDM
(SYNC)
2
I
Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An
external resistor to GND programs the magnitude of oscillator frequency dither. When frequency
dithering is disabled (CDR > 5 V), the internal master clock will synchronize to positive edges
presented on the RDM pin. Connect RDM to GND when dithering is disabled and synchronization
is not desired.
VAO
3
O
Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally
connected to Multiplier input and Zero-Power comparator. Connect the voltage regulation loop
compensation components between this pin and GND.
VSENSE
4
I
Output Voltage Sense. Internally connected to the inverting input of the transconductance
voltage error amplifier in addition to the positive terminal of the Current Synthesis difference
amplifier. Also connected to the OVP, PFC Enable, and slew-rate comparators. Connect to PFC
output with a resistor-divider network.
VINAC
5
I
Scaled AC Line Input Voltage. Internally connected to the Multiplier and negative terminal of the
Current Synthesis difference amplifier. Connect a resistor-divider network between VIN, VINAC,
and GND identical to the PFC output divider network connected at VSENSE.
IMO
6
O
Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier
gain.
RSYNTH
7
I
Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to
set the magnitude of the current synthesizer down-slope.
CSB
8
I
Phase B Current Sense Input. During the on-time of GDB, CSB is internally connected to the
inverting input of Phase B’s current amplifier.
CSA
9
I
Phase A Current Sense Input. During the on-time of GDA, CSA is internally connected to the
inverting input of Phase A’s current amplifier.
PKLMT
10
I
Peak Current Limit Programming. Connect a resistor-divider network between VREF and this
pin to set the voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows
adjustment for desired ΔILB.
CAOB
11
O
Phase B Current Amplifier Output. Output of phase B’s transconductance current amplifier.
Internally connected to the inverting input of phase B’s PWM comparator for trailing-edge
modulation. Connect the current regulation loop compensation components between this pin and
GND.
CAOA
12
O
Phase A Current Amplifier Output. Output of phase A’s transconductance current amplifier.
Internally connected to the inverting input of phase A’s PWM comparator for trailing-edge
modulation. Connect the current regulation loop compensation components between this pin and
GND.
VREF
13
O
6-V Reference Voltage and Internal Bias Voltage. Connect a 0.1-µF ceramic bypass capacitor
as close as possible to this pin and GND.
GDA
14
O
Phase A’s Gate Drive. This limited-current output is intended to connect to a separate gate-drive
device suitable for driving the Phase A switching component(s). The output voltage is typically
clamped to 13.5 V.
VCC
15
I
Bias Voltage Input. Connect a 0.1-µF ceramic bypass capacitor as close as possible to this pin
and GND.
GND
16
I/O
Device Ground Reference. Connect all compensation and programming resistor and capacitor
networks to this pin. Connect this pin to the system through a separate trace for high-current
noise isolation.
GDB
17
O
Phase B’s Gate Drive. This limited-current output is intended to connect to a separate
gate-drivedevice suitable for driving the Phase B switching component(s). The output voltage is
typically clamped to 13.5 V.
SS
18
I
Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the
soft-start slew rate based on an internally-fixed 10-µA current source. The regulation reference
voltage for VSENSE is clamped to VSS until VSS exceeds 3 V. Upon recovery from certain fault
conditions a 1-mA current source is present at the SS pin until the SS voltage equals the
VSENSE voltage. Pulling the SS pin below 0.6 V immediately disables both GDA and GDB
outputs.
RT
19
I
Timing Resistor. Oscillator frequency programming pin. A resistor to GND sets the running
frequency of the internal oscillator.
DMAX
20
I
Maximum Duty-Cycle Resistor. Maximum PWM duty-cycle programming pin. A resistor to GND
sets the PWM maximum duty-cycle based on the ratio of RDMX/RRT.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
7
PRODUCT PREVIEW
NAME
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Functional Block Diagram
+
In-Rush
VCC 15
VINAC
20mV Hys.
Fault
20mV
23V
VREF 13 6V
+
Linear
EN
Regulator
160 On
140 Off
o
0.75V
0.60V
+
C
S
VSENSE
Q
OVP
+
ZeroPwr
+
0.75V
0.60V
SS
VSENSE
+
+
3.18V
3.08V
8V
GND 16
Ext. Disable
ReStart
ThermSD
R
Q
UVLO
0.90V
0.75V
10.2V
9.2V
VAO
6
IMO
5 VINAC
DMAX 20
Voltage
FeedForward
CLKA
RT
Oscillator w/
Freq. Dither
19
CLKB
IIMO =
VVINAC * (VVAO – 1)
* 17uA
KVFF
KVFF
OffA
250nA
x
OffB
Mult.
/
3 VAO
x
PRODUCT PREVIEW
RDM/
SYNC
+
ReStart
SYNC
Logic
2
100uA
5V
CDR
1
+
SYNC
Enable
Dither
Disable
SS
4V
Slew Rate
Correction
+
10uA
2.8V
5V
Gm Amp
VA
4
+
+
3V
VSENSE
250nA
Adaptive SS
PKLMT 10
IpeakA
+
1mA
ReStart
ISS
10uA
+
Control
Logic
ReStart
Ext. Disable
IpeakB
CSA 9
+
+
18 SS
PWM1
CA1
Gm Amp
+
S
Q
R
Q
VCC
(Clamped at 13.5V)
OutA
CSB 8
OffA
IpeakA
OutB
Current
Synthesizer
RSYNTH 7
Fault
+
Disable
+
5V
CAOA 12
CLKA
VINAC
VSENSE
14 GDA
GND
PWM2
CA2
Gm Amp
Driver
VCC
+
OffB
IpeakB
Fault
CLKB
S
Q
R
Q
(Clamped at 13.5V)
Driver
17 GDB
GND
CAOB 11
8
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
APPLICATION INFORMATION
THEORY OF OPERATION
Natural Interleaving
One of the main benefits from the natural interleaving of phases is significant reductions in the high-frequency
ripple components of both the input current and the current into the output capacitor of the PFC pre-regulator.
Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the
burden of filtering conducted-EMI noise and helps reduce the EMI filter and CIN sizes. Additionally, reduced
high-frequency ripple current into the PFC output capacitor, COUT, helps to reduce its size and cost. Furthermore,
with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a
single-phase design [1].
On the input, natural interleaving reduces the peak-to-peak ripple amplitude to 1/2 or less of the ripple amplitude
of the equivalent single-phase current.
On the output, Natural Interleaving reduces the rms value of the PFC-generated ripple current in the output
capacitor by a factor of slightly more than √2, for PWM duty-cycles > 50% as derived from following Erickson’s
method [2].
Programming the PWM Frequency and Maximum Duty-Cycle Clamp
The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through
the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor
(RRT) directly sets the PWM frequency (fPWM).
RRT (k W ) =
7500
f PWM (kHz )
Once RRT has been determined, the DMAX resistor (RDMX) may be derived.
RDMX = RRT ´ (2 ´ DMAX - 1)
where DMAX is the desired maximum PWM duty-cycle.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
9
PRODUCT PREVIEW
Ripple current reduction due to interleaving is often referred to as “ripple cancellation”, but strictly speaking, the
peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other
than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual
phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC pre-regulator,
those of a 2-phase naturally-interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation,
the frequency of the naturally-interleaved ripple, at both the input and output, is 2 x fPWM.
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Frequency Dithering (Magnitude and Rate)
Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise
beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which
results in equal time spent at every point along the switching frequency range. This total range from minimum to
maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency
fPWM set with RRT. For example, a dither magnitude of 20 kHz on a nominal fPWM of 100 kHz results in a
frequency range of 100 kHz ±10 kHz. Furthermore, the programmed duty-cycle clamp set by RDMX remains
constant at the programmed value across the entire range of the frequency dithering.
The rate at which fPWM traverses from one extreme to the other and back again is defined as the dither rate. For
example, a dither rate of 1 kHz would linearly modulate the nominal frequency from 110 kHz to 90 kHz to 110
kHz once every millisecond. A good initial design target for dither magnitude is ±10% of fPWM. Most boost
components can tolerate such a spread in fPWM. The designer can then iterate around there to find the best
compromise between EMI reduction, component tolerances, and loop stability.
The desired dither magnitude is set by a resistor from the RDM pin to GND, of value calculated by the following
equation:
RRDM (k W ) =
937.5
f DM (kHz )
PRODUCT PREVIEW
Once the value of RRDM is determined, the desired dither rate may be set by a capacitor from the CDR pin to
GND, of value calculated by the following equation:
æR
ö
CCDR ( pF ) = 66.7 ´ ç RDM ÷ (k W / kHz )
è f DR ø
Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and
connecting the RDM pin directly to GND. (If populated, the relatively high impedance of the RDM resistor may
allow system switching noise to couple in and interfere with the controller timing functions if not bypassed with a
low impedance path when dithering is disabled.)
If an external frequency source is used to synchronize fPWM and frequency dithering is desired, the external
frequency source must provide the dither magnitude and rate functions as the internal dither circuitry is disabled
to prevent undesired performance during synchronization. (See SubSec2 0.1 section for more details.)
10
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
External Clock Synchronization
The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By
disabling frequency dithering (pulling CDR > 5 V), the UCC28070’s SYNC circuitry is enabled permitting the
internal oscillator to be synchronized with pulses presented on the RDM pin. In order to ensure a precise 180
degree phase shift is maintained between the GDA and GDB outputs, the frequency (fSYNC) of the pulses
presented at the RDM pin needs to be at twice the desired fPWM. For example, if a 100-kHz switching frequency
is desired, the fSYNC should be 200 kHz.
In order to ensure the internal oscillator does not interfere with the SYNC function, RRT should be sized to set the
internal oscillator frequency at least 10% below the fSYNC. It must be noted that the PWM modulator gain will be
reduced by a factor equivalent to the scaled RRT due to a direct correlation between the PWM ramp current and
RRT. Adjustments to the current loops should be made accordingly.
The maximum duty-cycle clamp programmability is still maintained via the selection of RDMX based on the second
and third equations below.
f SYNC
2
R' RT (k W ) =
15000
f SYNC (kHz )
PRODUCT PREVIEW
f PWM =
R DMX (k W ) = R ' RT ´ (2 ´ D MAX - 1)
RRT (k W ) = 1.1´
15000
f SYNC (kHz )
f SYN (max D ) £ 0.9 ´ (2 ´ DMAX - 1)
NOTE:
When external synchronization is used, a propagation delay of approximately 50 ns to
100 ns exists between internal timing circuits and the SYNC signal’s rising edge,
which may result in reduced off-time at the highest of switching frequencies.
Therefore, RDMX should be adjusted downward slightly by (TSYNC-0.1 µs)/TSYNC to
compensate. At lower SYNC frequencies, this delay becomes an insignificant fraction
of the PWM period, and can be neglected.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
11
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Multi-phase Operation
External synchronization also facilitates using more than 2 phases for interleaving. Multiple UCC28070s can
easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate
phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be
obtained. (An odd number of phases can be accommodated if desired, but the ripple cancellation would not be
optimal.) For 4-, 6-, or any 2 x n-phases (where n = the number of UCC28070 controllers), each controller should
receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application
interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation.
Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for
optimal ripple cancellation.
In a multi-phase interleaved system, each current loop is independent and treated separately, however there is
only one common voltage loop. To maintain a single control loop, all VSENSE, VINAC, SS, IMO and VAO
signals are paralleled, respectively between the n controllers. Where current-source outputs are combined (SS,
IMO, VAO), the calculated load impedances must be adjusted by 1/n to maintain the same performance as with
a single controller.
Figure 20 illustrates the paralleling of two controllers for a 4-phase 90°-interleaved PFC system.
VSENSE and VINAC Resistor Configuration
PRODUCT PREVIEW
The primary purpose of the VSENSE input is to provide the voltage feedback from the output to the voltage
control loop. Thus, a traditional resistor-divider network needs to be sized and connected between the output
capacitor and the VSENSE pin to set the desired output voltage based on the 3-V regulation voltage on
VSENSE.
A unique aspect of the UCC28070 is the need to place the same resistor-divider network on the VIN side of the
inductor to the VINAC pin. This provides the scaled input voltage monitoring needed for the linear multiplier and
current synthesizer circuitry. It is not required that the actual resistance of the VINAC network be identical to the
VSENSE network, but it is necessary that the attenuation (kR) of the two divider networks be equivalent for
proper PFC operation.
kR =
RB
(RA + RB )
In noisy environments, it may be beneficial for small filter capacitors to be applied to the VSENSE and VINAC
inputs to avoid the destabilizing effects of excessive noise on these inputs. If applied, the RC time-constant
should not exceed 100µs on the VSENSE input to avoid significant delay in the output transient response. The
RC time-constant should also not exceed 100 µs on the VINAC input to avoid degrading of the wave-shape
zero-crossings. Usually, a time constant of 3/fPWM is adequate to filter out typical noise on VSENSE and VINAC.
Some design and test iteration may be required to find the optimal amount of filtering required in a particular
application.
VSENSE and VINAC Open Circuit Protection
Both the VSENSE and VINAC pins have been designed with an internal 250-nA current sink to ensure that in the
event of an open circuit at either pin, the voltage is not left undefined, and the UCC28070 remains in a “safe”
operating mode.
12
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
V IN
L1
D1
–
+
To CSB1
VREF1
RDMX1
1 CDR
DMAX 20
2 RDM
RT 19
3 VAO
SS 18
T1
RS1
RRT1
RA
4 VSENSE
GDB 17
5 VINAC
GND 16
6 IMO
VCC 15
7 RSYNTH
GDA 14
M1
12V to 21V
RB
CSB1
8 CSB
VREF 13
9 CSA
CAOA 12
L2
VREF1
D2
From Ixfrms
CSA1
To CSA1
10 PKLMT
CAOB 11
T2
RSYN1
RS 2
CZC
RPK1
CREF
RIMO
CPV
CZC
CPC
RPK2
CPC
CSS
RZV
RZC
RZC
VOUT
RZC
RZC
RA
COUT
CPC
CPC
RB
CREF
CZC
CZC
Vin
L3
D3
RSYN2
To CSA2
10 PKLMT
T3
RS 3
CAOB 11
CSB2
9 CSA
CAOA 12
8 CSB
VREF 13
From Ixfrms
VREF2
CSA2
M3
7 RSYNTH
GDA 14
6 IMO
VCC 15
5 VINAC
GND 16
4 VSENSE
GDB 17
3 VAO
SS 18
2 RDM
RT 19
1 CDR
DMAX 20
12V to 21V
L4
D4
RRT2
To CSB2
RDMX2
Synchronized
Clocks
w/ 180 o
Phase Shift
RS 4
T4
M4
Figure 20. Functional Four-Phase Application Schematic Using Two UCC28070
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
13
PRODUCT PREVIEW
M2
CZV
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Current Synthesizer
One of the most prominent innovations in the UCC28070 design is the current synthesizer circuitry that
synchronously monitors the instantaneous inductor current through a combination of on-time sampling and
off-time down-slope emulation.
During the on-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins
respectively via the current transformer network in each output phase. Meanwhile, the continuous monitoring of
the input and output voltage via the VINAC and VSENSE pins permits the UCC28070 to internally recreate the
inductor current’s down-slope during each output’s respective off-time. Through the selection of the RSYNTH
resistor (RSYN), based on the equation below, the internal circuitry may be adjusted to accommodate the wide
range of inductances expected across the wide array of applications.
Waveform at
CSx input
Synthesized
down-slope
PRODUCT PREVIEW
Current Synthesizer
output to CA
Figure 21. Inductor Current’s Down Slope
RSYN (k W ) =
(10 ´ N
CT
´ LB (m H )´ k R )
RS (W )
Variables
• LB = Nominal Boost Inductance (µH),
• RS = Sense Resistor (Ω),
• NCT = Current-sense Transformer turns ratio,
• kR = RB/(RA+RB) = the resistor-divider attenuation at the VSENSE and VINAC pins.
14
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Programmable Peak Current Limit
The UCC28070 has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling
either GDA or GDB output whenever the corresponding current-sense input (CSA or CSB respectively) rises
above the voltage established on the PKLMT pin. Once an output has been disabled via the detection of peak
current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming
range of the PKLMT voltage extends to upwards of 4 V to permit the full utilization of the 3-V average current
sense signal range.
A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT,
provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. A load of
less than 0.5 mA is suggested, but if the resistance on PKLMT is very high, a small filter capacitor on PKLMT is
recommended to avoid operational problems in high-noise environments.
PKLMT
Externally Programmable Peak
Current Limit level (PKLMT)
10
IPEAKx
+
To Gate-Drive
Shut-down
CSx
To Current
Amplifier
PRODUCT PREVIEW
Current
Synthesizer
DI
3V Average Current-sense
Signal Range, plus Ripple
Figure 22. Externally Programmable Peak Current Limit
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
15
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Linear Multiplier
The multiplier of the UCC28070 generates a reference current which represents the desired wave shape and
proportional amplitude of the ac input current. This current is converted to a reference voltage signal by the RIMO
resistor, which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier
current is dependent upon the rectified, scaled input voltage VVINAC and the voltage-error amplifier output VVAO.
The VVINAC signal conveys three pieces of information to the multiplier:
1. The overall wave-shape of the input voltage (typically sinusoidal),
2. the instantaneous input voltage magnitude at any point in the line cycle,
3. and the rms level of the input voltage.
The VVAO signal represents the total output power of the PFC pre-regulator.
A major innovation in the UCC28070 multiplier architecture is the internal quantized VRMS feed-forward (QVFF)
circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow
response to transient line variations. A unique circuit algorithm detects the transition of the peak of VVINAC
through seven thresholds and generates an equivalent VFF level centered within the eight QVFF ranges. The
boundaries of the ranges expand with increasing VIN to maintain an approximately equal-percentage delta
between levels. These eight QVFF levels are spaced to accommodate the full “universal” line range of 85 V-265
VRMS.
PRODUCT PREVIEW
A great benefit of the QVFF architecture is that the fixed kVFF factors eliminate any contribution to distortion of the
multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion
components. Furthermore, the QVFF algorithm allows for rapid response to both increasing and decreasing
changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in
the level thresholds help avoid “chattering” between QVFF levels for VVINAC voltage peaks near a particular
threshold or containing mild ringing or distortion. The QVFF architecture requires that the input voltage be largely
sinusoidal, and relies on detecting zero-crossings to adjust QVFF downward on decreasing input voltage.
Zero-crossings are defined as VVINAC falling below 0.7 V for at least 50 µs typically.
Table 1 reflects the relationship between the various VINAC peak voltages and the corresponding kVFF terms for
the multiplier equation.
Table 1. VINAC Peak Voltages
VVINAC PEAK VOLTAGE
kVFF (V2)
8
2.60 V ≤ VVINAC(pk)
3.857
> 345 V
7
2.25 V ≤ VVINAC(pk) < 2.60 V
2.922
300 V to 345 V
6
1.95 V ≤ VVINAC(pk) < 2.25 V
2.199
260 V to 300 V
5
1.65 V ≤ VVINAC(pk) < 1.95 V
1.604
220 V to 260 V
4
1.40 V ≤ VVINAC(pk) < 1.65 V
1.156
187 V to 220 V
3
1.20 V ≤ VVINAC(pk) < 1.40 V
0.839
160 V to 187 V
2
1.00 V ≤ VVINAC(pk) < 1.20 V
0.600
133 V to 160 V
1
VVINAC(pk) ≤ 1.00 V
0.398
< 133 V
LEVEL
(1)
16
VIN PEAK VOLTAGE
(1)
The VIN peak voltage boundary values listed above are calculated based on a 400-V PFC output voltage and the use of a matched
resistor-divider network (kR = 3 V/400 V = 0.0075) on VINAC and VSENSE (as required for current synthesis). When VOUT is designed
to be higher or lower than 400 V, kR = 3 V/VOUT, and the VIN peak voltage boundary values for each QVFF level adjust to VVINAC(pk)/kR.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
The multiplier output current IIMO for any line and load condition can thus be determined by the equation
I IMO =
17 m A ´ (VVINAC )´ (VVAO - 1)
kVFF
Because the kVFF value represents the scaled VRMS2 at the center of a level, VVAO will adjust slightly upwards or
downwards when VINACpk is either lower or higher than the center of the QVFF voltage range to compensate for
the difference. This is automatically accomplished by the voltage loop control when VIN varies, both within a level
and after a transition between levels.
The output of the voltage-error amplifier VAO is clamped at 5.0 V, which represents the maximum PFC output
power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the
maximum input power allowed (and, as a consequence, limits maximum output power).
Unlike a continuous VFF situation, where maximum input power is a fixed power at any VRMS input, the discrete
QVFF levels permit a variation in maximum input power within limited boundaries as the input VRMS varies within
each level.
For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average)
output power required of the PFC pre-regulator and add some additional percentage to account for line drop-out
recovery power (to recharge COUT while full load power is drawn) such as 10% or 20% of POUT(max). Then apply
the expected efficiency factor to find the lowest maximum input power allowable:
PIN (max) =
1.10 ´ POUT (max)
h
At the PIN(max) design threshold, VVINAC = 0.76 V, hence QVFF = 0.398 and input VAC = 73 VRMS (accounting for
2-V bridge-rectifier drop) for a nominal 400-V output system.
Thus I IN ( rms ) =
PIN (max)
73VRMS
, and I IN ( pk ) = 1.414 ´ I IN ( rms )
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
17
PRODUCT PREVIEW
The lowest maximum power limit occurs at the VINAC voltage of 0.76 V, while the highest maximum power limit
occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold,
keeping in mind that decreasing thresholds are 95% of the increasing threshold values. Below VINAC = 0.76 V,
PIN is always less than PIN(max), falling linearly to zero with decreasing input voltage.
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
This IIN(pk) value represents the combined average current through the boost inductors at the peak of the line
voltage. Each inductor current is detected and scaled by a current-sense transformer (CT). Assuming equal
currents through each interleaved phase, the signal voltage at each current sense input pin (CSA and CSB) is
developed across a sense resistor selected to generate ~3 V based on (1/2) x IIN(pk) x RS/NCT, where RS is the
burden current sense resistor and NCT is the CT turns-ratio.
IIMO is then calculated at that same lowest maximum-power point, as
I IMO(max) = 17 m A ´
(0.76V )(5V - 1V ) = 130m A
0.398
RIMO is selected such that:
R
æ1ö
RIMO ´ I IMO(max) = ç ÷ ´ I IN ( pk ) ´ S
N CT
è2ø
Therefore:
PRODUCT PREVIEW
RIMO
ææ 1 ö
ö
ç ç 2 ÷ ´ I IN ( pk ) ´ RS ÷
è ø
ø
=è
(NCT ´ I IMO(max) )
At the increasing side of the level-1 to level-2 threshold, it should be noted that the IMO current would allow
much higher input currents at low-line:
I IMO( L1- L 2 ) = 17 m A ´
(1.0V )(5V - 1V ) = 171m A
0.398
However, this current may easily be limited by the programmable peak current limiting (PKLMT) feature of the
UCC28070 if required by the power stage design.
The same procedure can be used to find the lowest and highest input power limits at each of the QVFF level
transition thresholds. At higher line voltages, where the average current with inductor ripple is traditionally below
the PKLMT threshold, the full variation of maximum input power will be seen, but the input currents will inherently
be below the maximum acceptable current levels of the power stage.
The performance of the multiplier in the UCC28070 has been significantly enhanced when compared to previous
generation PFC controllers, with high linearity and accuracy over most of the input ranges. The accuracy is at its
worst as VVAO approaches 1 V because the error of the (VVAO-1) subtraction increases and begins to distort the
IMO reference current to a greater degree.
Enhanced Transient Response (VA Slew-Rate Correction)
Due to the low voltage loop bandwidth required to maintain proper PFC and ignore the slight 120-Hz ripple on
the output, the response of ordinary controllers to input voltage and load transients will also be slow. However,
the QVFF function effectively handles the line transient response with the exception of any minor adjustments
needed within a QVFF level. Load transients on the other hand can only be handled by the voltage loop, therefore,
the UCC28070 has been designed to improve its transient response by pulling up on the output of the voltage
amplifier (VAO) with an additional 100 µA of current in the event the VSENSE voltage drops below 93% of
regulation (2.79 V). During a soft-start cycle, when VSENSE is ramping up from the 0.75-V PFC Enable
threshold, the 100-µA correction current source is disabled to ensure the gradual and controlled ramping of
output voltage and current during a soft start.
18
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Voltage Biasing (VCC and VREF)
The UCC28070 operates within a VCC bias supply range of 10 V to 21 V. An Under-Voltage Lock-Out (UVLO)
threshold prevents the PFC from activating until VCC > 10.2 V, and 1 V of hysteresis assures reliable start-up
from a possibly low-compliance bias source. An internal 23-V zener-like clamp on VCC is intended only to protect
the device from brief energy-limited surges from the bias supply, and should NOT be used as a regulator with a
current-limited source.
At minimum, a 0.1-µF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to
provide local filtering of the bias supply. Larger values may be required depending on ICC peak current
magnitudes and durations to minimize ripple voltage on VCC.
In order to provide a smooth transition out of UVLO and to make the 6-V voltage reference available as early as
possible, the VREF output is enabled when VCC exceeds 8 V typically.
The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally.
At minimum, a 22-nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to
ensure stability of the circuit. External load current on VREF should be limited to less than 2 mA, or degraded
regulation may result.
The UCC28070 contains two independent circuits dedicated to disabling the GDx outputs based on the biasing
conditions of the VSENSE or SS pins. The first circuit which monitors the VVSENSE, is the traditional PFC Enable
that holds off soft-start and the overall PFC function until the output has pre-charged to ~25%. Prior to VVSENSE
reaching 0.75 V, almost all of the internal circuitry is disabled. Once VVSENSE reaches 0.75 V and VAO < 0.75 V,
the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage
on the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable
the GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6
V, the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present,
normal PWM operation resumes when the external SS pull-down is released. It must be noted that the external
pull-down needs to be sized large enough to override the internal 1-mA adaptive SS pull-up once the SS voltage
falls below the disable threshold. It is recommended that a MOSFET with less than 100-Ω RDS(on) resistance be
used to ensure the SS pin is held adequately below the disable threshold.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
19
PRODUCT PREVIEW
PFC Enable and Disable
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Adaptive Soft Start
In order to maintain a controlled power up, the UCC28070 has been designed with an adaptive soft-start function
that overrides the internal reference voltage with a controlled voltage ramp during power up. On initial power up,
once VVSENSE exceeds the 0.75-V enable threshold (VEN), the internal pull down on the SS pin is released, and
the 1-mA adaptive soft-start current source is activated. This 1-mA pull-up almost immediately pulls the SS pin to
0.75 V (VVSENSE) to bypass the initial 25% of dead time during a traditional 0 V to Vregulation SS ramp. Once the
SS pin has reached the voltage on VSENSE, the 10-µA soft-start current (ISS) takes over. Thus, through the
selection of the soft-start capacitor (CSS), the effective soft-start time (tSS) may be easily programmed based on
the equation below.
æ 2.25V ö
tSS = CSS ´ ç
÷
è 10 m A ø
Often, a system restart is desired following a brief shut-down. In such a case, VSENSE may still have substantial
voltage if VOUT has not fully discharged or if high line has peak charged COUT. To eliminate the delay caused by
charging CSS from 0 V up to the pre-charged VVSENSE with only the 10-µA current source and any further output
voltage sag, the adaptive soft start uses a 1-mA current source to rapidly charge CSS to VVSENSE, after which time
the 10-µA source controls the VSS accent to the desired soft-start ramp rate. In such a case, tSS is estimated as
follows:
PRODUCT PREVIEW
æ 3V - VVSENSE 0 ö
tSS = CSS ´ ç
÷
è 10 m A
ø
where VVSENSE0 is the voltage at VSENSE at the moment a soft start or restart is initiated.
(V)
VSS
VVSENSE
VSS if no adaptive current
Time (s)
PFC externally
disabled due to
AC-line drop-out
Reduced delay to regulation
AC-Line recovers
and SS pin released
Figure 23. Soft-Start Ramp Rate
20
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
PFC Start-Up Hold Off
An additional feature designed into the UCC28070 is the “Start-Up Hold Off” logic that prevents the device from
initiating a soft-start cycle until the VAO is below the zero-power threshold (0.75 V). This feature ensures that the
SS cycle will initiate from zero-power and zero duty-cycle while preventing the potential for any significant inrush
currents due to stored charge in the VAO compensation network.
Output Over-Voltage Protection (OVP)
Because of the high voltage output and a limited design margin on the output capacitor, output over-voltage
protection is essential for PFC circuits. The UCC28070 implements OVP through the continuous monitoring of
the VSENSE voltage. In the event VVSENSE rises above 106% of regulation (3.18 V), the GDx outputs are
immediately disabled to prevent the output voltage from reaching excessive levels. Meanwhile the CAOx outputs
are pulled low in order to ensure a controlled recovery starting from 0% duty-cycle after an OVP fault is released.
Once the VVSENSE voltage has dropped below 3.08 V, the PWM operation resumes normal operation.
Zero-Power Detection
Thermal Shutdown
In order to protect the power supplies from silicon failures at excessive temperatures, the UCC28070 has an
internal temperature-sensing comparator that shuts down nearly all of the internal circuitry, and disables the GDA
and GDB outputs, if the die temperature rises above 160°C. Once the die temperature falls below 140°C, the
device brings the outputs up through a typical soft start.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
21
PRODUCT PREVIEW
In order to prevent undesired performance under no-load and near no-load conditions, the UCC28070
zero-power detection comparator is designed to disable both GDA and GDB output in the event the VAO voltage
falls below 0.75 V. The 150 mV of hysteresis ensures that the output remains disabled until the VAO has nearly
risen back into the linear range of the multiplier (VAO ≥ 0.9 V).
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Advanced Design Techniques
Current Loop Feedback Configuration
(Sizing of the Current Transformer Turns Ratio and Sense Resistor (RS)
A current-sense transformer (CT) is typically used in high-power applications to sense inductor current while
avoiding significant losses in the sensing resistor. For average current-mode control, the entire inductor current
waveform is required; however low-frequency CTs are obviously impracticable. Normally, two high-frequency
CTs are used, one in the switching leg to obtain the up-slope current and one in the diode leg to obtain the
down-slope current. These two current signals are summed together to form the entire inductor current, but this
is not the case for the UCC28070.
A major advantage of the UCC28070 design is the current synthesis function, which internally recreates the
inductor current down-slope during the switching period off-time. This eliminates the need for the diode-leg CT in
each phase, significantly reducing space, cost and complexity. A single resistor programs the synthesizer down
slope, as previously discussed in SubSec2 0.2 .
A number of trade-offs must be made in the selection of the CT. Various internal and external factors influence
the size, cost, performance, and distortion contribution of the CT.
PRODUCT PREVIEW
These factors include, but are not limited to:
• Turns-ratio (NCT)
• Magnetizing inductance (LM)
• Leakage inductance (LLK)
• Volt-microsecond product (Vµs)
• Distributed capacitance (Cd)
• Series resistance (RSER)
• External diode drop (VD)
• External current sense resistor (RS)
• External reset network
Traditionally, the turns-ratio and the current sense resistor are selected first. Some iterations may be needed to
refine the selection once the other considerations are included.
22
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
In general, 50 ≤ NCT ≤ 200 is a reasonable range from which to choose. If NCT is too low, there may be high
power loss in RS and insufficient LM. If too high, there could be excessive LLK and Cd. (A one-turn primary
winding is assumed.)
LLK
IDS
1
NCT
LM
iM
CSx
RSER
D
Cd
Reset
Network
RS
A major contributor to distortion of the input current is the effect of magnetizing current on the CT output signal
(iRS). A higher turns-ratio results in a higher LM for a given core size. LM should be high enough that the
magnetizing current (iM) generated is a very small percentage of the total transformed current. This is an
impossible criterion to maintain over the entire current range, because iM unavoidably becomes a larger fraction
of iRS as the input current decreases toward zero. The effect of iM is to “steal” some of the signal current away
from RS, reducing the CSx voltage and effectively understating the actual current being sensed. At low currents,
this understatement can be significant and CAOx increases the current-loop duty-cycle in an attempt to correct
the CSx input(s) to match the IMO reference voltage. This unwanted correction results in overstated current on
the input wave shape in the regions where the CT understatement is significant, such as near the ac line zero
crossings. It can affect the entire waveform to some degree under the high line, light-load conditions.
The sense resistor RS is chosen, in conjunction with NCT, to establish the sense voltage at CSx to be about 3 V
at the center of the reflected inductor ripple current under maximum load. The goal is to maximize the average
signal within the common-mode input range VCMCAO of the CAOx current-error amplifiers, while leaving room for
the peaks of the ripple current within VCMCAO. The design condition should be at the lowest maximum input power
limit as determined in the Multiplier Section. If the inductor ripple current is so high as to cause VCSx to exceed
VCMCAO, then RS or NCT or both must be adjusted to reduce peak VCSx, which could reduce the average sense
voltage center below 3 V. There is nothing wrong with this situation; but be aware that the signal is more
compressed between full- and no-load, with potentially more distortion at light loads.
The matter of volt-second balancing is important, especially with the widely varying duty-cycles in the PFC stage.
Ideally, the CT is reset once each switching period; that is, the off-time Vµs product equals the on-time Vµs
product. (Because a switching period is usually measured in microseconds, it is convenient to convert the
volt-second product to volt-microseconds to avoid sub-decimal numbers.) On-time Vµs is the time-integral of the
voltage across LM generated by the series elements RSER, LLK, D, and RS. Off-time Vµs is the time-integral of the
voltage across the reset network during the off-time. With passive reset, Vµs-off is unlikely to exceed Vµs-on.
Sustained unbalance in the on or off Vµs products will lead to core saturation and a total loss of the
current-sense signal. Loss of VCSx causes VCAOx to quickly rise to its maximum, programming a maximum
duty-cycle at any line condition. This, in turn causes the boost inductor current to increase without control, until
the system fuse or some component failure interrupts the input current.
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
23
PRODUCT PREVIEW
Figure 28. Current Sense Transformer Equivalent Circuit
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
It is vital that the CT has plenty of Vµs design-margin to accommodate various special situations where there to
be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current
limiting.
Maximum Vµs(on) can be estimated by:
Vm (on )max = tON (max ) ´ (VRS + VD + VRSER + VLK )
where all factors are maximized to account for worst-case transient conditions and tON(max) occurs during the
lowest dither frequency when frequency dithering is enabled. For design margin, a CT rating of ~5*Vµs(on)max
or higher is suggested. The contribution of VRS varies directly with the line current. However, VD may have a
significant voltage even at near-zero current, so substantial Vµs(on) may accrue at the zero-crossings where the
duty-cycle is maximum. VRSER is the least contributor, and often can be neglected if RSER<<RS. VLK is developed
by the di/dt of the sensed current, and is not observable externally. However, its impact is considerable, given
the sub-microsecond rise-time of the current signal plus the slope of the inductor current. Fortunately, most of the
built-up Vµs across LM during the on-time is removed during the fall-time at the end of the duty-cycle, leaving a
lower net Vµs(on) to be reset during the off-time. Nevertheless, the CT must, at the very minimum, be capable of
sustaining the full internal Vµs(on)max built up until the moment of turn-off within a switching period.
Vµs(off) may be generated with a resistor or zener diode, using the iM as bias current.
PRODUCT PREVIEW
CRST
RRST
D
D
RRST
ZRST
Figure 29. Possible Reset Networks
In order to accommodate various CT circuit designs and prevent the potentially destructive result due to CT
saturation, the UCC28070’s maximum duty-cycle needs to be programmed such that the resulting minimum
off-time accomplishes the required worst-case reset. (See the PWM Frequency and Duty-Cycle Clamp section of
the data sheet for more information on sizing RDMX) Be aware that excessive Cd in the CT can interfere with
effective resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT
self-resonant frequency. A higher turns-ratio results in higher Cd [3], so a trade-off between NCT and DMAX must
be made.
The selected turns-ratio also affects LM and LLK, which vary proportionally to the square of the turns. Higher LM is
good, while higher LLK is not. If the voltage across LM during the on-time is assumed to be constant (which it is
not, but close enough to simplify) then the magnetizing current is an increasing ramp.
This upward ramping current subtracts from iRS, which affects VCSx especially heavily at the zero-crossings and
light loads, as stated earlier. With a reduced peak at VCSx, the current synthesizer starts the down-slope at a
lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these
conditions. If low input current distortion at very light loads is required, special mitigation methods may need to
be developed to accomplish that goal.
24
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
UCC28070
www.ti.com
SLUS794 – NOVEMBER 2007
Current-Sense Transformer (CT) Issue(s) When Operating In DCM
To maintain low THD over a wide range of line and load, AND keep a simple circuit, requires that Continuous
Conduction Mode (CCM) be maintained in the boost inductor over that same wide range. This requirement arises
out of the following situation:
The trend in PFC toward high-ripple, low-inductance design to reduce magnetics size and cost results in early
onset of discontinuous conduction mode (DCM) at high-line and/or lighter loads. Ordinarily, DCM can be
averaged as well as CCM, however a side-effect of DCM in conjunction with CT use leads to waveform distortion
in the following manner.
During the dead-time of DCM, when the boost inductor current has discharged to zero, the high voltage stored
on the MOSFET's COSS begins to ring back reverse current through the boost inductor and hence necessarily
backwards through the CT.
For a given power level and input voltage, an ideal current sinewave can be calculated. The regions of inductor
DCM have less actual current than the ideal sinewave requires, and so VAO voltage increases VIMO to inflate the
CCM portion to compensate for the difference. Hence a significant amount of distortion can result from a small
amount of DCM.
The simplest way to avoid this is to design the inductance high enough to avoid DCM under all conditions where
low THD is required. Otherwise, additional compensating circuitry will be necessary to mitigate the DCM
situation, with complexity increasing as low-THD conditions are expanded.
To maintain <5% THD over 85 V-265 VRMS at full load only,
• Design LB to avoid DCM up to 250 V-260 VRMS, and
• Add a positive bias current injection circuit to VCSA and VCSB, which activates only at low-line (below ~155
VRMS). Bias current is adjusted empirically.
This is crude, fairly simple, and effective, but works only for full-load. The fixed bias current optimized for full load
is insufficient for lighter loads.
At lighter loads (say to 50%), one can follow the same method as above, with yet larger LB, or employ additional,
more complicated compensation techniques with variable bias levels and polarities under different conditions.
Ultimately, all compensation techniques are attempts to remove the influence of negative or positive magnetizing
current (iM) of the CT from the VRS signal. A fixed bias current has limited success in canceling a variable iM, and
more sophisticated adaptable bias-adjusting circuits are obviously more complicated and expensive.
Adjusting the switching period (TSW) by manipulating the values of RT and RDMX can be another technique, with
the objective to maintain CCM over more of the range of possible operating conditions. This can be effective as
long as variable switching frequency is permissible.
Also, low-loss resistive sensing can replace the CT if very wide GBW operational amplifiers are available. But
drawbacks of this approach include cost, complexity, leading-edge spikes (from gate drive), etc.
References
1. O’Loughlin, Michael, “An Interleaving PFC Pre-Regulator for High-Power Converters”, Texas Instruments,
Inc. 2006 Unitrode Power Supply Seminar, Topic 5
2. Erickson, Robert W., “Fundamentals of Power Electronics”, 1st ed., pp. 604-608 Norwell, MA: Kluwer
Academic Publishers, 1997
3. Creel, Kirby “Measuring Transformer Distributed Capacitance”, White Paper, Datatronic Distribution, Inc.
website: http://www.datatronics.com/pdf/distributed_capacitance_paper.pdf
Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): UCC28070
25
PRODUCT PREVIEW
This reverse inductor current through the CT drives a reverse magnetizing current through the CT's inductance
which subsequently adds to the VRS signal level during the next switching cycle on-time. This additional signal
level overstates the scaled inductor current to the Current Amplifier (CA) with respect to the VIMO reference and
the CA acts to reduce the duty-cycle, thus maintaining and reinforcing the DCM. So it is a positive feedback
situation whereby DCM is artificially maintained along substantial portions of the lower sinewave, until VIN
becomes high enough to instigate CCM. Once in CCM, the current waveform faithfully follows VIMO until DCM
begins again some time after the peak of VIN.
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated