TI UC1864

UC1861-1868
UC2861-2868
UC3861-3868
Resonant-Mode Power Supply Controllers
FEATURES
DESCRIPTION
• Controls Zero Current Switched (ZCS) The UC1861-1868 family of ICs is optimized for the control of Zero Curor Zero Voltage Switched (ZVS)
rent Switched and Zero Voltage Switched quasi-resonant converters. DifQuasi-Resonant Converters
ferences between members of this device family result from the various
combinations of UVLO thresholds and output options. Additionally, the
• Zero-Crossing Terminated One-Shot
one-shot pulse steering logic is configured to program either on-time for
Timer
ZCS systems (UC1865-1868), or off-time for ZVS applications (UC1861• Precision 1%, Soft-Started 5V
1864).
Reference
The primary control blocks implemented include an error amplifier to com• Programmable Restart Delay
pensate the overall system loop and to drive a voltage controlled oscillator
Following Fault
(VCO), featuring programmable minimum and maximum frequencies. Triggered by the VCO, the one-shot generates pulses of a programmed maxi• Voltage-Controlled Oscillator (VCO)
mum width, which can be modulated by the Zero Detection comparator.
with Programmable Minimum and
Maximum Frequencies from 10kHz to This circuit facilitates “true” zero current or voltage switching over various
line, load, and temperature changes, and is also able to accommodate the
1MHz
resonant components' initial tolerances.
• Low Start-Up Current (150µA typical)
Under-Voltage Lockout is incorporated to facilitate safe starts upon
• Dual 1 Amp Peak FET Drivers
power-up. The supply current during the under-voltage lockout period is
typically less than 150µA, and the outputs are actively forced to the low
• UVLO Option for Off-Line or DC/DC
state.
(continued)
Applications
Device
UVLO
Outputs
“Fixed”
1861
16.5/10.5
Alternating
Off Time
1862
16.5/10.5
Parallel
Off Time
1863
36014
Alternating
Off Time
1864
36014
Parallel
Off Time
1865
16.5/10.5
Alternating
On Time
1866
16.5/10.5
Parallel
On Time
1867
36014
Alternating
On Time
1868
36014
Parallel
On Time
BLOCK DIAGRAM
Pin numbers refer to the J and N packages.
10/98
UDG-92018
UC1861-1868
UC2861-2868
UC3861-3868
DESCRIPTION (cont.)
UVLO thresholds for the UC1861/62/65/66 are 16.5V
(ON) and 10.5V (OFF), whereas the UC1863/64/67/68
thresholds are 8V (ON) and 7V (OFF). After VCC exceeds the UVLO threshold, a 5V generator is enabled
which provides bias for the internal circuits and up to
10mA for external usage.
start delay, and the internal system reference.
Each device features dual 1 Amp peak totem pole output
drivers for direct interface to power MOSFETS. The outputs
are
programmed
to
alternate
in
the
UC1861/63/65/67 devices. The UC1862/64/66/68 outputs operate in unison alllowing a 2 Amp peak current.
A Fault comparator serves to detect fault conditions and
set a latch while forcing the output drivers low. The SoftRef pin serves three functions: providing soft start, re-
CONNNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
PLCC-20 & LCC-20 (Top View)
Q & L Package
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Output Current
Source or Sink (Pins 11 & 14) . . . . . . . . . . . . . . . . . . . . . 0.5A
DC Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5A
Power Ground Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V
Inputs (Pins 2, 3, 10, & 15) . . . . . . . . . . . . . . . . . . . . –0.4 to 7V
Error Amp Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±2mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Junction Temperature (Operating). . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C
PACKAGE PIN FUNCTION
All voltages are with respect to signal ground and all currents
are positive into the specified terminal. Pin numbers refer to
the J and N packages. Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and
limitations of packages.
DIL-16, SOIC-16 (Top View)
J or N, DW Packages
2
FUNCTION
PIN
Soft Ref
5V
NI
INV
E/A Out
Sig Gnd
Range
RMIN
CVCO
RC
Zero
NC
NC
A Out
Pwr Gnd
Pwr Gnd
VCC
B Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
UC1861-1868
UC2861-2868
UC3861-3868
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°C≤TA≤125°C for the
UC186x, –25°C≤TA≤85°C for the UC286x, and 0°C≤TA≤70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,
C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
5V Generator
Output Voltage
Short Circuit Current
Soft-Reference
12V ≤ Vcc ≤ 20V, –10mA ≤ IO ≤ 0mA
VO = 0V
4.8
5.0
–150
5.2
V
–15
mA
Restart Delay Current
V = 2V
10
20
35
µA
Soft Start Current
V = 2V
–650
–500
–350
µA
Reference Voltage
TJ = 25°C, IO = 0A
4.95
5.00
12V ≤ VCC ≤ 20V, –200µA ≤ IO ≤ 200µA
4.85
Line Regulation
Load Regulation
Error Amplifier (Note 3)
5.05
V
5.15
V
12V ≤ VCC ≤ 20V
2
20
mV
–200µA ≤ IO ≤ 200µA
10
30
mV
10
mV
Input Offset Voltage
VCM = 5V, Vo = 2V, IO = 0A
–10
Input Bias Current
VCM = 0V
–2.0
–0.3
µA
Voltage Gain
Vcm = 5V, 0.5V ≤ VO ≤ 3.7V, IO = 0A
70
100
dB
Vcm = 5V, VO = 2V, 12V ≤ VCC ≤ 20V
70
100
dB
65
Power Supply Rejection Ratio
Error Amplifier (Note 3) (cont.)
Common Mode Rejection Ratio
0V ≤ Vcm ≤ 6V, VO = 2V
VOUT Low
VID = –100mV, IO = 200µA
VOUT High
VID = 100mV, IO = –200µA
3.9
4.2
V
(Note 4)
0.5
0.8
MHz
VID (Error Amp) = 100mV, TJ = 25°C
450
500
VID (Error Amp) = 100mV
425
VID (Error Amp) = –100mV, TJ = 25°C
45
VID (Error Amp) = –100mV
42
Unity Gain Bandwidth
Voltage Controlled Oscillator
Maximum Frequency
Minimum Frequency
100
0.17
50
dB
0.25
550
V
kHz
575
kHz
55
kHz
58
kHz
One Shot
Zero Comparator Vth
0.45
Propagation Delay
(Note 4)
Maximum Pulse Width
VZERO = 1V
0.50
0.55
V
120
200
ns
1000
1150
ns
2.5
4
5.5
4
5.5
7
3.8
5.5
7
25
45
ns
850
Maximum to Minimum Pulse
VZERO = 0V
UCx861 – UCx864
Width Ratio
VZERO = 0V
UCx865 – UCx868. –55°C to +85°C
VZERO = 0V
UCx865 – UCx868, +125°C
Output Stage
Rise and Fall Time
CLOAD = 1nF (Note 4)
Output Low Saturation
IO = 20mA
0.2
0.5
V
IO = 200mA
0.5
2.2
V
Output High Saturation
UVLO Low Saturation
Fault Comparator
IO = –200mA, down from Vcc
1.7
2.5
V
IO = 20mA
0.8
1.5
V
3.00
3.15
V
100
200
ns
Fault Comparator Vth
Delay to Output
2.85
(Note 4) (Note 5)
3
UC1861-1868
UC2861-2868
UC3861-3868
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°C≤TA≤125°C for the
UC186x, –25°C≤TA≤85°C for the UC286x, and 0°C≤TA≤70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,
C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
UVLO
Vcc Turn-on Threshold
UCx861, UCx862, UCx865, UCx866
15
16.5
18
V
UCx863, UCx864, UCx867, UCx868
7
8.0
9
V
Vcc Turn-off Threshold
UCx861, UCx862, UCx865, UCx866
9.5
10.5
11.5
V
UCx863, UCx864, UCx867, UCx868
6
7.0
8
V
Icc Start
VCC = VCC(on) – 0.3V
150
300
µA
Icc Run
VID = 100mV
25
32
mA
Note 1: Currents are defined as positive into the pin.
Note 2: Pulse measurement techniques are used to insure that TJ = TA.
Note 3: VID = V(NI) – V(INV).
Note 4: This parameter is not 100% tested in production but guaranteed by design.
Note 5: Vi = 0 to 4V
tr(Vi) 10ns
tpd = t(Vo = 6V) – t(Vi = 3V)
APPLICATION INFORMATION
UVLO & 5V GENERATOR (See Figure 1): When power
is applied to the chip and Vcc is less than the upper
UVLO threshold, Icc will be less than 300µA, the 5V generator will be off, and the outputs will be actively held low.
The fault pin is input to a high speed comparator with a
threshold of 3V. In the event of a detected fault, the fault
latch is set and the outputs are driven low. If Soft-Ref is
above 4V, the delay latch is set. Restart delay is timed as
Soft-Ref is discharged by 20µA. When Soft-Ref is fully
discharged, the fault latch is reset if the fault input signal
is low. The Fault pin can be used as a system shutdown
pin.
When Vcc exceeds the upper UVLO threshold, the 5V
generator turns on. Until the 5V pin exceeds 4.9V, the
outputs will still remain low.
The 5V pin should be bypassed to signal ground with a
0.1µF capacitor. The capacitor should have low equivalent series resistance and inductance.
If a fault is detected during soft-start, the fault latch is set
and the outputs are driven low. The delay latch will remain reset until Soft-Ref charges to 4V. This sets the delay latch, and restart delay is timed. Note that restart
delay for a single fault event is longer than for recurring
faults since Soft-Ref must be discharged from 5V instead
of 4V.
FAULT AND SOFT-REFERENCE (See Figure 1): The
Soft-Ref pin serves three functions: system reference, restart delay, and soft-start. Designed to source or sink
200µA, this pin should be used as the input reference for
the error amplifier circuit. This pin requires a bypass capacitor of at least 0.1µF. This yields a minimum soft-start
time of 1ms.
The restart delay to soft-start time ratio is 24:1 for a fault
occurring during normal operation and 19:1 for faults occurring during soft-start. Shorter ratios can be programmed down to a limit of approximately 3:1 by the
addition of a 20kΩ or larger resistor from Soft-Ref to
ground.
Under-Voltage Lockout sets both the fault and restart delay latches. This holds the outputs low and discharges
the Soft-Ref pin. After UVLO, the fault latch is reset by
the low voltage on the Soft-Ref pin. The reset fault latch
resets the delay latch and Soft-Ref charges via the 0.5mA
current source.
A 100kΩ resistor from Soft-Ref to 5V will have the effect
of permanent shut down after a fault since the internal
20µA current source can't pull Soft-Ref low. This feature
can be used to require recycling Vcc after a fault. Care
must be taken to insure Soft-Ref is indeed low at start up,
or the fault latch will never be reset.
4
UC1861-1868
UC2861-2868
UC3861-3868
APPLICATION INFORMATION
UDG-92020
UDG-92021-1
Figure 1. UVLO, 5V, fault and soft-ref.
5
UDG-92022-1
UDG-92023-1
Figure 2. Error Amp, Voltage Controlled Oscillator, and One Shot
6
UC1861-1868
UC2861-2868
UC3861-3868
APPLICATION INFORMATION
The Error Amplifier directly controls the oscillator frequency. E/A output low corresponds to minimum frequency and output high corresponds to maximum
frequency. At the end of each oscillator cycle, the RC pin
is discharged to one diode drop above ground. At the beginning of the oscillator cycle, V(RC) is less than Vth1
and so the output of the zero detect comparator is ignored. After V(RC) exceeds Vth1, the one shot pulse will
be terminated as soon as the zero pin falls below 0.5V or
V(RC) exceeds Vth2. The minimum one shot pulse width
is approximately given by the equation:
Minimum oscillator frequency is set by Rmin and Cvco.
The minimum frequency is approximately given by the
equation:
FMIN ≅
43
.
RMIN • CVCO
Maximum oscillator frequency is set by Rmin, Range &
Cvco. The maximum frequency is approximately given by
the equation:
FMAX ≅
(RMIN
3.3
/ / Range ) • CVCO
Tpw(min)
0.3 R C.
The maximum pulse width is approximately given by:
Tpw(max)
1.2 R
C.
STEERING LOGIC
UDG-92014
UDG-92013
The steering logic is configured on the UC1861,63 to result in
dual non-overlapping square waves at outputs A & B. This is
suited to drive dual switch ZVS systems.
The steering logic is configured on the UC1862,64 to result in
inverted pulse trains occurring identically at both output pins.
This is suited to drive single switch ZVS systems. Both outputs
are available to drive the same MOSFET gate. It is advisable
to join the pins with 0.5 ohm resistors.
UDG-92015
The steering logic is configured on the UC1865,67 to result in
alternating pulse trains at outputs A & B. This is suited to drive
dual switch ZCS systems.
UDG-92016
The steering logic is configured on the UC1866,68 to result in
non-inverted pulse trains occurring identically at both output
pins. This is suited to drive single switch ZCS systems. Both
outputs are available to drive the same MOSFET gate. It is advisable to join the pins with 0.5 ohm resistors.
7
UC1861-1868
UC2861-2868
UC3861-3868
APPLICATION INFORMATION (cont.)
UDG-92017
Figure 3. Current waveforms.
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8
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