SEMTECH ACS8515P

ACS8515 LC/P
ADVANCED COMMUNCIATIONS
Line Card Protection Switch
for SONET or SDH Network Elements
FINAL
Description
Features
The ACS8515 is a highly integrated, single-chip
solution for “hit-less” protection switching of SEC
clocks from Master and Slave SETS clockcards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching against master clock failure. A
further input is provided for an optional standby
SEC clock. The ACS8515 is fully compliant with
the required specifications and standards.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card clock, e.g. 8
kHz distributed on the back plane and 19.44 MHz
generated on the line cards.
An SPI serial port is incorporated, providing access to the configuration and status registers for
device setup.
The ACS8515 can utilise either a low cost XO
oscillator module, or a TCXO with full temperature calibration - as required by the application.
Block Diagram
3 x SEC Input
Master/Slave
+ Standby:
N x 8kHz
1.544MHz
2.048MHz
6.48M Hz
19.44MHz
38.88MHz
51.84MHz
77.76MHz
155.52MHz
Plus:
MFrSync
•Suitable for Stratum 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
•Meets AT&T, ITU-T, ETSI and Telcordia
specifications
•Three SEC input clocks, from 2 kHz to 155.52
MHz
•Generates two SEC output clocks, up to 311.04
MHz
•Frequency translation of SEC input clock to a
different local line card clock
•Robust input clock source frequency and
activity monitoring on all inputs
•Supports Free-Run, Locked and Holdover
modes of operation
•Automatic “hit-less” source switchover on loss
of input
•External force fast switch between SEC inputs
•Phase build-out for output clock phase
continuity during input switchover
•SPI compatible serial microprocessor interface
•Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
•Single 3.3 v operation. 5 v I/O compatible
•Operating temperature (ambient) -40°C to
+85°C
•Available in 64 pin LQFP package
3xSEC
Input
Ports
2xSEC
APLL
Monitors
DPLL
Frequency Synthesis
Frequency
Dividers
MFrSync
Chip C lock
Generator
Priority
Table
Register
Set
Output
Ports
FrSync
MFrSync
2 x SEC Output
including:
1.544/2.048MHz
3.088/4.096MHz
6.176/8.192MHz
12.352/16.384MHz
19.44MHz
38.88MHz
155.52MHz
311.04MHz
Plus:
2kHz MFrSync
8kHz FrSync
SPI Compatible Serial
M icroprocessor Port
TCXO or XO
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Table of Contents
Pin diagram................................................................................................................................................3
Pin descriptions.........................................................................................................................................4
Functional description...............................................................................................................................6
Local oscillator clock..........................................................................................................................................................6
Input Interfaces..................................................................................................................................................................7
Input reference clock ports................................................................................................................................................7
Input wander and jitter tolerance......................................................................................................................................9
Output clock ports...........................................................................................................................................................10
Output wander and jitter..................................................................................................................................................11
Phase variation.................................................................................................................................................................13
Phase build-out.................................................................................................................................................................15
Microprocessor interface................................................................................................................................................15
Interrupt enable and clear...............................................................................................................................................16
Register map.....................................................................................................................................................................17
Register map description.................................................................................................................................................20
Selection of input reference clock sources...................................................................................................................27
Activity monitoring...........................................................................................................................................................28
Modes of operation..........................................................................................................................................................30
Power on reset - PORB.....................................................................................................................................................31
Electrical specification............................................................................................................................33
Absolute maximum range...............................................................................................................................................33
Operating conditions.......................................................................................................................................................33
TTL DC characterisitics...................................................................................................................................................33
PECL DC characteristics..................................................................................................................................................35
LVDS DC characteristics..................................................................................................................................................36
Jitter characteristics........................................................................................................................................................37
Microprocessor inter face timing characteristics.......................................................................................41
Serial mode.......................................................................................................................................................................41
Package information................................................................................................................................43
Application information............................................................................................................................45
Simplified application schematic...................................................................................................................................45
Revision History.......................................................................................................................................46
Order information....................................................................................................................................47
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Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
IC
AGND
VA1+
INTREQ
REFCLK
DGND
VD+
VD+
DGND
DGND
VD+
SRCSW
VA2+
AGND
IC
FrSync
MFrSync
O1POS
O1NEG
GND_DIFF
VDD_DIFF
SEC1_POS
SEC1_NEG
SEC2_POS
SEC2_NEG
VDD5
Sync2k
SEC1
SEC2
DGND
VDD
1
ACS8515
LC/P
Rev 2.0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SONSDHB
IC
IC
IC
IC
NC
DGND
VDD
O2
NC
VDD
DGND
SDO
IC
IC
IC
PORB
SCLK
VDD
VDD
CSB
SDI
CLKE
IC
DGND
VDD
VDD
IC
VDD
IC
SEC3
IC
Top view of 64 pin LQFP package.
NC - Not Connected, IC - Internally Connected
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Pin Descriptions
Power
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
8, 9, 12
V D+
P
-
S u p p l y v o l t ag e : Digital sup p ly to gates in analog section, +3.3
Volts. +/- 10%
22
V DD_DIFF
P
-
S u p p l y v o l t ag e : Digital sup p ly for d ifferential outp ut p ins 19 &
20, +3.3 Volts. +/- 10%
27
V DD5
P
-
V D D 5: Digital sup p ly for +5 Volts tolerance to inp ut p ins. Connect
to +5 volts (+/- 10%) for clamp ing to +5 v. Connect to V DD for
clamp ing to +3.3 v. Leave floating for no clamp ing, inp ut p ins
tolerant up to +5.5 v.
32, 36, 38,
39, 45, 46,
54, 57
V DD
P
-
S u p p l y v o l t ag e : Digital sup p ly to logic, +3.3 Volts. +/- 10%
4
VA 1+
P
-
S u p p l y v o l t ag e : A nalog sup p ly to clock multip ying A PLL, +3.3
Volts. +/- 10%
14
VA 2+
P
-
S u p p l y v o l t ag e : A nalog sup p ly to outp ut A PLL, +3.3 Volts. +/- 10%
7, 10, 11,
31, 40, 53,
58
DGN D
P
-
S u p p l y G r o u n d : Digital ground for logic
21
GN D_DIFF
P
-
S u p p l y G r o u n d : Digital ground for d ifferential outp ut p ins 19 &
20
1, 3, 15
A GN D
P
-
S u p p l y G r o u n d : A nalog ground
No connections
PIN
SYM B OL
IO
T YPE
55, 59
NC
-
-
N ot C on n ect ed : Leave to Float
2, 16, 60,
61, 62, 63
IC
-
-
I n t er n al l y C on n ect ed : Leave to Float
37
IC
-
-
I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG control
reset inp ut on next revision
41
IC
-
-
I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG test mode
select inp ut on next revision
49
IC
-
-
I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG
b oundary scan clock inp ut on next revision
50
IC
-
-
I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG serial test
data outp ut on next revision
51
IC
-
-
I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG serial test
data inp ut on next revision
Revision 2.05/Jan 2001 ã2001 Semtech Corp
N A M E /DE SCR I P T I O N
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Others
PIN
SYM B OL
IO
T YPE
N A M E /DE SCR I P T I O N
5
IN T R E Q
O
-
6
REFCLK
I
TTL
R e f e r e n ce cl o ck : 12.8 MHz (refer to section h ead ed Local
Oscillator Clock)
13
SRCSW
I
T T LD
S o u r ce sw i t ch i n g : Force fast source sw itch ing on SEC1 and SEC2
17
FrSync
O
TTL
O u t p u t r e f e r e n ce : 8 kHz Frame Sync, 50:50 mark/sp ace ratio
outp ut
18
MFrSync
O
TTL
O u t p u t r e f e r e n ce : 2 kHz Multi-Frame Sync, 50:50 mark/sp ace
ratio outp ut
19
20
O1POS
O1N EG
O
LV DS/
PECL
O u t p u t r e f e r e n ce : Programmab le, d efault 38.88 MHz LV DS
23
24
SEC1_POS
SEC1_N EG
I
LV DS/
PECL
I n p u t r e f e r e n ce : Programmab le, d efault 19.44 MHz LV DS
25
26
SEC2_POS
SEC2_N EG
I
PECL/
LV DS
I n p u t r e f e r e n ce : Programmab le, d efault 19.44 MHz PECL
28
Sync2k
I
T T LD
M u l t i - Fr am e S y n c 2 k H z : Multi-Frame Sync inp ut
29
SEC1
I
T T LD
I n p u t r e f e r e n ce : Programmab le, d efault 8 kHz
30
SEC2
I
T T LD
I n p u t r e f e r e n ce : Programmab le, d efault 8 kHz
33
IC
-
-
34
SEC3
I
T T LD
35
IC
-
-
42
CLKE
I
T T LD
S C L K e d g e se l e ct : SCLK active ed ge select, CLKE=1 selects
falling ed ge of SCLK to b e active
43
SDI
I
T T LD
M i cr o p r o ce sso r i n t e r f ace ad d r e ss: Serial d ata inp ut
44
CSB
I
T T LU
C h i p se l e ct ( act i v e l o w ) : Th is p in is asser ted Low b y th e
microp rocessor to enab le th e microp rocessor inter face
47
SCLK
I
T T LD
A d d r e ss L at ch E n ab l e : d efault Serial d ata clock. Wh en th is p in
transitions from h igh to low, th e ad d ress b us inp uts are latch ed
into th e internal registers
48
PORB
I
T T LU
P o w e r o n r e se t : Master reset. If PORB is forced Low, all internal
states are reset b ack to d efault values
I n t e r u p t r e q u e st : Softw are Interrup t enab le
I n t e r n al l y co n n e ct e d : Connect to GN D. Reserved for Slave Multiframe sync 2 kHz inp ut on next revision.
I n p u t r e f e r e n ce : External stand b y reference clock source,
p rogrammab le, d efault 19.44 MHz
I n t e r n al l y co n n e ct e d : Connect to GN D. Reserved for external
stand b y 2 kHz Multi-frame sync inp ut on next revision.
Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor
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PIN
SYM B OL
IO
T YPE
52
SDO
O
T T LD
M i cr o p r o ce sso r i n t e r f ace ad d r e ss: Serial d ata outp ut
56
O2
O
TTL
O u t p u t r e f e r e n ce : 19.44 MHz fixed
T T LD
S O N E T S D H B : SON ET or SDH freq uency select: sets th e initial
p ow er up state (or state after a PORB) of th e SON ET/SDH
freq uency selection registers, ad d r 34h , b it 2 and ad d r 38, b it 5.
Wh en low SDH rates are selected (2.048 MHz etc) and w h en set
h igh SON ET rates are selected (1.544 MHz etc). Th e register states
can b e ch anged after p ow er up b y softw are
64
SON SDHB
I
N A M E /DE SCR I P T I O N
programmable (0.1 Hz up to 20 Hz cut-off
points).
Functional description
The ACS8515 is a highly integrated, single-chip
solution for “hit-less” protection switching of
SEC clocks from Master and Slave SETS clock
cards in a SONET or SDH Network Element.
The ACS8515 has fast activity monitors on the
inputs and will implement automatic system
protection switching for Master/Slave SEC clock
failure. The standby SEC clock will be selected
if both the Master and Slave input clocks fail.
The selection of the Master/Slave input can
also be forced by a Force Fast Switch pin.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card - e.g. 8 kHz
distributed on the back plane and 19.44 MHz
generated on the line cards.
The ACS8515 has three SEC clock inputs
(Master, Slave and Standby) and a single MultiFrame Sync input, for synchronising the frame
and multi-frame sync outputs.
The ACS8515 generates two SEC clock outputs
via PECL/LVDS and TTL ports, with spot
frequencies from 1.544/2.048 MHz up to
311.04 MHz. The ACS8515 also provides an 8
kHz Frame Sync and 2 kHz Multi-Frame Sync
output clock.
The ACS8515 has a high tolerance to input
jitter and wander. The output jitter and wander
are low, where the wander transfer is
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The ACS8515 includes an SPI compatible serial
microprocessor port, providing access to the
configuration and status registers for device
setup.
Local Oscillator Clock
The Master system clock on the ACS8515
should be provided by an external clock oscillator
of frequency 12.80 MHz. The exact clock
specification is dependent on the quality of
Holdover performance required in the
application.
In most Line Card protection switching
applications where there is a high chance that
at least one SEC reference input will be
available, the long term stability requirement
for Holdover is not appropriate and an
inexpensive crystal local oscillator can be used.
In other applications where there may be a
requirement for longer term Holdover stability
to meet the ITU standards for Stratum 3, a
higher quality oscillator can be used.
Please contact Semtech for information on
crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less
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important than the stability since any frequency
offset can be compensated by adjustment of
register values in the IC. This allows for
calibration and compensation of any crystal
frequency variation away from its nominal value.
+/- 50 ppm adjustment would be sufficient to
cope with most crystals, in fact the range is an
order of magnitude larger due to the use of
two 8 bit register locations. The setting of the
conf_nominal_frequency register allows for this
adjustment. An increase in the register value
increases the output frequencies by 0.02 ppm
for each LSB step. The default value (in decimal)
is 39321. The minimum being 0 and the
maximum 65535, gives a +500 ppm to -700
ppm adjustment range of the output
frequencies.
For example, if the crystal was oscillating at
12.8 MHz + 5ppm, then the calibration value
in the register to give a -5 ppm adjustment in
output frequencies to compensate for the
crystal inaccuracy, would be : 39321 - (5 /
0.02) = 39071 (decimal).
Input Interfaces
The ACS8515 supports up to three individual
input reference clock sources via TTL/CMOS
and PECL/LVDS technologies. These interface
technologies support 3.3 V and 5 V operation.
Input Reference Clock Ports
The input reference clock ports are arranged in
groups. Group one comprises a TTL port (SEC1)
and a PECL/LVDS port (SEC1POS and
SEC1NEG). Group two comprises a TTL port
(SEC2) and a PECL/LVDS port (SEC2POS and
SEC2NEG). Group three comprises a TTL port
(SEC3). For group one and group two, only one
of the two input ports types must be active at
any time, the other must not be driven by a
reference input. Unused PECL/LVDS differential
inputs should be fixed with one input high (VDD)
and the other low (GND), or set in LVDS mode
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and left floating (in which case one input is
internally pulled high and the other low).
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
64). Specific frequencies and priorities are set
by configuration.
The TTL ports (compatible also with CMOS
signals) support clock speeds up to 100 MHz,
with the highest spot frequency being 77.76
MHz. Clock speeds above 100 MHz should not
be applied to the TTL ports. The PECL/LVDS
ports support the full range of clock speeds,
up to 155.52 MHz.
The actual spot frequencies supported are; 8
kHz (and N x 8 kHz), 1.544 MHz/2.048 MHz,
6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, and 155.52 MHz. The
frequency selection is programmed via the
cnfg_ref_source_frequency register. The
internal DPLL will normally lock to the selected
input at the frequency of the input, eg. 19.44
MHz will lock the DPLL phase comparisons at
19.44 MHz. It is, however, possible to utilise
an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase
comparisons in the DPLL. This pre-divider can
be used in one of 2 ways;
(i) any of the supported spot frequencies can be divided to
8 kHz by setting the "lock8K" bit (bit 6) in the appropriate
cnfg_ref_source_frequency register location
(ii) any multiple of any supported frequency can be
supported by using the "DivN" feature (bit 7 of the
cnfg_ref_source_frequency register). Any reference input
can be set to lock at 8 kHz independently of the
frequencies and configurations of the other inputs.
Any reference input with the "DivN" bit set in
the cnfg_ref_source_frequency register will
employ the internal pre-divider prior to the DPLL
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S E C S o u r ce G r o u p
D e f au l t
P ri ori t y
8kHz
8kHz
1
1 (4)
8kHz
8kHz
2
3 (5)
Up to 155.52MHz (N ote 2)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
1
2 (6)
Up to 155.52MHz (N ote 2)
Default (SON ET):
19.44MHz
Default (SDH):
19.44MHz
2
4 (7)
TTL/CMOS
Up to 100MHz (N ote 1)
Default (SON ET):
Default (SDH):
3
5 (10)
TTL/CMOS
2kHz Multi Frame Sync
-
-
P o r t N am e
I n p u t P or t
Te c h n o l o g y
SEC1
TTL/CMOS
Up to 100MHz (N ote 1)
Default (SON ET):
Default (SDH):
SEC2
TTL/CMOS
Up to 100MHz (N ote 1)
Default (SON ET):
Default (SDH):
SEC1
LVDS/PECL
LVDS default
SEC2
PECL/LVDS
PECL default
SEC3
SYN C1
Fr eq u en ci es S u p p or t ed
19.44MHz
19.44MHz
(N ote 3)
Table 1: Input Reference Source Selection and Group allocation
Notes for Table 1.
Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency
being 77.76 MHz. The actual spot frequencies are 8 kHz (N x 8 kHz), 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz,
38.88 MHz, 51.84 MHz and 77.76 MHz.
Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output
clock frequencies available for SONET and SDH applications. F1/F2 means that the output frequency is F1 for SONET mode
selection and F 2 for SDH mode selection.
Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the
ACS8510.
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
locking. The cnfg_freq_divn register contains
the divider ratio N where the reference input
will get divided by (N+1) where 0<N<214-1. The
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
input frequency. When using the “DivN” feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the ‘lock8k’ bit high (bit
6 in cnfg_ref_source_frequency register). Any
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input set to DivN must have the frequency
monitors disabled (if the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the “DivN” feature, only one N can be
programmed, hence all inputs using the “DivN”
feature must require the same division to get
to 8 kHz.
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PECL and LVDS ports support the spot clock
frequencies listed above plus 155.52 MHz. The
choice of PECL or LVDS compatibility is
programmed via the cnfg_differential_inputs
register.
Unused PECL/LVDS differential inputs should
be fixed with one input high (VDD) and the other
input low (GND), or set in LVDS mode and left
floating, in which case one input is internally
pulled high and the other low.
Input Wander and Jitter Tolerance
The ACS8515 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI T1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for
each input port in Table 2. Minimum jitter
tolerance masks are specified in Figures 1 and
2, and Tables 3 and 4, respectively. The
ACS8515 will tolerate wander and jitter
J i t t er
To l e r a n c e
Fr eq u en cy M on i t or
A c c e p t an c e R an g e
G.703
G.783
G.823
+/- 16.6 p p m
GR-1244-CORE
components greater than those shown in Figure
1 and Figure 2, up to a limit determined by a
combination of the apparent long-term
frequency offset caused by wander and the
eye-closure caused by jitter (the input source
will be rejected if the offset pushes the
frequency outside the hold-in range for long
enough to be detected, whilst the signal will
also be rejected if the eye closes sufficiently to
affect the signal purity). The ‘8klocking’ mode
should be engaged for high jitter tolerance
according to these masks.
All reference clock ports are monitored for
quality, including frequency offset and general
activity. Single short-term interruptions in
selected reference clocks may not cause
rearrangements, whilst longer interruptions, or
multiple, short-term interruptions, will cause
rearrangements, as will frequency offsets which
are sufficiently large or sufficiently long to cause
loss-of-lock in the phase-locked loop. The failed
reference source will be removed from the
priority table and declared as unserviceable,
until its perceived quality has been restored to
Fr eq u en cy
A c c e p t an c e R an g e
( Pull-in)
Fr eq u en cy
A c c e p t an c e
R an g e ( H o l d - i n )
Fr eq u en cy
A c c e p t an c e R an g e
( P u l l - ou t )
+/- 4.6 p p m
(see N ote 1)
+/- 4.6 p p m
(see N ote 1)
+/- 4.6 p p m
(see N ote 1)
+/- 9.2 p p m
(see N ote 2)
+/- 9.2 p p m
(see N ote 2)
+/- 9.2 p p m
(see N ote 2)
Table 2: Input Reference Source Jitter Tolerance.
Notes for Table 2.
Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the
external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.
Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal
frequency of 12.8 MHz.
Note 3. The power up default PDLL range is as stated in note 2, but the range is also programmable from 0 to 80 ppm
in 0.08 ppm steps.
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disabled so the input reference source is not
automatically rejected as out of frequency
range.
an acceptable level.
The registers reg sts_curr_inc_offset (address
0C, 0D, 07) report the frequency of the DPLL
with respect to the external TCXO frequency.
This is a 19 bit signed number with one LSB
representing 0.0003 ppm (range of +/- 80
ppm). Reading this regularly can show how the
currently locked source is varying in value e.g.
due to wander on its input.
Output Clock Ports
The ACS8515 supports two SEC output clocks
on both TTL and PECL/LVDS ports and a pair
of secondary output clocks, ‘Frame-Sync’ and
‘Multi-Frame-Sync’. The two output clocks are
individually controllable. The ‘Frame-Sync’ and
‘Multi-Frame-Sync’ are derived from the main
SEC clock. The frequencies of the output clock
are selectable from a range of pre-defined spot
frequencies, and a variety of output
technologies are supported, as defined in Table
5.
The ACS8515 performs automatic frequency
monitoring with an acceptable input frequency
offset range of +/- 16.6 ppm. The ACS8515
DPLL has a programmable frequency limit of
+/- 80 ppm. If the range is programmed to be
> 16.6 ppm, the activity monitors should be
$
$
$
$
$
-LWWHUDQGZDQGHUIUHTXHQF\ORJVFDOH
I
I
I
I
I
I
I
I
I
Figure 1: Minimum Input Jitter Tolerance for inputs supporting G.783 compliant sources
ST M
l evel
STM-1
P e ak t o p e ak am p l i t u d e
( u n i t I n t e r v al )
Fr eq u en cy ( H z )
A0
A1
A2
A3
A4
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
2800
311
39
1.5
0.15
12u
178u
1.6m
15.6m
0.125
19.3
500
6.5k
65k
1.3m
Table 3: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.783 compliant sources
Revision 2.05/Jan 2001 ã2001 Semtech Corp
10
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3HDNWRSHDNMLWWHUDQGZDQGHUDPSOLWXGHORJ
VFDOH
$
$
-LWWHUDQGZDQGHUIUHTXHQF\ORJVFDOH
I
I
I
I
Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources
Ty p e
S p ec.
A mp litud e
( U I p k-p k)
Fr e q u e n cy
( Hz )
A1
A2
F1
F2
F3
F4
DS1
G R - 1244- C O R E
5
0.1
10
500
8k
40k
E1
I T U G. 823
1.5
0.2
20
2.4k
18k
100k
Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources
Low-speed Output Clock
Frame Sync and Multi-Frame Sync Clocks
The O2 SEC clock is supplied on a TTL port with
a fixed frequency of 19.44 MHz.
Frame Sync (8 kHz) and Multi-Frame Sync (2
kHz) clocks will be provided on outputs FrSync
and MFrSync. The FrSync and MFrSync clocks
have a 50:50 mark space ratio.
High-speed Output Clock
The O1 SEC clock is supplied on a PECL/LVDS
port with spot frequencies of 19.44 MHz, 38.88
MHz, 155.52 MHz, 311.04 MHz and Dig 1
(where Dig 1 is 1.544/2.048 MHz and multiples
of 2, 4 and 8 depending on SONET/SDH mode
setting). The actual frequency is selectable via
the cnfg_differential_outputs register. The O1
port can also support 311.04 MHz, which is
enabled via the cnfg_T0_output_enable
register. The O1 port can be made LVDS or
PECL
compatible
via
the
cnfg_differential_outputs register.
Revision 2.05/Jan 2001 ã2001 Semtech Corp
11
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
The magnitude of wander and jitter on the selected
input reference clock (in locked mode);
The internal wander and jitter transfer characteristic
(in locked mode);
The jitter on the local oscillator clock;
The wander on the local oscillator clock (in Hold-Over
mode).
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Wander and jitter are treated in different ways
to reflect their differing impacts on network
design. Jitter is always strongly attenuated,
whilst wander attenuation can be varied to suit
the application and operating state. Wander and
jitter attenuation is performed by using a digital
phase locked loop (DPLL) with a programmable
bandwidth. This gives a transfer characteristic
of a low pass filter, with a programmable pole.
It is sometimes necessary to change the filter
dynamics to suit particular circumstances - one
example being when locking to a new source,
the filter can be opened up to reduce locking
time and can then be gradually tightened again
to remove wander. Since wander represents a
relatively long-term deviation from the nominal
operating frequency, it affects the rate of supply
of data to the network element. Strong wander
attenuation limits the rate of consumption of
data to within a smaller range, so a larger buffer
store is required to prevent data loss. But, since
any buffer store potentially increases latency,
wander may often only need to be removed at
specific points within a network where buffer
stores are acceptable, such as at digital cross
connects. Otherwise, wander is sometimes not
required to be attenuated and can be passed
through transparently. The ACS8515 has
programmable wander transfer characteristics
in a range from 0.1 Hz to 20 Hz. The wander
and jitter transfer characteristic is shown in
Figure 3.
Wander on the local oscillator clock will not
have significant effect on the output clock whilst
in locked mode, so long as the DPLL bandwidth
is set high enough so that the DPLL can
compensate quickly enough for any frequency
changes in the crystal. In free-running or
Holdover mode wander on the crystal is more
significant. Variation in crystal temperature or
supply voltage both cause drifts in operating
frequency, as does ageing. These effects must
be limited by careful selection of a suitable
component for the local oscillator, as specified
in the section ‘Local Oscillator Clock’.
P or t
N am e
O u t p u t P or t
Te c h n o l o g y
O1
LVDS/PECL
LVDS default
O2
TTL/CMOS
19.44MHz fixed
FrSync
TTL/CMOS
FrSync, 8kHz. 50:50 mark/sp ace ratio
MFrSync
TTL/CMOS
MFrSync, 2kHz. 50:50 mark/sp ace ratio
Fr eq u en ci es S u p p or t ed
(N ote 1)
19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz, Dig1
Dig1 is 1.544 MHz/2.048 MHz and multip les of 2, 4 and 8
Table 5: Output Reference Source Selection table
Notes for Table 5.
Note 1. There are different output clock frequencies available for SONET and SDH applications. Dig 1 can be configured for
either frequency F1/F2, where the output frequency is F1 when the SONET mode is selected, and F2 when the SDH mode is
selected.
On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by
configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.
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3HDNWRSHDNMLWWHUDQGZDQGHUDPSOLWXGH
ORJVFDOH
-LWWHUFXWRIIORZIUHTXHQF\ +]
-LWWHUFXWRIIKLJKIUHTXHQF\ +]
8,#I
G%
G%
-LWWHUDQGZDQGHUIUHTXHQF\ORJVFDOH
Figure 3: Wander and Jitter Transfer Characteristsics
Phase Variation
There will be a phase shift across the ACS8515
between the selected input reference source
and the output clock. This phase shift may vary
over time but will be constrained to lie within
specified limits. The phase shift is characterised
using two parameters, MTIE (Maximum Time
Interval Error), and TDEV (Time Deviation), which,
although being specified in all relevent
specifications, differ in acceptable limits in each
one. Typical measurements for the ACS8515
are shown in Figures 4 and 5, for locked mode
operation. Figure 6 shows a typical
measurement of Phase Error accumulation in
Holdover mode operation.
The required performance for phase variation
during Holdover is specified in several ways
depending upon the particular circumstances
pertaining:
1. ETSI 300 462-5, Section 9.1, requires that the shortterm phase error during switchover (i.e., Locked to
Holdover to Locked) be limited to an accumulation rate
no greater than 0.05 ppm during a 15 second interval.
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13
2. ETSI 300 462-5, Section 9.2, requires that the longterm phase error in the Holdover mode should not
exceed {(a1+a2)S+0.5bS2+c}, where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10-4 ns/s2 (allowance for ageing)
c = 120 ns (allowance for entry into Holdover mode).
3. ANSI Tin1.101-1994, Section 8.2.2, requires that
the phase variation be limited so that no more than
255 slips (of 125 µs each) occur during the first day of
Holdover. This requires a frequency accuracy better
than:
((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm.
Temperature variation is not restricted, except to within
the normal bounds of 0 to 50 Celsius.
4. Bellcore GR.1244.CORE, Section 5.2. Table 4. shows
that an initial frequency offset of 50 ppb is permitted
on entering Holdover, whilst a drift over temperature
of 280 ppb is allowed; an allowance of 40 ppb is
permitted for all other effects.
5. ITU G.822, Section 2.6, requires that the slip rate
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1 00
G .8 1 3 o p tion 1 , co n sta n t te m p e rature w an de r lim it
T im e
(n s)
10
1
M T IE m e a su re m e n t o n 1 5 5 M H z o u tp u t, 1 9.44 M H z i/p (8 kH z lo ckin g),
V e c tro n 6 6 6 4 x tal
0 .1
0 .0 1
0 .01
0.1
1
10
100
1000
10000
O b s erv a tio n in terva l (s)
Figure 4: Maximum Time Interval Error of TOUT0 output port
10
G .8 13 optio n 1 con s tan t tem perature w ander lim it
T im e
(ns)
1
0 .1
T D E V m ea su rem e nt on 1 55 M H z ou tpu t, 19.44 M H z i/p (8kH z locking),
V ectron 6 664 xtal
0.01
0.01
0.1
1
10
1 00
1 000
100 00
O bs erva tio n interval (s )
Figure 5: Time Deviation of TOUT0 output port
10000000
Phase Error (ns)
1000000
P e rm itte d P h a s e E rro r L im it
100000
10000
1000
100
T y p ic a l m e a s u re m e n t, 2 5 °C c o n s ta n t te m p e ra tu re
10000
1000
100000
Figure 6: Phase error accumulation of TOUT0 output port in Holdover mode
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during category(b) operation (interpreted as being
applicable to Holdover mode operation) be limited to
less than 30 slips (of 125 µs each) per hour
((((60 x 60)/30)+125µs)/(60x60)) = 1.042 ppm.
Phase Build Out
is enabled. When PBO is enabled, it can also
be frozen, which will disable the PBO operation
on the next input reference switch, but will
remain with the current offset. If PBO is
disabled while the device is in the Locked mode,
there will be a phase jump on the output SEC
clocks as the DPLL locks back to 0 degree
phase error.
Phase Transient response and Holdover
Phase Build Out (PBO) is the function to minimise
phase transients on the output SEC clock during
input reference switching or mode switching. If
the currently selected input reference clock
source is lost (due to a short interruption, out
of frequency detection, or complete loss of
reference), the second, next highest priority
reference source will be selected. During this
transition, the Lost_Phase mode is entered.
The typical phase disturbance on clock
reference source switching will be less than 10
ns on the ACS8515. For clock reference
switching caused by the main input failing or
being disconnected, then the phase disturbance
on the output will still be less than the 120 ns
allowed for in the G.813 spec.
The actual
value is dependant on the frequency being
locked to.
The PBO requirement, as specified in Telcordia
GR1244-CORE, Section 5.7, in that a phase
transient of greater than 3.5 µs occuring in
less than 0.1 seconds should be absorbed, will
be implemented on a future version. ITU-T
G.813 states that the max allowable short term
phase transient response, resulting from a
switch from one clock source to another, with
Holdover mode entered in between, should be
a maximum of 1 µs over a 15 second interval.
The maximum phase transient or jump should
be less than 120 ns at a rate of change of less
than 7.5 ppm and the Holdover performance
should be better than 0.05 ppm.
Micro-Processor Interface
The ACS8515 incorporates a serial
microprocessor interface that is compatible with
the Serial Peripheral Interface (SPI) for device
setup.
Register Set
All registers are 8-bits wide, organised with the
most-significant bit positioned in the left-most
bit, with bit-significance decreasing towards the
right-most bit. Some registers carry several
individual data fields of various sizes, from
single-bit values (e.g., flags) upwards. Several
data fields are spread across multiple registers;
their organisation is shown in the register map.
Configuration Registers
Each configuration register reverts to a default
value on power-up or following a reset. Most
default values are fixed, but some will be pinsettable. All configuration registers can be read
out over the microprocessor port.
Status Registers
The Status Registers contain readable registers.
They may all be read from outside the chip but
are not writable from outside the chip (except
for a clearing operation). All status registers
are read via shadow registers to avoid data
hits due to dynamic operation. Each individual
status register has a unique location.
On the ACS8515, PBO can be enabled, disabled
or frozen using the µP interface. By default, it
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Register Access
Most registers are of one of two types,
configuration registers or status registers, the
exceptions being the Chip_revision register.
Configuration registers may be written to or read
from at any time (the complete 8-bit register
must be written, even if only one bit is being
modified). All status registers may be read at
any time and, in some status registers (such as
the ‘sts_interrupts’ register), any individual data
field may be cleared by writing a "1" into each
bit of the field (writing a "0" value into a bit will
not affect the value of the bit). Details of each
register are given in the Register Map and
Register Description sections.
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ
(active High).
Bits in the interrupt status register are set (high)
by the following conditions;
(i) any reference source becoming valid or going invalid
(ii) a change in the operating state (eg. Locked,
Holdover etc.)
(iii) brief loss of the currently selected reference source
All interrupt sources are maskable via the mask
register (cnfg_interrupt_mask), each one being
enabled by writing a '1' to the appropriate bit.
Revision 2.05/Jan 2001 ã2001 Semtech Corp
16
Any unmasked bit set in the interrupt status
register will cause the interrupt request pin to
be asserted (high).
All interrupts are cleared by writing a '1' to the
bit(s) to be cleared in the status register.
When all pending unmasked interrupts are
cleared the interrupt pin will go inactive (low).
The loss of the currently selected reference
source will eventually cause the input to be
considered invalid, triggering an interrupt. The
time taken to raise this interrupt is dependant
on the leaky bucket configuration of the activity
monitors. The very fastest leaky bucket setting
will still take up to 128 ms to trigger the
interrupt. The interrupt caused by the brief
loss of the currently selected reference source
is provided to facilitate very fast source failure
detection if desired. It is triggered after missing
just a couple of cycles of the reference source.
Some applications require the facility to switch
downstream devices based on the status of
the reference sources. In order to provide extra
flexibility, it is possible to flag the "main
reference failed" interrupt (addr 06, bit 6) on
the pin TDO. This is simply a copy of the status
bit in the interrupt register and is independent
of the mask register settings. The bit is reset
by writing to the interrupt status register in the
normal way. This feature can be enabled and
disabled by writing to bit 6 of register 48Hex.
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Register map
Shaded areas in the map are ‘don’t care’ and writing either 0 or 1 will not affect any function of
the device.
Bits labelled ‘Set to 0’ or ‘Set to 1’ must be set as stated during initialisation of the device,
either following power up, or after a power on reset (POR). Failure to correctly set these bits may
result in the device operating in an unexpected way.
Some registers do not appear in this list, for example 07 and 08. These are either not used, or
have test functionality. Do not write to any undefined registers as this may cause the device to
operate in a test mode. If an undefined register has been inadvertently addressed, the device
should be reset to ensure the undefined registers are at default values.
A d d r. P ar am et er N am e
( Hex )
D at a B i t
7 ( m sb )
02
chip _revision
(read only)
03
cnfg_control1
(read/w rite)
04
cnfg_control2
(read/w rite)
05
sts_interrup ts
(read/w rite)
06
sts_op erating_mode
(read only)
0A
sts_p riority_tab le
(read only)
0C
5
4
3
Analog
div sync
Set to '0'
Set to '0'
Phase loss flag limit
SEC2DIFF
1
0 ( l sb )
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '1'
Set to '0'
SEC1DIFF
SEC2
SEC1
Main ref
failed
SEC3
Op erating mode (2:0)
Highest p riority valid source
Currently selected reference source
3rd highest p riority valid source
2nd highest p riority valid source
sts_curr_inc_offset
(read only)
Current increment offset (7:0)
0D
Current increment offset (15:8)
07
0E
2
Chip revision numb er (7:0)
Op erating
mode
09
0B
6
Current increment offset (18:16)
sts_sources_valid
(read only)
SEC2DIFF
SEC1DIFF
SEC2
SEC1
0F
11
SEC3
sts_reference_sources
(read/w rite)
12
status <SEC2>
status <SEC1>
status <SEC2DIFF>
status <SEC1 DIFF>
14
Revision 2.05/Jan 2001 ã2001 Semtech Corp
status <SEC3>
17
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A d d r. P ar am et er N am e
( Hex )
18
19
cnfg_ref_selection_p riority
(read/w rite)
D at a B i t
7 ( m sb )
6
5
4
3
2
1
0 ( l sb )
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
1A
p rogrammed _p riority <SEC2>
p rogrammed _p riority <SEC1>
p rogrammed _p riority <SEC2DIFF>
p rogrammed _p riority <SEC1DIFF>
1B
Set to '0'
Set to '0'
Set to '0'
Set to '0'
1C
Set to '0'
Set to '0'
Set to '0'
Set to '0'
1D
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
1E
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
divn
lock8k
b ucket_id <SEC1> (1:0)
reference_source_frequency <SEC1> (3:0)
divn
lock8k
b ucket_id <SEC2> (1:0)
reference_source_frequency <SEC2> (3:0)
divn
lock8k
b ucket_id
<SEC1DIFF> (1:0)
reference_source_frequency <SEC1DIFF> (3:0)
divn
lock8k
b ucket_id
<SEC2DIFF> (1:0)
reference_source_frequency <SEC2DIFF> (3:0)
divn
lock8k
b ucket_id <SEC3> (1:0)
reference_source_frequency <SEC3> (3:0)
22
cnfg_ref_source_frequency
(read/w rite)
23
24
25
28
32
cnfg_op erating_mode
(read/w rite)
33
cnfg_ref_selection
(read/w rite)
34
cnfg_mode
(read/w rite)
35
cnfg_control3
(read/w rite)
36
cnfg_differential_inp uts
(read/w rite)
38
cnfg_outp ut_enab le
(read/w rite)
39
cnfg_O1_outp ut_frequencies
(read/w rite)
3A
cnfg_differential_outp ut
(read/w rite)
3B
cnfg_b andw idth
(read/w rite)
3C
cnfg_nominal_frequency
(read/w rite)
3D
Set to '0'
Set to '0'
Set to '0'
Set to '0'
p rogrammed _p riority <SEC3>
Forced op erating mode
force_select_reference_source
A u to
external
2k enab le
311.04
MHz on O1
Phase
alarm
timeout
enab le
Clock
edge
Holdover
offset
enab le
Set to '0'
Set to '0'
1=SON ET
0=SDH
for Dig1
Set to '0'
External 2k
Sync enab le
reversion
mode
SON ET/
SDH I/P
SEC2DIFF
PECL
SEC1DIFF
PECL
Set to '0'
O2
Set to '0'
Set to '0'
Set to '0'
Set to '0'
O1 LVDS
enab le
O1 PECL
enab le
Digital 1
O1 frequency selection
Auto b /w
sw itch
acq/lock
Revision 2.05/Jan 2001 ã2001 Semtech Corp
Acquistion b andw idth
Set to '0'
N ormal/locked b andw idth
N ominal frequency (7:0)
N ominal frequency (15:8)
18
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A d d r. P ar am et er N am e
( Hex )
D at a B i t
7 ( m sb )
3E
6
5
cnfg_holdover_offset
(read/w rite)
3
2
1
Holdover offset (15:8)
40
A u to
Holdover
Averaging
Holdover offset (18:16)
cnfg_freq_limit
(read/w rite)
DPLL Frequency offset limit (7:0)
42
43
DPLL Frequency offset
limit (9:8)
cnfg_interrup t_mask
(read/w rite)
44
Set to '0'
Set to '0'
status
SEC2DIFF
status
SEC1DIFF
status
SEC2
status
SEC1
Set to '0'
Set to '0'
Op er. mode
Main ref
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
status
SEC3
Set to '0'
Set to '0'
Set to '0'
Set to '0'
Set to '0'
45
46
0 ( l sb )
Holdover offset (7:0)
3F
41
4
cnfg_freq_divn
(read/w rite)
Divide-inp ut-b y-n ratio (7:0)
47
Divide-inp ut-b y-n ratio (13:8)
48
cnfg_monitors
(read/w rite)
50
cnfg_activ_up p er_threshold 0
(read/w rite)
Configuration 0: Activity alarm set threshold (7:0)
51
cnfg_activ_low er_threshold 0
(read/w rite)
Configuration 0: Activity alarm reset threshold (7:0)
52
cnfg_b ucket_size 0
(read/w rite)
53
cnfg_decay_rate 0
(read/w rite)
54
cnfg_activ_up p er_threshold 1
(read/w rite)
Configuration 1: Activity alarm set threshold (7:0)
55
cnfg_activ_low er_threshold 1
(read/w rite)
Configuration 1: Activity alarm reset threshold (7:0)
56
cnfg_b ucket_size 1
(read/w rite)
57
cnfg_decay_rate 1
(read/w rite)
58
cnfg_activ_up p er_threshold 2
(read/w rite)
Configuration 2: Activity alarm set threshold (7:0)
59
cnfg_activ_low er_threshold 2
(read/w rite)
Configuration 2: Activity alarm reset threshold (7:0)
Revision 2.05/Jan 2001 ã2001 Semtech Corp
Flag ref lost
on TDO
Ultra-fast
sw itching
External
source
sw itch
enab le
Freeze
p hase
b uildout
Phase
b uildout
enab le
Frequency monitors
configuration (1:0)
Configuration 0: Activity alarm b ucket size (7:0)
Configuration 0:
decay_rate (1:0)
Configuration 1: Activity alarm b ucket size (7:0)
Configuration 1:
decay_rate (1:0)
19
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A d d r. P ar am et er N am e
( Hex )
D at a B i t
7 ( m sb )
6
5
4
3
2
5A
cnfg_b ucket_size 2
(read/w rite)
5B
cnfg_decay_rate 2
(read/w rite)
5C
cnfg_activ_up p er_threshold 3
(read/w rite)
Configuration 3: Activity alarm set threshold (7:0)
5D
cnfg_activ_low er_threshold 3
(read/w rite)
Configuration 3: Activity alarm reset threshold (7:0)
5E
cnfg_b ucket_size 3
(read/w rite)
5F
cnfg_decay_rate 3
(read/w rite)
1
0 ( l sb )
Configuration 2: Activity alarm b ucket size (7:0)
Configuration 2:
decay_rate (1:0)
Configuration 3: Activity alarm b ucket size (7:0)
Configuration 3:
decay_rate (1:0)
Register map description
A d d r. P ar am et er N am e
( Hex )
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
02
ch ip _revision
Th is read only register contains th e ch ip revision numb er
00000001
03
cnfg_control1
Bits (3:0) & 5 are test controls and must b e eith er set at '0' d uring initialisation or left
unch anged .
XX000000
Bit 4, w h en set h igh , synch ronises th e d ivid ers in th e outp ut A PLL section to th e d ivid ers in th e
DPLL section such th at th eir p h ases align. Th is is necessary to h ave th e p h ase alignment
b etw een th e inp uts and outp ut clocks at OC3 d erived rates (6.48 MHz to 77.76 MHz). By d efault,
synch ronisation occurs for 2 second s after p ow er up and is th en turned off. Setting th is b it h igh
keep s synch ronisation on, w h ich may b e necessary to avoid th e d ivid ers getting out of sync w h en
q uick ch anges in freq uency occur such as a force into freerun mod e.
04
cnfg_control2
Bits (2:0) are test controls and must b e set at '010' d uring initialisation or left unch anged .
XX100010
Bits (5:3) d efine th e p h ase loss flag limit. By d efault set to 4 (100) w h ich corresp ond s to
ap p roximately 140°. A low er value sets a corresp ond ing low er p h ase limit. Th e flag limit
d etermines th e value at w h ich th e DPLL ind icates p h ase lost as a result of inp ut jitter, a p h ase
jump , or a freq uency jump on th e inp ut
sts_interrup ts
Th is 16 b it register contains one b it for each b it of sts_sources_valid , one for loss of reference th e
d evice w as locked to, and anoth er for th e op erating mod e. A ll b its are active h igh .
A ll b its excep t th e 'main ref failed ' b it (b it 14) are set on a "ch ange" in th e state of th e relevent
status b it, i.e. if a source b ecomes valid , or goes invalid it w ill trigger an interrup t. If th e
Op erating Mod e (register 9) ch anges state th e interrup t w ill b e generated .
Bit 14 (main ref failed ) of th e interrup t status register is used to flag inactivity on th e reference
th at th e d evice is locked to much more q uickly th an th e activity monitors can sup p or t. If b it 6 of
th e cnfg_monitors register (register 48) (flag ref loss on TDO) is set, th en th e state of th is b it is
d riven onto th e TDO p in of th e d evice.
A ll b its are maskab le b y th e b its in th e cnfg_interrup t_mask register. Each b it may b e cleared
ind ivid ually b y w riting a '1' to th at b it, th us resetting th e interrup t. A ny numb er of b its can b e
cleared w ith a single w rite op eration. Writing '0's w ill h ave no effect.
05
Bits (7:6) unused
Least significant b yte (5:2)
Bits (1:0) unused .
XX0000XX
06
Most significant b yte (7:6) and 0
Bits (5:1) unused
00XXXXX0
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A d d r. P ar am e t e r N am e
( Hex )
09
sts_op erating_mode
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
Th is read -only register h old s th e current op erating state of th e main state mach ine. Figure 7 sh ow
h ow th e values of th e 'op erating state' variab le match w ith th e ind ivid ual states.
B it
Content
2:0
Op erating state (2:0)
Bits (2:0) State
001
freerun
010
h old over
100
locked
110
p re-locked
101
p re-locked 2
111
p h ase lost
XXXXX001
3:7
sts_p riority_tab le
unused
Th is is a 16-b it read -only register, taking tw o ad d resses.
Currently-selected reference source: th is is th e ch annel numb er of th e inp ut reference source
w h ich is currently connected to th e SETG function.
High est-p riority valid source: th is is th e ch annel numb er of th e inp ut reference source w h ich is
valid and h as th e h igh est p riority; it may not b e th e same as th e currently-selected reference
source (d ue to failure h istory or ch anges in p rogrammed p riority).
Second -h igh est p riority valid source: th is is th e ch annel numb er of th e inp ut reference source
w h ich is valid and h as th e next-h igh est p riority to th e h igh est-p riority valid source.
Th ird -h igh est p riority valid source: th is is th e ch annel numb er of th e inp ut reference source w h ich
is valid and h as th e next-h igh est p riority to th e second -h igh est-p riority valid source.
N ote th at th ese registers are up d ated b y th e state mach ine in resp onse to th e contents of th e
cnfg_ref_selection_p riority register and th e ongoing status of ind ivid ual ch annels; ch annel
numb er '0000', ap p earing in any of th ese registers, ind icates th at no ch annel is availab le for th at
p riority.
B it
Content
0A
(7:4)
(3:0)
High est-p riority valid source
Currently selected reference source
00000000
0B
(7:4)
(3:0)
3rd-h igh est-p riority valid source
2nd-h igh est-p riority valid source
00000000
sts_curr_inc_offset
Th is read -only register contains a signed -integer value rep resenting th e 19 significant b its of th e
current increment offset of th e d igital PLL. Th e register may b e read p eriod ically to b uild up a
h istorical d atab ase for later use d uring h old over p eriod s (th is w ould only b e necessary if an
external oscillator w h ich d id not meet th e stab ility criteria d escrib ed in Local Oscillator Clock
section is used ). Th e register w ill read 00000000 immed iately after reset.
0C
Least significant b yte of offset value
00000000
0D
N ext significant b yte of offset value
00000000
07
0E
sts_sources_valid
Bits (2:0) 3 most significant b its of offset value, b its (7:4) unused
XXXXX000
Th is 8 b it register contains cop ies of b it 3 from all th e status_reference_sources b ytes. Th is allow s
th e user to get th e ‘valid ity’ of all sources in just 2 read s.
00000000
0F
XX000000
Th is register only ind icates w h eth er or not a source h as p assed all criteria.
sts_reference_sources
Th is is a 5-b yte register w h ich h old s th e status of each of th e 8 inp ut reference sources. Th e
status of each reference source is sh ow n in a 4-b it field . Each b it is active h igh .To aid status
ch ecking, a cop y of each status b it 3 is p rovid ed in th e sts_sources_valid register. Th e status is
rep or ted as follow s: (Each b it may b e cleared ind ivid ually)
Status b it
Status b it
Status b it
Status b it
0 = p h ase lock alarm
1 = no activity alarm
2 = out-of-b and alarm
3 = Source valid (no alarms) (b it 3 is comb ination of b its 0-2)
11
(3:0)
(7:4)
Status of inp ut reference source SEC1
Status of inp ut reference source SEC2
12
(3:0)
(7:4)
Status of inp ut reference source SEC1DIFF
Status of inp ut reference source SEC2DIFF
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01100110
01100110
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A d d r. P ar am e t e r N am e
( Hex )
14
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
sts_reference_sources
(3:0)
(7:4)
Status of inp ut reference source SEC3
Unused
cnfg_ref_selection_p riority
Th is is a 7-b y te register w h ich h old s th e p riority of each of th e 3 inp ut reference sources. Th e
p riority values are all relative to each oth er, w ith low er-valued numb ers taking h igh er p riorities.
Only th e values 1 to 15(d ec) are valid - '0' d isab les th e reference source. Each reference source
must b e given a uniq ue p riority.
XXXX0110
It is recommend ed to reserve th e p riority value '1' as th is is used w h en forcing reference selection
via th e cnfg_ref_selection register. If th e user d oes not intend to use th e cnfg_ref_selection
register th en p riority value '1' need not b e reserved .
B it
Content
18
(7:0)
Must b e set to 00000000 d uring initialisation
00110010
19
(3:0)
(7:4)
Programmed p riority of inp ut reference source SEC1
Programmed p riority of inp ut reference source SEC2
01010100
1A
(3:0)
(7:4)
Programmed p riority of inp ut reference source SEC1DIFF
Programmed p riority of inp ut reference source SEC2DIFF
01110110
1B
(7:0)
Must b e set to 00000000 d uring initialisation
10011000
1C
(3:0)
(7:4)
Programmed p riority of inp ut reference source SEC3
Must b e set to 0000 d uring initialisation
10111010
1D
(7:0)
Must b e set to 00000000 d uring initialisation
11010001
1E
(7:0)
Must b e set to 00000000 d uring initialisation
11111110
cnfg_ref_source_freq uency
Th is is a 5-b y te register w h ich h old s th e key s to th e freq uencies of each of th e 5 inp ut reference
sources, as listed b elow.
Bits (3:0) d efine th e freq uency of th e reference source in accord ance w ith th e follow ing key :
Value (3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Freq uency
8 kHz
1544 kHz(SON ET)/2048 kHz(SDH) (A s d efined b y Register 34, b it 2)
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
2 kHz
4 kHz
Bits (5:4) togeth er d efine w h ich leaky b ucket settings (0-3) are used , as d efined in registers 50
(h ex)to 5F (h ex).
Bits (7:6) of each b y te d efine th e op eration und er taken on th e inp ut freq uency, in accord ance
w ith th e follow ing key :
00
01
10
11
Th e inp ut freq uency is fed d irectly into th e DPLL
Th e inp ut freq uency is internally d ivid ed d ow n to 8 kHz, b efore b eing fed into th e
DPLL. Th is gives excellent jitter tolerance.
Unsup p or ted configuration - d o not use
Uses th e d ivision coefficient stored in register cnfg_freq _d ivn to d ivid e th e inp ut b y
th is value p rior to going to th e DPLL. Th e freq uency monitors must b e d isab led . Th e
d ivid ed d ow n freq uency sh ould eq ual 8 kHz. Th e freq uency (3:0) sh ould b e set to
th e nearest sp ot freq uency just b elow th e actual inp ut freq uency. Th e DivN feature
w orks for inp ut freq uencies b etw een 1.544 MHz and 100 MHz.
22
Freq uency of reference source SEC1
00000000
23
Freq uency of reference source SEC2
00000000
24
Freq uency of reference source SEC1DIFF
00000011
25
Freq uency of reference source SEC2DIFF
00000011
28
Freq uency of reference source SEC3
00000011
32
cnfg_op erating_mod e
Th is 3-b it register is used to force th e d evice into a d esired op erating state, rep resented b y th e
b inary values sh ow n in Figure 8. Value 0 (h ex) allow s th e control state mach ine to op erate
automatically.
B it
(2:0)
(7:3)
Reference source
Desired op erating state (as p er Figure 8)
Unused
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A d d r. P ar am et er N am e
( Hex )
33
cnfg_ref_selection
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
This 4-b it register occup ies the entire 8-b it sp ace at address 33(hex). It is used to force the
device to select a p ar ticular inp ut reference source, irresp ective of its p riority. Writing to this
register temp orarily raises the selected inp ut to p riority '1'. Provided no other inp ut is already
p rogrammed w ith p riority '1', and rever tive mode is on, this source w ill b e selected, if it has
b een validated b y the frequency and activity monitors.
Bit (3:0) define the source that is selected in accordance w ith the follow ing key. Bits (7:4) are
unused. Writing X0(hex) or XF(hex) w ill disab le all inp ut reference sources. * The default is XF.
34
cnfg_mode
Value (3:0)
Selected source
0011
0100
0101
0110
1001
SEC1
SEC2
SEC1DIFF
SEC2DIFF
SEC3
XXXX1111*
This 6-b it register occup ies the address 34(hex). It contains several individual configuration
fields, as detailed b elow :
B it 0
= 0 N on-rever tive Mode: The device w ill retain the p resently selected source. This is the default
state.
= 1 Rever tive Mode: The device w ill sw itch to the highest p riority source show n in
sts_p riority_tab le register(7:4) (at address 0A(hex)).
Bits 1 is unused.
B it 2
=0 SDH mode: The device exp ects the inp ut frequency of any inp ut channel given the value
'0001' in the cnfg_ref_source_frequency register to b e 2048 kHz. This b it is w riteab le.
=1 SON ET mode: The device exp ects the inp ut frequency of any inp ut channel given the value
'0001' in the cnfg_ref_source_frequency register to b e 1544 kHz. This b it is w riteab le.
B it 3
=0 External 2 kHz Sync Disab le. The device w ill ignore the Sync2k p in.
=1 External 2 kHz Sync Enab le. The device w ill align the p hase of its internally generated
Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) w ith that of the signal sup p lied
to the Sync2k p in. The device should b e locked to a 6.48 MHz outp ut from an ACS8510. This is
the default state.
B it 4
=0 Holdover offset disab le: The device w ill ignore the value and holdover w ill use the current
PLL integral p ath value. This is the default state.
=1 Holdover offset enab le: The device w ill adop t the Holdover offset value stored in the
cngf_holdover_offset register. This value is then used to set the frequency in holdover mode.
11001000
B it 5
=0 Falling Clock Edge selected: The device w ill reference to the falling edge of the external
oscillator signal. This is the default state.
=1 Rising Clock Edge selected: The device w ill reference to the rising edge of the external
oscillator signal.
B it 6
=0 Phase Alarm Timeout disab le: The p hase alarm w ill not timeout and must b e reset b y
softw are.
=1 Phase Alarm Timeout enab le: The p hase alarm w ill timeout after 100 seconds. This is the
default state.
B it 7
=0 Auto 2 kHz Sync Disab le. The user controls this function using b it 3 of this register, as
describ ed ab ove.
=1 Auto 2 kHz Sync Enab le. External 2 kHz Sync w ill b e enab led only w hen the source is locked
to 6.38 MHz. Otherw ise it w ill b e disab led. This is the default state.
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A d d r. P ar am e t e r N am e
( Hex )
36
cnfg_d ifferential_inp uts
D e scr i p t i o n
Th is 2-b it register occup ies th e entire 8-b it sp ace at ad d ress 36(h ex). It contains tw o ind ivid ual
configuration field s, as d etailed b elow :
B it
0
1
(7:2)
38
cnfg_outp ut_enab le
D e f au l t
Val u e ( b i n )
Configuration field
'1' = Inp ut SEC1DIFF is PECL-comp atib le
'0' = Inp ut SEC1DIFF is LV DS-comp atib le (Default)
'1' = Inp ut SEC2DIFF is PECL-comp atib le (Default)
'0' = Inp ut SEC2DIFF is LV DS-comp atib le
Unused
XXXXXX10
Th is 8-b it register occup ies th e entire 8-b it sp ace at ad d ress 38(h ex). It contains several
ind ivid ual configuration field s, as d etailed b elow :
B it
Configuration field
0, 1, 3, 4, 6 are unused , and sh ould b e set to '0'
2
'1' = Outp ut p or t O2 enab led
'0' = Outp ut p or t O2 d isab led
5
'1' = Sonet mod e selected for Dig1
'0' = SDH mod e selected for Dig1
7
'1' = O1 outp ut freq uency set to 311.04 MHz
'0' = O1 outp ut freq uency set b y A d d ress 3A (5:4)
00011111
N ote: "Disab led " means th at th e outp ut p or t h old s a static logic value (th e p or t is not Tri-stated ).
39
cnfg_01_outp ut_freq uencies
Th is register h old s th e freq uency selections for th e 01 outp ut p or t, as d etailed b elow.
B it
Configuration field
(0:3) and (6:7) are unused
(5:4)
00
01
10
11
* = d efault
Dig1 freq uency
1544 kHz/2048 kHz*
3088 kHz/4096 kHz
6176 kHz/8192 kHz
12352 kHz/16384 kHz
00001000
For Dig1 th e left most freq uency values are for Sonet mod e and th e oth ers are for SDH mod e.
Th ey are selected via th e SON ET/SDH b its in register cnfg_outp ut_enab le.
3A
cnfg_d ifferential_outp uts
Th is register h old s th e freq uency selections and th e p or t-tech nology typ e for th e d ifferential
outp ut O1, as d etailed b elow. Bits 7, 6, 3 and 2 are unused .
B it
(1:0)
00
01
10
11
3B
cnfg_b and w id th
Configuration field
B it
PECL/LV DS
(5:4)
Por t d isab led
00
PECL-comp atib le
01
LV DS-comp atib le (d efault) 10
unused
11
Configuration field
O1 freq uency
38.88 MHz (d efault)
19.44 MHz
155.52 MHz
Dig1.
XX00XX10
Th is register contains information used to control th e op eration of th e d igital PLL. Wh en
b and w id th selection is set to automatic, th e DPLL w ill use th e acq uisition b and w id th setting
w h en out of lock, and th e normal/locked b and w id th setting w h en in lock. Wh en set to manual,
th e DPLL w ill alw ay use th e normal/locked b and w id th setting.
Bit (2:0)
000
001
010
011
100
101
110
111
3
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Loop b and w id th
0.1 Hz
0.3 Hz
0.6 Hz
1.2 Hz
2.5 Hz
5.0 Hz
10 Hz
20 Hz
unused
(6:4)
000
001
010
011
100
101
110
111
7
24
A cq uisition b and w id th
0.1 Hz
0.3 Hz
0.6 Hz
1.2 Hz
2.5 Hz
5.0 Hz
10 Hz
20 Hz
Band w id th selection
'0'= Manual op eration
'1'= A utomatic op eration
0111X101
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A d d r. P ar am et er N am e
( Hex )
cnfg_nominal_frequency
3C
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
This register holds a 16 b it unsigned integer rep resenting the desired nominal frequency. This
is availab le to op tionally calib rate the nominal outp ut frequency to comp ensate against
variation in the external crystal frequencies.
10011001
Least significant b yte.
3D
10011001
Most significant b yte.
cnfg_holdover_offset
3E
This 19-b it register uses addresses 3E(hex) to 40(hex). It holds a 19 b it signed integer,
rep resenting the holdover offset value, w hich can b e used to set the holdover mode frequency
w hen enab led via the holdover offset enab led b it in the cnfg_mode register.
00000000
Least significant b yte.
3F
00000000
N ext significant b yte
40
Most significant b its.
Bit 7 is Auto Holdover Averaging enab le - default 1. This enab les the frequency average to b e
taken from 32 samp les. One samp le taken every 32 seconds, after the frequency has b een
confirmed to b e in-b and b y the frequency monitors, giving a 17 minute history of the currently
locked to reference source for use in Holdover.
cnfg_freq_limit
1XXXX000
This register holds a 10 b it unsigned integer rep resenting the p ull-in range of the DPLL. It
should b e set according to the accuracy of crystal imp lemented in the ap p lication, using the
follow ing formula;
Frequency range +/- (p p m) = (cnfg_freq_limit x 0.0785)+0.01647 or
cnfg_freq_limit = (Frequency range - 0.01647) / 0.0785
Default value w hen SRCSW is left unconnected or tied low is ±9.2 p p m. Default value w hen
SRCSW is high is the full range of around ±80 p p m.
41
01110110
(SRCSW low )
11111111
(SRCSW high)
Least significant b yte
42
43
(7:2) unused
(1:0) Most significant b its
cnfg_interrup t_mask
XXXXXX00
(SRCSW low )
XXXXXX11
(SRCSW high)
Each b it of this 21 b it register, if set to zero, w ill disab le the ap p rop riate interrup t source in the
interrup t status register.
44
11111111
11111111
45
XXX11111
cnfg_freq_divn
This 15 b it integer is used as the divisor for any inp ut to get the p hase locking frequency
desired. Only active for inp uts w ith the divn b it set to ‘1’. This w ill cause the inp ut frequency
to b e divided b y (n+1) p rior to p hase comp arison.
The reference_source_frequency b its should reflect the source frequency after the division b y
(n+1).
46
47
least-significant b yte.
00000000
most-significant b its.
XX000000
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A d d r. P ar am et er N am e
( Hex )
48
cnfg_monitors
D e scr i p t i o n
D e f au l t
Val u e ( b i n )
This 7 b it register allow s glob al configuration of monitors and control of p hase b uild out.
Bits (1:0) are for configuring frequency monitors- 00 = off, 01 = 15p p m, others are reserved for
future use.
Bit 2 Phase b uildout en enab les p haseb uildout. If disab led, the DPLL w ill alw ays lock to 0
degrees.
Bit 3 Freeze p hase b uildout (w hen p hase b uildout is enab led) w ill effectively disab le any future
p hase b uildout events b ut remain w ith the current p hase offset.
Bit 4 External p rotection sw itching enab les the SrcSw it p in to force the locking to either inp ut 4
or 3.
X0000101*
Bit 5 Ultra-fast sw itching enab les the dp ll to raise an inactivity alarm on the currently selected
source after missing only a few cycles. This w ill enab le very fast sw itching aw ay from the
selected source in a p rotection typ e ap p lication. This is triggered b y the main_ref_failed
interrup t mechanism.
Bit 6 Flag reference loss on TDO w ill enab le the value of the main_ref_failed interrup t to b e
driven out of the TDO p in of the device.
* The default value given is valid w hen SRCSWT p in is left unconnected or tied low. If SRCSWT
is tied high, the default value is 15 (hex).
50
cnfg_activ_up p er_threshold 0 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised.
00000110
51
cnfg_activ_low er_threshold 0 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared.
00000100
52
cnfg_b ucket_size 0
This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive
i n p u t.
00001000
53
cnfg_decay_rate 0
This 2 b it register controls the leak rate of the leaky b ucket. The fill-rate of the b ucket is +1 for
every 128ms interval that has exp erienced some level of inactivity. The decay rate is
p rogrammab le in ratios of the fill rate. The ratio can b e set to 1:1, 2:1, 4:1, 8:1 b y using values
of 00, 01, 10, 11 resp ectively. How ever, these b uckets are not ‘true’ leaky b uckets in nature.
The b ucket stop s ‘leaking’ w hen it is b eing filled. This means that the fill and decay rates can
b e the same (00 = 1:1) w ith the net effect that an active inp ut can b e recognised at the same
rate as an inactive one.
XXXXXX01
54
cnfg_activ_up p er_threshold 1 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised.
00000110
55
cnfg_activ_low er_threshold 1 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared.
00000100
56
cnfg_b ucket_size 1
This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive
i n p u t.
As for register 53(hex) b ut for b ucket 1.
00001000
57
cnfg_decay_rate 1
58
cnfg_activ_up p er_threshold 2 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised.
00000110
59
cnfg_activ_low er_threshold 2 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared.
00000100
5A
cnfg_b ucket_size 2
This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive
i n p u t.
5B
cnfg_decay_rate 2
As for register 53(hex) b ut for b ucket 2.
5C
cnfg_activ_up p er_threshold 3 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised.
00000110
5D
cnfg_activ_low er_threshold 3 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared.
00000100
5E
cnfg_b ucket_size 3
This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive
i n p u t.
00001000
5F
cnfg_decay_rate 3
As for register 53(hex) b ut for b ucket 3.
XXXXXX01
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26
XXXXXX01
00001000
XXXXXX01
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Selection
Source
of
Input
Reference
Clock
Under normal operation, the input reference
sources are selected automatically by an order
of priority, where SEC1 is the highest priority,
SEC2 is the second highest priority and SEC3
is the lowest priority. The priorities can be reassigned with external software. The SEC1
reference source has inputs via either a low
speed TTL input port or a high speed PECL/
LVDS input port. Similarly, the SEC2 reference
source has both a low speed TTL or a high
speed PECL/LVDS input port. The SEC3
(standby) reference source only has provision
via a low speed TTL input port. There is provision
for one sync clock input via a TTL port. Whilst
SEC1, SEC2 and SEC3 reference source inputs
can all be active at the same time, only one of
the TTL or PECL/LVDS input ports for the SEC1
and SEC2 reference sources may be used at
any time, the inactive port is ignored, by setting
the priority of that port to zero.
Restoration of repaired reference sources is
handled carefully to avoid inadvertent
disturbance of the output clock. The ACS8515
has two modes of operation; Revertive and nonRevertive. In Revertive mode, if a re-validated
(or newly validated) source has a higher priority
than the reference source which is currently
selected, a switch over will take place. Many
applications prefer to minimise the clock
switching events and choose Non-Revertive
mode. In Non-Revertive mode , when a revalidated (or newly validated) source has a
higher priority then the selected source will be
maintained. The re-validation of the reference
source will be flagged in the sts_sources_valid
register and, if not masked, will generate an
interrupt. Selection of the re-validated source
can only take place under software control the software should briefly enable Revertive
mode to affect a switch-over to the higher
priority source. If the selected source fails under
these conditions the device will still not select
Revision 2.05/Jan 2001 ã2001 Semtech Corp
27
the higher priority source until instructed to do
so by the software, by briefly setting the
Revertive mode bit. When there is a reference
available with higher priority than the selected
reference, there will be NO change of reference
source as long as the Non-Revertive mode
remains on. This is the case even of there are
lower priority references available or the
currently selected reference fails. When the
ONLY valid reference sources that are available
have a lower priority than the selected
reference, a failure of the selected reference
will always trigger a switch-over regardless of
whether Revertive or Non-revertive mode has
been chosen.
Automatic Control Selection
When automatic selection is required, the
'cnfg_ref_selection' registers must be set to allzero.
The
configuration
registers,
'cnfg_ref_selection_priority', held in the µP port
are organised as 5, 4-bit registers with each
representing an input reference port. Unused
ports should be given the value, '0000' in the
relevant register to indicate they are not to be
included in the priority table. On power-up, or
following a reset, the whole of the configuration
file will be defaulted to the values defined by
Table 1. The selection priority values are all
relative to each other, with lower-valued
numbers taking higher priorities. Each reference
source should be given a unique number, the
valid values are 1 to 15(dec). A value of 0
disables the reference source. However if two
or more inputs are given the same priority
number those inputs will be selected on a first
in, first out basis. If the first of two same priority
number sources goes invalid the second will be
switched in. If the first then becomes valid
again, it becomes the second source on the
first in, first out basis, and there will not be a
switch. If a third source with the same priority
number as the other two becomes valid, it joins
the priority list on the same first in, first out
basis. There is no implied priority based on the
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channel numbers.
Activity Monitoring
The ACS8515 has a combined inactivity and
irregularity monitor. The ACS8515 uses a "leaky
bucket" accumulator, which is a digital circuit
which mimics the operation of an analog
integrator, in which input pulses increase the
output amplitude but die away over time. Such
integrators are used when alarms have to be
triggered either by fairly regular defect events,
which occur sufficiently close together, or by
defect events which occur in bursts. Events
which are sufficiently spread out should not
trigger the alarm. By controlling the alarmsetting threshold, the point at which the alarm
is triggered can be controlled. The point at which
the alarm is cleared depends upon the decay
rate and the alarm-clearing threshold. On the
alarm-setting side, if several events occur close
together, each event adds to the amplitude
and the alarm will be triggered quickly; if events
occur a little more spread out, but still
sufficiently close together to overcome the
decay, the alarm will be triggered eventually. If
events occur at a rate which is not sufficient to
overcome the decay, the alarm will not be
triggered. On the alarm-clearing side, if no defect
events occur for a sufficient time, the amplitude
will decay gradually and the alarm will be cleared
when the amplitude falls below the alarmclearing threshold. The ability to decay the
amplitude over time allows the importance of
defect events to be reduced as time passes
by. This means that, in the case of isolated
events, the alarm will not be set, whereas, once
the alarm becomes set, it will be held on until
normal operation has persisted for a suitable
time (but if the operation is still erratic, the
alarm will remain set).
The "leaky bucket" accumulators are
programmable for size, alarm set & reset
thresholds and decay rate. Each source is
monitored over a 128 ms period. If, within a
128 ms period, an irregularity occurs that is
not deemed to be due to allowable jitter/wander,
then the accumulator is incremented. The
accumulator will continue to increment up to
the point that it reaches the programmed
bucket size. The "fill rate" of the leaky bucket
is, therefore, 8 units/second. The "leak rate"
inactivities/irregularities
reference
source
bucket_size
leaky bucket
response
upper_threshold
lower_threshold
programmable fall slopes
(all programmable)
alarm
Figure 7: Inactivity and irregularity monitoring
Revision 2.05/Jan 2001 ã2001 Semtech Corp
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ACS8515 LC/P
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of the leaky bucket is programmable to be in
multiples of the fill rate (x1, x0.5, x0.25 and
x0.125) to give a programmable leak rate from
8 units/sec down to 1 unit/sec. A conflict
between trying to ‘leak’ at the same time as a
‘fill’ is avoided by preventing a ‘leak’ when a
‘fill’ event occurs.
Disqualification of a non-selected reference
source is based on inactivity, or on an out of
band result from the frequency monitors. The
currently selected reference source can be
disqualified for phase, frequency, inactivity or if
the source is outside the DPLL lock range. If
the currently selected reference source is
disqualified, the next highest priority, active
reference source is selected.
Restoration of repaired reference sources is
handled carefully to aviod inadvertant disruption
of the output clock. The ACS8515 operates in
a Non-revertive mode by default. In this mode,
if the restored reference source has a higher
priority than the reference source which is
currently selected, a switch-over to the restored
source will not tale place automatically. A
restored reference source will assume its
correct place in the priority table but a switchover will only take place automatically upon
failure of the currently selected source. It is
possible to invoke a switch-over by external
control or by enabling revertive mode.
Ultra Fast Switching
A reference source is normally disqualified after
the leaky bucket monitor thresholds have been
crossed. An option for a faster disqualification
has been implemented, whereby if register 48H,
bit 5 (Ultra Fast Switching), is set then a loss of
activity of just a few reference clock cycles will
set the ‘no activity alarm’ and cause a
reference switch. This can be chosen to cause
an interrupt to occur instead of or as well as
causing the reference switch.
Leaky bucket timing
The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky
bucket empty) will be:
(cnfg_activ_upper_threshold N)
secs
8
where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then
this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is
0.75 s.
The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated
as:
(cnfg_decay_rate N)
2
x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N))
secs
8
where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown
in the following:
1
2
x (8-4)
= 1.0 s
8
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External Protection Switching
Free-Run mode
Fast external switching between inputs SEC1
and SEC2 can also be triggered directly from a
dedicated pin (SRCSW). This mode can be
activated either by holding this pin high during
reset, or by writing to bit 4 of register address
48Hex.
The Free-Run mode is typically used following a
power-on-reset or a device reset before
network synchronisation has been achieved. In
the Free-Run mode, the timing and
synchronisation signals generated from the
ACS8515 are based on the Master clock
frequency provided from the external oscillator
and are not synchronised to an input reference
source. The frequency of the output clock is a
fixed multiple of the frequency of the external
oscillator, and the accuracy of the output clock
is equal to the accuracy of the Master clock.
Once external protection switching is enabled,
then the value of this pin directly selects either
SEC1 (SRCSW high) or SEC2 (SRCSW low). If
this mode is activated at reset by pulling the
SRCSW pin high, then it configures the default
frequency tolerance of SEC1 and SEC2 to +/80 ppm (register address 41Hex and 42Hex).
Any of these registers can be subsequently set
by external s/w if required.
The transition from Free-Run to Pre-locked(1)
occurs when the ACS8515 selects a reference
source.
When external protection switching is enabled,
the device will operate as a simple switch. All
clock monitoring is disabled and the DPLL will
simply be forced to try to lock on to the
indicated reference source. The operating state
(sts_operating_mode register) will always
indicate ‘locked’ in the mode.
Pre-Locked(1) mode
Modes of Operation
Locked mode
The ACS8515 has three primary modes of
operation (Free-Run, Locked and Holdover)
supported by three secondary, temporary
modes (Pre-Locked, Lost_Phase and PreLocked2). These are shown in the State
Transition Diagram, Figure 6.
The Locked mode is used when an input
reference source has been selected and the
PLL has had time to lock. When the Locked
mode is achieved, the output signal is in phase
and locked to the selected input reference
source. The selected input reference source is
determined by the priority table. When the
ACS8515 is in Locked mode, the output
frequency and phase follows that of the
selected input reference source. Variations of
the external crystal frequency have a minimal
effect on the output frequency. Only the
minimum to maximum frequency range is
affected. Note that the term, 'in phase', is not
applied in the conventional sense when the
ACS8515 is used as a frequency translator (e.g.,
when the input frequency is 2.048 MHz and
The ACS8515 can operate in Forced or
Automatic control. On reset, the ACS8515
reverts to Automatic Control, where transitions
between states are controlled completely
automatically. Forced Control can be invoked
by configuration, allowing transitions to be
performed under external control. This is not
the normal mode of operation, but is provided
for special occasions such as testing, or where
a high degree of hands-on control is required.
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The ACS8515 will enter the Locked state in a
maximum of 100 seconds, as defined by GR1244-CORE specification, if the selected
reference source is of good quality. If the device
cannot achieve lock within 100 seconds, it
reverts to Free-Run mode and another
reference source is selected.
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the output frequency is 19.44 MHz) as the input
and output cycles will be constantly moving past
each other; however, this variation will itself be
cyclical over time unless the input and output
are not locked.
Lost_Phase mode
Lost_Phase mode is used whenever the
selected reference source suffers most kinds
of anomalous behaviour. Clock generation is
performed in the same way as in the Holdover
mode. If the leaky bucket accumulator
calculates that the anomaly is serious, the
device rejects the reference source and one of
the following transitions takes place:
Go to Pre-Locked(2);
- If a known-good standby source is available.
Go to Holdover;
- If no standby sources are available.
Holdover mode
The Holdover mode is used when the circuit
was in Locked mode but the selected reference
source has become unavailable and a
replacement has not yet been selected.
The Holdover performance is mainly limited by
what is happening to the TCXO. The ACS8515
has 3 ways of determining Holdover, either;
1. By external frequency setting (cnfg_holdover_offset
register)
due to temperature fluctuations in the room,
then the instantaneous value can be different
from the average value, and then it may be
possible to exceed the 0.05 ppm limit
(depending on how extreme the temperature
fluctuations are). It is advantageous to shield
the TCXO to slow down frequency changes due
to drift and external temperature fluctuations.
In Holdover mode, the ACS8515 provides the
timing and synchronisation signals to maintain
the Network Element (NE), but they are not
phase locked to any input reference source.
The timing is based on a stored value of the
frequency ratio obtained during the last Locked
mode period.
The frequency accuracy of Holdover mode has
to meet the ITU-T, ETSI and Telcordia
performance requirements. The performance
of the external oscillator clock is critical in this
mode, although only the frequency stability is
important - the stability of the output clock in
Holdover is directly related to the stability of
the external oscillator.
Pre-Locked(2) mode
This state is very similar to the Pre-Locked(1)
state. It is entered from the Holdover state
when a reference source has been selected
and applied to the phase locked loop. It is also
entered if the device is operating in revertive
mode and a higher-priority reference source is
restored.
2. By an internal frequency measuring and averaging
system which averages the last 20 minutes
PORB
3. By just using the last frequency (as reported by the
sts_curr_inc_offset register). This value can be read
out of the device and used to build up a longer term
average using an external averaging circuit. This value
can then to readback into the device and used as the
Holdover offset (via cnfg_holdover_offset register).
The Power On Reset (PORB) pin resets the
device if forced Low for a power-on-reset to be
initiated. The reset is asynchronous, the
minimum Low pulse width is 5 ns. Reset is
needed to initialize all of the register values to
their defaults. Asserting Reset (POR) is required
at power on, and may be re-asserted at any
time to restore defaults. This is implemented
By default it uses the internal averager. This
means that if the TCXO frequency is varying
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most simplistically by an external capacitor to
GND along with the internal pull-up resistor.
The ACS8510 is held in a reset state for 250
(1)Reset
ms after the PORB pin has been pulled High. In
normal operation PORB should be held High.
free-run
select ref
(state 001)
(2) all refs evaluated
&
at least one ref valid
(3) no valid standby ref
&
(main ref invalid
or out of lock >100s)
Reference sources are flagged as ’valid’ when
active, ’in-band’ and have no phase alarm set.
(4) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
pre-locked
w ait for up to 100s
(state 110)
(5) selected ref
phase locked
All sources are continuously checked for
activity and frequency.
Only the main source is checked for phase.
A phase lock alarm is only raised on a
reference when that reference has lost phase
whilst being used as the main reference. The
micro-processor can reset the phase lock
alarm.
A source is considered to have phase locked
when it has been continuously in phase lock
for between 1 and 2 seconds
locked
keep ref
(state 100)
(10) selected source phase
locked
(9) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) ]
pre-locked2
w ait for up to 100s
(state 101)
(12) valid standby ref
&
(main ref invalid
or out of lock >100s)
(8) phase
regained within
100s
(6) no valid standby ref
&
main ref invalid
(7) phase lost
on main ref
Lost phase
w ait for up to 100s
(state 111)
(11) no valid standby ref
&
(main ref invalid
or out of lock >100s)
holdover
select ref
(state 010)
(13) no valid standby ref
&
(main ref invalid
or out of lock >100s)
(15) valid standby ref
&
[ main ref invalid or
(higher-priority ref valid
& in revertive mode) or
out of lock >100s]
(14) all refs evaluated
&
at least one ref valid
Figure 8: Automatic Mode Control State Diagram.
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Electrical Specification
Important Note: The "Absolute Maximum Ratings" are stress ratings only, and functional operation
of the device at conditions other than those indicated in the "Operating Conditions" sections of
this specification are not implied. Exposure to the absolute maximum ratings for an extended
period may reduce the reliability or useful lifetime of the product.
ABSOLUTE MAXIMUM RATINGS
PA RA MET ER
SYM B OL
MIN
MA X
U N IT S
Sup p ly Voltage
V DD, V D+, V A1+,V A2+
V DD
-0.5
3.6
V
Inp ut Voltage
(non-sup p ly p ins)
V in
-
5.5
V
Outp ut Voltage
(non-sup p ly p ins)
Vout
-
5.5
V
TA
-40
85
°C
Tstor
-50
150
°C
A mb ient Op erating Temp erature
Range
Storage Temp erature
OPERATING CONDITIONS
PA RA MET ER
SYM B OL
MIN
T YP
MA X
U N IT S
Pow er Sup p ly (d c voltage)
V DD, V D+,VA 1+, VA 2+, V DD_DIFF
V DD
3.0
3.3
3.6
V
Pow er Sup p ly (d c voltage)
V DD5
V DD5
3.0
3.3/5.0
5.5
V
TA
-40
-
85
°C
Typ ical - one 19 MHz outp ut
Maximum - 190 mA b efore s/w
initialisation, 150 mA after s/w intialisation
IDD
-
110
190/150
mA
Total p ow er d issip ation
PTOT
-
360
685
mW
A mb ient temp erature Range
Sup p ly current
DC CHARACTERISTICS: TTL Input pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Inp ut current
Ii n
-
-
10
µA
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ACS8515 LC/P
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DC CHARACTERISTICS: TTL Input pad with internal pull-up.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Pull-up resistor
PU
30
-
80
kW
Inp ut current
Ii n
-
-
120
µA
DC CHARACTERISTICS: TTL Input pad with internal pull-down.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V in High
V ih
2.0
-
-
V
Vin Low
V il
-
-
0.8
V
Pull-ud ow n resistor
PD
30
-
80
kW
Inp ut current
Ii n
-
-
120
µA
DC CHARACTERISTICS: TTL Output pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
Vout Low
Iol = 4mA
Vol
0
-
0.4
V
Vout High
Ioh = 4mA
Voh
2.4
-
Drive current
ID
-
-
Revision 2.05/Jan 2001 ã2001 Semtech Corp
34
V
4
mA
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ACS8515 LC/P
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DC CHARACTERISTICS: PECL Input/Output pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V ILPECL
V DD-2.5
-
V DD-0.5
V
Differential inp uts (N ote 1)
V IHPECL
V DD-2.4
-
V DD-0.4
V
Inp ut Differential voltage
V IDPECL
0.1
-
1.4
V
V ILPECL_S
V DD-2.4
-
V DD-1.5
V
V IHPECL_S
V DD-1.3
-
V DD-0.5
V
IIHPECL
-10
-
+10
µA
IILPECL
-10
-
+10
µA
V OLPECL
V DD-2.10
-
V DD-1.62
V
V OHPECL
V DD-1.25
-
V DD-0.88
V
V ODPECL
580
-
900
mV
PECL Inp ut Low voltage
Differential inp uts (N ote 1)
PECL Inp ut High voltage
PECL Inp ut Low voltage
Single end ed inp ut (N ote 2)
PECL Inp ut High voltage
Single end ed inp ut (N ote 2)
Inp ut High current
Inp ut d ifferential voltage
V ID = 1.4v
Inp ut Low current
Inp ut d ifferential voltage
V ID = 1.4v
PECL Outp ut Low voltage
(N ote 3)
PECL Outp ut High voltage
(N ote 3)
PECL Outp ut Differential voltage
(N ote 1)
Notes:
Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs
tied to VDD and GND respectively.
Note 1. Assuming a differential input voltage of at least 100 mV.
Note 2. Unused differential input terminated to VDD-1.4v.
Note 3. With 50W load on each pin to VDD-2v. i.e. 82W to GND and 130W to VDD.
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VDD
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
VDD
130R
ZO=50Ω
I5POS
ZO=50Ω
130R
82R
130R
T06POS
ZO=50Ω
I5NEG
130R
82R
T06NEG
82R
82R
GND
GND
VDD
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
VDD
130R
ZO=50Ω
I6POS
ZO=50Ω
130R
T07POS
130R
82R
19.44, 38.88, 155.52,
311.04 MHz & DIG1
ZO=50Ω
I6NEG
130R
82R
19.44, 51.84, 77.76,
155.52 MHz
T07NEG
82R
82R
GND
GND
Recommended line termination for PECL Input/Output ports for VDD = 3.3V
DC CHARACTERISTICS: LVDS Input/Output pad.
Across operating conditions, unless otherwise stated
PA R A M E T E R
SYM B OL
MIN
T YP
MA X
U N IT S
V VRLVDS
0
-
2.40
V
V DITH
-100
-
+100
mV
V IDLVDS
0.1
-
1.4
V
R T E RM
95
100
105
W
V OHLVDS
-
-
1.585
V
V OLLVDS
0.885
-
-
V
V ODLVDS
250
-
450
mV
V DOSLVDS
-
-
25
mV
V OSLVDS
1.125
-
1.275
V
LV DS Inp ut voltage range
Differential inp ut voltage = 100 mV
LV DS Differential inp ut th resh old
LV DS Inp ut Differential voltage
LV DS Inp ut termination resistance
Must b e p laced externally across th e
LV DS+/- inp ut p ins of A CS8510.
Resistor sh ould b e 100W w ith 5%
tolerance
LV DS Outp ut h igh voltage
(N ote 1)
LV DS Outp ut low voltage
(N ote 1)
LV DS Differential outp ut voltage
(N ote 1)
LV DS Ch arge in magnitud e of
d ifferential outp ut voltage for
comp limentary states
(N ote 1)
LV DS outp ut offset voltage
Temp erature = 25°C
(N ote 1)
Note 1. With 100W load between the differential outputs.
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ACS8515 LC/P
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8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
ZO=50Ω
ZO=50Ω
ZO=50Ω
I5POS
T06POS
I5NEG
T06NEG
I6POS
T07POS
100R
ZO=50Ω
ZO=50Ω
ZO=50Ω
100R
19.44, 38.88, 155.52,
311.04 MHz & DIG1
ZO=50Ω
100R
ZO=50Ω
I6NEG
100R
19.44, 51.84, 77.76,
155.52 MHz
T07NEG
Recommended line termination for LVDS Input/Output ports
DC CHARACTERISTICS: Output Jitter Generation
Across operating conditions, unless otherwise stated
Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8MHz
TCXO on ICT Flexacom + 10MHz reference from Wavetek 905.
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8515
R ev 2
G813 for 155.52 MHz op tion 1
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 2)
G813 for 155.52 MHz op tion 1
65 kHz to 1.3 MHz
UIpp = 0.1
0.048 (N ote 3)
0.048 (N ote 2)
0.053 (N ote 4)
0.053 (N ote 5)
0.058 (N ote 6)
0.053 (N ote 7)
G813 for 155.52 MHz op tion 2
12 kHz to 1.3 MHz
UIpp = 0.1
0.053 (N ote 2)
0.058 (N ote 3)
0.057 (N ote 8)
0.055 (N ote 9)
0.057 (N ote 10)
0.057 (N ote 11)
0.057 (N ote 12)
0.053 (N ote 13)
G813 & G812 for 2.048 MHz
op tion 1
20 Hz to 100 kHz
Revision 2.05/Jan 2001 ã2001 Semtech Corp
UIpp = 0.05
37
0.046 (N ote 14)
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Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8515
R ev 2
G812 for 1.544 MHz
10 Hz to 40 kHz
UIpp = 0.05
0.036 (N ote 14)
G812 for 155.52 MHz electrical
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 3)
G812 for 2.048 MHz electrical
65 kHz to 1.3 MHz
U Ip p =
0.075
0.048 (N ote 3)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8515
R ev 2
ETS-300-462-3 for 2.048 MHz
SEC
20 Hz to 100 kHz
UIpp = 0.5
0.046 (N ote 14)
ETS-300-462-3 for 2.048 MHz
SEC
(Filter sp ec 49 Hz to 100 kHz)
20 Hz to 100 kHz
UIpp = 0.2
0.046 (N ote 14)
ETS-300-462-3 for 2.048 MHz
SSU
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
ETS-300-462-3 for 155.52 MHz
500 Hz to 1.3 MHz
UIpp = 0.5
0.058 (N ote 3)
ETS-300-462-3 for 155.52 MHz
65 kHz to 1.3 MHz
UIpp = 0.1
0.048 (N ote 3)
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Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m easu r em en t on A C S 8515
R ev 2
GR-253-CORE net i/f, 51.84
MHz
100 Hz to 400 kHz
UIpp = 1.5
0.022 (N ote 3)
GR-253-CORE net i/f, 51.84
MHz
(Filter sp ec 20 kHz to 400 kHz)
18 kHz to 400 kHz
UIpp = 0.15
0.019 (N ote 3)
GR-253-CORE net i/f, 155.52
MHz
500 Hz to 1.3 MHz
UIpp = 1.5
0.058 (N ote 3)
GR-253-CORE net i/f, 155.52
MHz
65 kHz to 1.3 MHz
UIpp = 0.15
0.048 (N ote 3)
UIpp = 0.1
0.058 (N ote 3)
UIrms = 0.01
0.006 (N ote 3)
UIpp = 0.1
0.017 (N ote 3)
UIrms = 0.01
0.003 (N ote 3)
UIpp = 0.1
0.036 (N ote 14)
UIrms = 0.01
0.0055 (N ote 14)
GR-253-CORE cat II elect i/f,
155.52 MHz
12 kHz to 1.3 MHz
GR-253-CORE cat II elect i/f,
51.84 MHz
12 kHz to 400 kHz
GR-253-CORE DS1 i/f, 1.544
MHz
10 Hz to 40 kHz
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8515
R ev 2
AT&T 62411 for 1.544 MHz
(Filter sp ec 10 Hz to 8 kHz)
10 Hz to 40 kHz
UIrms = 0.02
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
10 Hz to 40 kHz
UIrms =
0.025
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
10 Hz to 40 kHz
UIrms =
0.025
0.0055 (N ote 14)
AT&T 62411 for 1.544 MHz
Broad b and
UIrms = 0.05
0.0055 (N ote 14)
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Te s t d e f i n i t i o n
F i l t e r u se d
U I sp ec
U I m easu r em en t on A C S 8515
R ev 2
G-742 for 2.048 MHz
DC to 100 kHz
UIpp = 0.25
0.047 (N ote 14)
G-742 for 2.048 MHz
(Filter sp ec 18 kHz to 100 kHz)
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
G-742 for 2.048 MHz
20 Hz to 100 kHz
UIpp = 0.05
0.046 (N ote 14)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m easu r em en t on A C S 8515
R ev 2
TR-N WT-000499 & G824 for
1.544 MHz
10 Hz to 40 kHz
UIpp = 5.0
0.036 (N ote 14)
TR-N WT-000499 & G824 for
1.544 MHz
(Filter sp ec 8 kHz to 40 kHz)
10 Hz to 40 kHz
UIpp = 0.1
0.036 (N ote 14)
Te s t d e f i n i t i o n
F i l t e r u se d
U I sp e c
U I m e asu r e m e n t o n A C S 8515
R ev 2
GR-1244-CORE for 1.544 MHz
>10 Hz
UIpp = 0.05
0.036 (N ote 14)
Notes for the output jitter generation tables
Note 1.
Filter used is that defined by test definition unless otherwise stated
Note 2.
5 Hz bandwidth, 19.44 MHz input, direct lock
Note 3.
5 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 4.
20 Hz bandwidth, 19.44 MHz input, direct lock
Note 5.
20 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 6.
10 Hz bandwidth, 19.44 MHz input, direct lock
Note 7.
10 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 8.
2.5 Hz bandwidth, 19.44 MHz input, direct lock
Note 9.
2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 10.
1.2 Hz bandwidth, 19.44 MHz input, direct lock
Note 11.
1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 12.
0.6 Hz bandwidth, 19.44 MHz input, direct lock
Note 13.
0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock
Note 14.
5 Hz bandwidth, 2.048 MHz input, 8 kHz lock
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Microprocessor interface timing
SERIAL MODE
In SERIAL mode, the device is configured to interface with a serial microprocessor bus. The following figures
show the timing diagrams of write and read accesses for this mode.
During read access the output data SDO is clocked out on the rising edge of SCLK when the active edge selection
control bit CLKE is 0 and on the falling edge when CLKE = 1.
Address, read/write control bit and write data are always clocked into the interface on the rising edge of SCLK.
Both input data SDI and clock SCLK are oversampled, filtered and synchronized to the 6MHz internal clock.
The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1).
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CSB
t su2
t h2
t pw2
SCLK
SDI
t pw1
t h1
t su1
_
R/W
A0
A1
A2
A3
A4
A5
A6
t d1
D0
SDO
t d2
D1
D2
D3
D4
D5
D6
D7
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CSB
t h2
SCLK
SDI
_
R/W
A0
A1
A2
A3
A4
A5
A6
t d1
t d2
D0
SDO
D1
D2
D3
D4
D5
D6
D7
Read access timing in SERIAL Mode.
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Sy m b ol
tsu1
tsu2
P ar am e t e r
MIN
T YP
MA X
0 ns
-
-
160 ns
-
-
Setup SDI valid to SCLKrising edge
Setup CSBfalling edge to SCLKrising edge
td 1
Delay SCLKrising edge (SCLKfalling edge for CLKE = 1)to SDO valid
-
-
17 ns
td 2
Delay CSBrising edge to SDO h igh -Z
-
-
10 ns
tp w 1
SCLK low time
180 ns
-
-
tp w 2
SCLK h igh time
180 ns
-
-
th 1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th 2
Hold CSB low after SCLKrising edge, for CLKE = 0
Hold CSB low after SCLKfalling edge, for CLKE = 1
5 ns
-
-
tp
Time b etw een consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
Read access timing in SERIAL Mode.
C SB
t su2
t h2
t pw 2
SC LK
S DI
t pw1
t h1
t su1
_
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
SD O
Sy m b ol
P ar am e t e r
MIN
T YP
MA X
0 ns
-
-
tsu1
Setup SDI valid to SCLKrising edge
tsu2
Setup CSBfalling edge to SCLKrising edge
160 ns
-
-
tp w 1
SCLK low time
180 ns
-
-
tp w 2
SCLK high time
180 ns
-
-
th 1
Hold SDI valid after SCLKrising edge
170 ns
-
-
th 2
Hold CSB low after SCLKrising edge
5 ns
-
-
tp
Time betw een consecutive accesses (CSBrising edge to CSBfalling edge)
160 ns
-
-
Write access timing in SERIAL Mode.
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Package information
D
2
D1 1
3
AN2
AN3
1
Section A-A
R1
S
E
2
R2
B
AN1
E1
1
A
A
B
3
AN4
L
4
L1
5
1 2 3
b
Section B-B
7
e
A
A2
c
c1
7
7
Seating plane
A1 6
b1 7
b
8
Notes
1
The top package body may be smaller than the bottom package body by as much as 0.15 mm.
2
To be determined at seating plane.
3
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
4
Details of pin 1 identifier are optional but will be located within the zone indicated.
5
Exact shape of corners can vary.
6
A1 is defined as the distance from the seating plane to the lowest point of the package body.
7
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
8
Shows plating.
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64 L Q F P
P ac k ag e
D i m e n si o n s
in mm
D/E
D 1/ E 1
Mi n
N om
12.00
10.00
Max
A
A1
A2
1.40
0.05
1.35
1.50
0.10
1.40
1.60
0.15
1.45
e
0.50
AN1
AN2
AN3
AN4
R1
R2
L
11°
11°
0°
0°
0.08
0.08
0.45
12°
12°
-
3.5°
-
-
0.60
13°
13°
-
7°
-
0.20
0.75
L1
1.00
(ref)
S
b
b1
c
c1
0.20
0.17
0.17
0.09
0.09
-
0.22
0.20
-
-
-
0.27
0.23
0.20
0.16
Thermal conditions
The device is rated for full temperature range when this package is used with a 4 layer or more
PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum
operating temperature must be reduced when the device is used with a PCB with less than these
requirements.
NOTES
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Application information
A simplified Application Schematic for the ACS8515 is illustrated in Figure 9.
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Figure 9: A simplified Application Schematic.
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Revision History
Changes from revision 2.04 to 2.05, January 2001.
I t em
S e ct i o n
P ag e
D e scr i p t i o n
1
Tab le of contents
2
Inclusion of Revision History
2
Register
descrip tion
20
sts_interrup ts register re-formatted
3
Register
descrip tion
22
cnfg_op erating_mode register error corrected
4
Register
descrip tion
24
cnfg_differential_outp uts error corrected
5
Register
descrip tion
25
cnfg_freq_limit register re-formatted and re-w ritten
6
Holdover mode
31
Sp elling error corrected
7
Revision History
46
Section added
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Ordering information
PA R T N U M B E R
DE SCR I P T I O N
A CS8515
SON ET/SDH Line Card Protection, 64 p in LQFP
Disclaimers
Life support - This product is not designed or intended for use in life suport equipment, devices or
systems, or other critical applications. This product is not authorized or warranted by Semtech
Corporation for such use.
Right to change - Semtech Corporation reserves the right to make changes, without notice, to this
product. Customers are advised to obtain the latest version of the relevant information before
placing orders.
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-Mail:
[email protected]
Internet:
http://www.semtech.com
USA:
652 Mitchell Road, Newbury Park, CA 91320-2289
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST:
11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.
Tel: +886 2 2748 3380, Fax: +886 2 2748 3390
EUROPE:
Delta House, Chilworth Science Park, Southampton, Hants, SO16 7NS, UK
Tel: +44 23 80 769008, Fax: +44 23 80 768612
ISO9001
CERTIFIED
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