SC2449 BI-Phase/Dual Controller POWER MANAGEMENT Description The SC2449 can be configured as a dual converter or a bi-phase converter for high current applications. The part is designed for point of use power supplies with 8.5-28V nominal backplane power sources. Multiple supplies can be synchronized together to prevent low frequency harmonics on the backplane. The power dissipation is controlled using a novel low voltage supply technique, allowing high speed and integration, with the high drive currents to ensure low MOSFET switching loss. The use of high speed switching circuits allows very narrow PWM outputs down to 15:1 voltage ratios. Single pin compensation for each channel simplifies development as well as reducing external pin count. Capable of driving MOSFETs via external driver transistors for phase currents beyond 20A. Features K K K K K K K K K K Selectable dual output or bi-phase operation Direct drive for N-channel MOSFETs Undervoltage lockout Synchronization to external clock Multi-converter synchronization Soft start Fast transient response Max duty cycle 45% Output over voltage protection Thermal shutdown Applications K Power supplies for advanced telecoms/datacoms K SO IP, Ethernet and PABX power supplies Typical Application Circuit Revision 4, May 2002 1 www.semtech.com SC2449 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Supply Voltage Voltage on BST Pins Oscillator Frequency Symbol Maximum Units VIN 30 V V BST 38 V 2 MHz 8 V (1) VC C Thermal Resistance Junction to Case θJ C 25 °C/W Thermal Resistance Junction to Ambient θJ A 80 °C/W Operating Temperature Range TA -40 to +85 °C Storage Temperature Range TSTG -55 to +150 °C Lead Temperature (Soldering) 10 seconds TLEAD 300 °C Note: (1) Maximum frequency and maximum supply voltage could cause excessive power dissipation in the part. Electrical Characteristics Unless specified VIN = 24V, TA = 25°C Parameter Conditions Typ 8.5 Supply Voltage, VIN Supply Current Min ENABLE = 0 30 Max Units 28 V 40 mA Under Voltage Lockout 5.8 V UVLO Hysteresis 400 mV Voltage Regulator Pre Regulator Voltage Bgout Voltage 6 CLOAD = 4.7nF 0.99 Bgout Impedance REGDRV Pin Sink Current IREGDRV 1 7 V 1.01 V 3 KΩ 5 mA Error Amp Input Offset Voltage 15 mV Input Offset Mismatch 6 mV Input Impedance 5 Linear Transconductance KΩ .002 A/V Internal Oscillator Frequency RREF = 30K 1 MHz Frequency RREF = 60K 500 kHz 2002 Semtech Corp. 2 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified VIN = 24V, TA = 25°C Parameter Conditions Min Typ Max Units Internal Oscillator (Cont.) Ramp Valley to Peak VIN = 12V 1.5 V Ramp Valley to Peak VIN = 24V 3 V External Clock Detect Time Rise Time < 50ns Unlock Time Frequency Range 2 µs 10 50 µs 0.27 1 MHz High Side Gate Drive Max Duty Cycle 45 % Peak Source CLOAD = 10nF 1 A Peak Sink CLOAD = 10nF 1 A Peak Source CLOAD = 10nF 2 A Peak Sink CLOAD = 10nF 2 A 50 ns Low Side Gate Drive Sync Drive Timing Min Non-overlap PWM Match CLOAD = 1nF Fet Drive < 1V 20 50% Duty Cycle, FOSC = 1MHz -1 1 % VIN = 0 - 5V -10 10 µA Logic Input Pins Input Bias Current Logic Threshold FB2 Disable Threshold 0.8 V VCC - 0.7V V 700 µA Over Current Protection OC+ I/P Bias Current VIN = 24V OC- I/P Bias Current @ trip voltage 40 50 60 µA Over Voltage Protection OVP Threshold 120 % Thermal Shutdown 150 °C Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. 2002 Semtech Corp. 3 www.semtech.com SC2449 POWER MANAGEMENT Pin Configuration Ordering Information Part Number(1) Top View SC2449ISWTR S C 2449E V B PACKAGE SO-28 Evaluation Board TAMB (TA) -40 - +85°C Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (28-Pin SOIC) Block Diagram 2002 Semtech Corp. 4 www.semtech.com SC2449 POWER MANAGEMENT Pin Descriptions Pin Pin Name 1 FB 1 2 COMP1 3 NC No connection. 4 BG 1V reference for error amplifiers, 3K source impedance. 5 FB 2 Feedback for channel 2. 6 COMP2 7 REGDRV Regulator drive for external pass transistor. 8 ENABLE Enable threshold is 2.05V, connect to ground to disable. 9 PHASE2 Phase node input for channel 2. 10 DRVH2 Gate drive for high side channel 2. 11 BSTH2 Bootstrap input for high side channel 2. 12 DRVL2 Gate drive for low side channel 2. 13 BSTL2 Supply for low side channel 2. 14 VC C Pre-regulated IC power supply. 15 BSTL1 Supply for low side channel 1. 16 DRVL1 Gate drive for low side channel 1. 17 BSTH1 Bootstrap input for high side channel 1. 18 DRVH1 Gate drive for high side channel 1. 19 PHASE1 20 PGND 21 OC+ Overcurrent comparator inverting input. 22 OC-2 Overcurrent comparator non-inverting input for channel 2. 23 OC-1 Overcurrent comparator non-inverting input for channel 1. 24 EXTCLK External clock, converter locks to this input when a valid signal is present. 25 CLKOUT Clock out, logic level drive to provide synchronizing signal for other converters. 26 NC No connection. 27 AGND Analog ground. 28 RREF External reference resistor for internal oscillator and ramp generator. 2002 Semtech Corp. Pin Function Feedback for channel 1. Compensation for channel 1. Compensation for channel 2. Phase node input for high side channel 1. Power ground. 5 www.semtech.com SC2449 POWER MANAGEMENT Typical Application Schematic for Two Channel Operation 2002 Semtech Corp. 6 www.semtech.com SC2449 POWER MANAGEMENT Typical Application (Cont.) Bill of Material for Two Channel Operation Item Qty Reference Part Number/Value Manufacturer 1 8 C1 - C8 0.47µF, 50V, Cer. Any 2 3 C9,C24,C25 0.33µF, Cer., 1206 Any 3 2 C10,C11 22nF, Cer., 1206 Any 4 1 C 12 0.1µF, Cer., 1206 Any 5 2 C13,C14 100pF, Cer., 1206 Any 6 1 C 15 47pF, Cer., 1206 Any 7 6 C16,C19,C20,C21,C22,C23 22µF, 35V, Tant. Any 8 2 C17,C18 680µF, 35V, Alum. Any 9 2 C26,C27 2.2nF, Cer., 1206 Any 10 3 C28,C29,C50 1.0nF, Cer., 1206 Any 11 1 C 30 1.0µF, Cer., 1206 Any 12 11 C31,C32,C33,C36,C37,C40,C41,C42,C43,C44,C45 10µF, Cer., 1206 Any 13 4 C34,C35,C38,C39 1500µF, 6.3V, Alum. Any 14 4 D1,D2,D5,D6 1A, 40V, Schottky, MELF, 1N5819M Any 15 2 D3,D4 3A, 40V, Schottky, 30BQ040 Any 16 2 L1,L2 Inductor, 9 turns Magnetics: Kool Mu P/N: 77206-A7 17 4 M1,M2,M3,M4 N-Channel MOSFET, TO263A B Fairchild P/N: FDB7030BL 18 1 Q1 80V, 1A, NPN, Med. Pwr. SOT-223 B C P 56C T 19 2 R1,R3 2.2, 5%, 1206 Any 20 2 R4,R6 4.7, 5%, 1206 Any 21 4 R2,R5,R7,R11 1.0, 5%, 1206 Any 22 1 R8 56k, 5%, 1206 Any 23 2 R9,R10 2.2k, 5%, 1206 Any 24 1 R12 Chip resistor, 0.005, 1W, 1%, 2512 Any 2002 Semtech Corp. 7 www.semtech.com SC2449 POWER MANAGEMENT Typical Application (Cont.) Bill of Material for Two Channel Operation (Cont.) Item Qty Reference Part Number/Value Manufacturer 25 4 R13,R14,R15,R16 2.2, 1/4W, 5%, 1210 Any 26 1 R17*,R19,R31* Chip resistor, 0, 1206 Any 27 2 R20,R21 1.00k, 1%, 1206 Any 28 1 R22 2.32k, 1%, 1206 Any 29 1 R23 4.02k, 1%, 1206 Any 30 2 R26,R27 2.0k, 5%, 1206 Any 31 1 R28 10, 5%, 1206 Any 32 1 R29 51, 5%, 1206 Any 33 1 R34 15k, 5%, 1206 Any 34 1 R36 68.1k, 1%, 1206 Any 35 1 R37 10.0k, 1%, 1206 Any 36 1 S C 2449 Bi-Phase/Dual Controller, SO-28W Semtech Corp. P/N: SC2449ISW 805-498-2111 Notes: 1. * Indicates optional parts. 2. Some parts are selected due to availability or lead time, and are not optimized. 2002 Semtech Corp. 8 www.semtech.com SC2449 POWER MANAGEMENT Typical Application (Cont.) Schematic for Bi-Phase Operation 2002 Semtech Corp. 9 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves Two Channel Operation Efficiency in Two-Channel Application Circuit (5V/12A, 3.3V/18A) Overall System Efficiency vs. Overall Load (W ) of the 5V and 3.3V channels 95.00% 90.00% Efficiency 85.00% 80.00% Efficiency 75.00% 70.00% 65.00% 60.00% 0 20 40 60 80 100 120 Output Power (W ) Phase Node Waveform of Two-Channel Application Circuit (Vin = 24V, Load Current = 12A for 5V, Load Current = 18A for 3.3V) ch1: Vphase5V; ch2: Vphase3.3V 2002 Semtech Corp. 10 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) 3.3V Channel Gate Waveform (Vin = 24V, Load Current = 18A) ch1: VgateH; ch2: VgateL 5.0V Channel Gate Waveform (Vin = 24V, Load Current = 12A) ch1: VgateH; ch2: VgateL 2002 Semtech Corp. 11 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) Start-up (Vin = 24V, Vout1 = 5.0V/12A, Vout2 = 3.3V /18A) ch1: Vout5.0V; ch2: Vout3.3V Bi-Phase Operation (Vout = 3.3V, Max. Load Current = 20A) Efficiency in Bi-Phase Application Circuit (3.3V/20A) Overall System Efficiency vs. iLoad 90.00% 85.00% Efficiency 80.00% 75.00% Overall Efficiency 70.00% 65.00% 60.00% 0 5 10 15 20 Load Current (A) 2002 Semtech Corp. 12 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) Phase Node Waveform (Vin = 24V, Vout = 3.3V, Load Current = 20A) ch1: Vphase1; ch2: Vphase2 Gate Waveform (Vin = 24V, Vout = 3.3V, Load Current = 10A/phase) ch1: VgateL; ch2: VgateH 2002 Semtech Corp. 13 www.semtech.com SC2449 POWER MANAGEMENT Electrical Characteristic Curves (Cont.) Start-up (Vin = 24V, Vout = 3.3V, Load Current = 5A/phase) ch1: Vout Theory of Operation The SC2449 employs a voltage mode control with feed forward to provide fast output response to load and line transients. The SC2449 has two outputs, which can be used to generate two separate supply voltages or can be combined in bi-phase operation to generate one single supply voltage. The internal reference is trimmed to 1 V with +/-1% accuracy, and the outputs voltages can be adjusted by two external resistors. In bi-phase operation, the dual switching regulators are operated 180° out of phase. Load current sharing between phases is normally required, and this can be achieved by using precise feedback voltage divider resistors (typically 0.1%) to match individual phase output voltage. In addition, small drooping resistors ( could be PCB traces) are employed at the output of each phase to enhance phase current balance. PWM Control Changes on the output voltages are fed to the inverting input of the Error Amplifiers, by the FB1 and FB2 pins, and compared with the internal 1 V reference. The compensation to the transconductance amplifier is achieved by connecting a capacitor in series with a resistor from the COMP1 and COMP2 pins to AGND respectively. The error signal from the error amplifier is compared to the saw tooth waveform by the PWM comparator, and 2002 Semtech Corp. matched timing signal is generated to control the upper and lower gate drives of the two phases. A single Ramp signal is used to generate the control signals for both of phases, hence the maximum duty cycle is less than 50%. Oscillator Frequency Selection The sawtooth signal is generated by charging an internal capacitor with a current source. The charge current is set by an external resistor connected from the RREF pin to AGND. The oscillator frequency and the external resistance follow an inversely proportional relationship. Feed Forward The SC2449 incorporates a voltage feed forward scheme to improve line transient immunity when changes of the input voltage occur. As the input voltage changes, the ramp valley to peak voltage of the internal oscillator follows this change instantly. As a result the output voltage will have minimum disturbance due to the input line change. Synchronized Operation The internal oscillator can be synchronized to an external clock operating in the range of 270 kHz to 1 MHz. 14 www.semtech.com SC2449 POWER MANAGEMENT Theory of Operation (Cont.) The switching frequency of each channel is one half of the oscillator frequency. The oscillator clock is also available externally through the CLKOUT pin and can be used to provide synchronization for other converters. BG capacitor is being charged through the internal resistor, the PWM pulse width increases until the bandgap is charged completely. This controlled start up of the PWM prevents output voltage overshoot, unnecessary component stress, and noise generation during start up. Bias Generation Over Current Protection A 6-7 Volt supply voltage is required to power up the SC2449. This voltage could be provided by an external power supply or derived from VIN through an external pass transistor. REGDRV is the control signal to the base of the pass transistor that will regulate VCC. The voltage at the VCC pin is compared to the internal voltage reference, and the REGDRV pin can sink up to 5mA current to regulate the voltage at the VCC pin. The SC2449 current limit provides protection during an over current condition. A sense resistor or PCB trace can be used to sense the input supply current. Enable If the ENABLE pin is connected to logic high, the SC2449 is enabled, while connecting it to ground will put the device into disabled mode. The ENABLE pin can also be configured as input UVLO through input voltage divider resistors. The controller will be enabled when the ENABLE pin voltage reaches 2.05 V, and will be disabled with 400mV hysteresis. Under Voltage Lockout Under Voltage lockout (UVLO) circuitry senses VCC through a voltage divider. If this signal falls below 5.8V, with a typical hysteresis of 400 mV, the BG pin is pulled low by an internal transistor causing the lower MOSFET gate to be on and the upper MOSFET gate off for both phases. Over Voltage Protection The SC2449 provides OVP protection for each output individually. Once the converter output voltage exceeds 120% nominal output voltage, the lower MOSFET gates are latched on and the upper MOSFET gates are latched off. The latch is then reset once the OVP condition is removed. Soft Start An external capacitor at the BG pin is used to set up the Soft Start duration. The capacitor value, in conjunction with the internal 3K resistor at the BG pin, control the duration to bring up the bandgap to its final level. As the 2002 Semtech Corp. The over current protection trip point is determined by the voltage drop across the sense resistor. Once this voltage drop exceeds the voltage across the programming resistor (50µA through R26), OCP protection circuit will be triggered. Due to component and layout parasitics, filtering might be necessary across the OC+ and OC- pins. It is recommended to use a small RC filter with time constant around 0.2µS. To clean up the phase node ringing, one usually has to have a ceramic capacitor from the top FET drain to the power ground. Too much capacitance will bypass the top FET current from the sensing resistor hence reducing OCP accuracy, while to little capacitance will not be able to clean up the phase node ringing for full load operation. See application circuits. Once an over current condition occurs, the lower MOSFET gates are latched on and the upper MOSFET gates are latched off. The latch is then reset at the beginning of the next clock cycle. The cycle is repeated indefinitely until the over current condition is removed. Thermal Shutdown In addition to current limit, the SC2449 monitors over temperature condition. The over temperature detection will shut down the part if the SC2449 die temperature exceeds 150°C, and will auto reset once the die temperature is dropped down. Gate Drive The SC2449 integrates high current gate drivers for fast switching of large MOSFETs. The high-side gates can be switched with peak currents of 1 Amp, while the larger low-side gates can be switched with peak currents of 2 Amps. A cross conduction prevention circuitry ensures a non-overlapping operation between the upper and lower MOSFETs. This prevents false current limit tripping and provides high efficiency. 15 www.semtech.com SC2449 POWER MANAGEMENT Control Loop Design R2 The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: R1 0 Gpwm Error-Amp Verror - L Duty (1) Calculate the corner frequency of the output filter: + R Rc + + Ro Vin Vbg C 0 - 0 0 The control model of SC2449 can be depicted in Fig. 1. This model can also be used in a Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of: .. .. A . G error . 0.002 ⋅ V The compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is proportional to the input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the ramp amplitude, and this gain is given by: V ramp The total control loop-gain can then be derived as follows: where 1 s. R. C . s. R. C 1 s. R c. C o L 2 s . L. C o . 1 Ro 2 .π. L .C o F e rs< Ro . c C o F sw 5 If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency or the output ripple frequency in bi-phase mode operation: Fx_over F sw 5 If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: R Rc 1 2 . π. R (3) Check that the ESR zero frequency is not too high. 1 s. R c. C o .. .. T o G error.V in.G pwm .R . 2002 Semtech Corp. F e sr 1 where the ramp amplitude (peak-to-peak) is 3 volts when input voltage is 24 volts. T( s) T o . 1 (2) Calculate the ESR zero frequency of the output filter capacitor: 0 Fig. 1. SC2449 control model. G pwm Fo Co when: 1 G pwm. V in. G error . F esr Fo 2 . F x_over F esr . Vo V bg F o < F esr< F x_o ver R2 R1 R2 16 www.semtech.com SC2449 POWER MANAGEMENT Control Loop Design (Cont.) or Step 1. Output filter corner frequency R 1 . Fo 2 . G pwm. V in. G error F esr F x_over Fo . Vo V bg Fo = 1.453 KHz Step 2. ESR zero frequency: when F esr< F o < F x_over Fesr = 2.653 KHz Step 3. Check the following condition: (5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency: Fo F zero zero An example is given below to demonstrate the procedure introduced above. The parameters of the power supply are given as: V I F o o := 24 V Fx_over = 30 KHz R = 5.89 KΩ Step 5. Calculate the compensator C: C = 92.98 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85°C that ensures the loop stability. Fig. 2 shows the Bode plot of the loop. := 2.5 V := 20 A := 150 KHz sw L := 4 µH C o R R R 2002 Semtech Corp. in 5 Step 4. Choose crossover frequency and calculate compensator R: (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. V F sw Which is satisfied in this case. 5 1 2 . π. R . F C F ers< := 3000 µF c := 0.02 Ω 1 := 1.5 KΩ 2 := 1.0 KΩ 17 www.semtech.com SC2449 POWER MANAGEMENT Control Loop Design (Cont.) L o o p G ain M ag ( dB) 10 0 ma g ( i ) 50 0 50 10 10 0 3 1 10 F 4 1 10 5 1 10 6 1 10 i L o o p G ain P h ase ( D egr ee) 0 45 p h a s e( i ) 90 13 5 18 0 10 10 0 3 1 10 F 4 1 10 5 1 10 6 1 10 i Fig. 2. Bode plot of the loop Layout Guidelines Good layout is necessary for successful implementation of the SC2449 bi-phase/dual controller. Important layout guidelines are listed below. 1). The high power parts should be laid out first. The parasitic inductance of the pulsating power current loop (start from positive end of the input capacitor, to top MOSFET, then to bottom MOSFET back to power ground) must be minimized. The high frequency input capacitors and top MOSFETs should be close to each other. The freewheeling Schottky diode, the bottom MOSFET snubber, and the bottom MOSFET should be placed close to each other. The MOSFET gate drive and current sense loop areas should be minimized. The gate drive trace should be short and wide. 2). The layout of the two phases should be made as symmetrical as possible. The SC2449 controller should be placed in the center of the two phases. Please see evaluation board layout as an example. 2002 Semtech Corp. 3). Separate ground planes for analog and power should be provided. Power current should avoid running over the analog ground plane. The AGND is star connected to the PGND at the converter output to provide best possible ground sense. Refer to the application schematics, certain components should be connected directly to the AGND. 4). If a multi-layer PCB is used, power layer and ground layer are recommended to be adjacent to each other. Typically the power layer is on the top, followed by the ground layer. This results in the least parasitic inductance in the MOSFET-capacitor power loop, and reduces the ringing on the phase node. The rest of the layers could be used to run DC supply traces and signal traces. An example of a two-layer PCB layout is given below to illustrate these layout principles. 18 www.semtech.com SC2449 POWER MANAGEMENT Layout Guidelines (Cont.) Component Side (TOP) Copper (TOP) 2002 Semtech Corp. 19 www.semtech.com SC2449 POWER MANAGEMENT Layout Guidelines (Cont.) PGND A GN D Copper (BOTTOM) Outline Drawing - SO-28W Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2002 Semtech Corp. 20 www.semtech.com