SHARP ID246

Product Overview
®
Integrated Circuits Group
ID246 Series
Flash Memory Card
(Model Numbers: ID246xxx)
Spec No.: CPS0008E-001
SHARI=
ID246 SERIES PRODUCT
OVERVIEW
l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.
l When using the products covered herein, please observe the conditions written herein and the precautions
outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from
failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When
using the products covered herein for the equipment listed in Paragraph (2). even for the following
application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for
the equipment listed in Paragraph (3).
* Office electronics
. Instrumentation and me.asuring equipment
* Machine tools
* Audiovisual equipment
. Home appliances
* Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands
high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for
ensuring reliability and safety of the equipment and the overall system.
* Control and safety devices for airplanes, trams, automobiles, and other transportation equipment
. Mainframe computers
- Traffic control systems
* Gas leak detectors and automatic cutoff devices
* Rescue and security equipment
. Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following
performance in terms of functionality,
equipment which demands extremely high
reliability, or accuracy.
* Aerospace equipment
. Communications
equipment for trunk lines
. Control equipment for the nuclear power industry
* Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a
sales representative of the company.
l Please direct all queries regarding the products covered herein to a sales representative of the company.
CPS0008E-00
SHARP
2
ID246 SERIES PRODUCT OVERVIEW
Contents
1. Intnxluction .................................................................................................................
2. Features .......................................................................................................................
P.
3
P.
3
3. Block Diagram ............................................................................................................
4. Pin Connections ..........................................................................................................
P.
4
P.
5
5. Signal Description ......................................................................................................
6. Functions .....................................................................................................................
P.
6
P.
7
P.
7
P.
8
P.
9
P.
9
P.
12
P.
12
P.
12
P.
12
P.
12
P.
15
P.
17
P.
18
P.
21
P.
22
11. 1 Absolute Maximum Ratings ...........................................................................
11. 2 Recommended Operating Conditions. ............................................................
P.
22
P.
22
11. 3 Capacitance .....................................................................................................
P.
22
P.
22
6. 1
6. 2
Common Memory.. .........................................................................................
Attribute Memory ................ ...........................................................................
Function Table ..... . ..........................................................................................
7. Card Information Structure (CIS) ...............................................................................
8. Card Control ...............................................................................................................
6. 3
8. 1
8. 2
8. 3
8. 4
Reset
.............................................................................................................
Status Register ................................................................................................
Write Protect Switch .......................................................................................
Identifier Codes. ..............................................................................................
9. Component Management Register (CMR) .................................................................
10. Commad Definitions.. ...............................................................................................
10. 1 Query Command.. ....... ....................................................................................
lo. 2 STS Configuration
11. Electrical Specifications
11. 4 AC Input/Output
Command ........................................................................
.............................................................................................
Test Conditions ..................................................................
12. DC Characteristics
......................................................................................................
P.
23
13. AC Characteristics
......................................................................................................
P.
25
13. 1 Common Memory Read Operations ...............................................................
P.
25
13. 2 Command Write Operations : Common Memory ..........................................
P.
27
13. 3 Attribute Memory Read Operations ...............................................................
13. 4 Attribute Memory Write Operations ..............................................................
P.
33
P.
34
P.
35
P.
36
P.
36
P.
37
Down.. ................................................................................
14. Specification Changes ................................................................................................
15. Other Precautions.. ......................................................................................................
16. External Diagrams ......................................................................................................
13. 5 Power-Up/Power
SHARP
ID246 SERIFS PRODUCT OVERVIEW
1. Introduction
This datasheet is for SHARP’s ID246 series flash memory card. This datasheet provides all AC and DC characteristics (including timing waveforms)
grated registers(including
and a convenient reference for the device command set and the cards inte-
the Flash Memory’s status registers). This datasheet provides description of the meth-
ods which are very helpful for customer to use the card.
2. Features
2.1
Type
2.2
Overview
Flash Memory Card
Common
Memory
Capacity
ID246Pxx
ID246Rxx
ID246Sxx
Byte
32Mbyte
40Mbyte
48Mbyte
Word
16Mword
20Mword
24Mword
LH28F032SKD
8devices
LH28F032SKD
lodevices
LH28F032SKD
12devices
Device
Attribute Memory
Capasity
(Note:standard
2Kbyte
CIS is not writable)
vcc=sv ! vpp=sv,
vcc=3.3v I vpp=3.3v,5v
Supply Voltage
150ns(@Vcc=%)
250ns(@Vcc=3.3v)
Access time
64K word blocks
Erase Unit
Program/Erase
Cycles
External
Dimensions
1OO,OOOcycles/Block
PCMCIA Type 1
54.0X 85.6X 3.3mm
2.3
Interface
Parallel I/O Interface
2.4
Function Table
See Function Table in page. 9
2.5
Pin Connections
See Pin Connections in page. 5
2.6
Type of Connector
Conforms to PCMCIA PC Card Standard 95 Card Use Connector
Card connector:
JC20-J68S-NB3
by JAE
FCN-568J068-G/O
ICM-C68S-TS
2.1
Operating Temperature
0 to 60°C
2.8
Storage Temperature
-20 to 65°C
2.9
Not designed for rated radiation hardened.
by Fujitsu
13-5035A by JST
or
or
SHARP
ID246 SERIES PRODUCT
OVERVlEW
3. Block Diagram
Control
Logic
Flash Memory
l w
VPP2
b Data
b Add
**
zvcc
VPPl
.
VPP2
~
: :
: :
l
wE#
RP#-+
*
OE#
STS ---( ’
-
/I
wFJ#
cE#
wE#
OE#
STS
4--4--4---(c
4i()-I
I
’
’
:
.
m
VPP2
vcc
- - - -
VPP 1
t
Flash Memory
3
e
-Rp#
-
cE#
/A
vcc
t
Flash Memory
-
Data *
Add +
+
Data
Add
STS
vcc
t
-
-
-
-
Flash Memory
wP#k+
cE#l*
wE# 4---,
OE# M
Figure 1. Block Diagram
A
-
-bwP#
+
cm
*WI3
OE#
Data *’
Add 4
RPWJ
STS -
.
SHARP
ID246 SERIES PRODUCT OVERVIEW
5
4. Pin Connections
Table 1. Pin Connections
I;r I
5
D6
6
7
8
D7
SIGNAL
CEI#
AIO
9 OE#
10 Al1
1 11 1As
I
I
I/O
I
FUNCTION
I/O
I/O
I
I
I
I
I I
Data Bit 6
Data Bit 7
Card Enable 1
Address Bit 10
Output Enable
Address Bit 11
IAddress Bit9
1
1
15 IWE#
I 16 IRDYTSSY#
17 vcc
18 VPPI
I I I Write Enable
I o IReady BUSY
Supply Voltage
Program Voltage
1 22
23
24
25
26
I I IAddress Bit7
I Address Bit 6
I Address Bit 5
I Address Bit 4
I [Address Bit 3
IA7
As
As
A4
As
4
ACTIVE
I I
;,”
39
40
41
42
43
44
SIGNAL
T
I
I/O
I
FUNCTION
LOW
I
I
I
DIG
~D,J
DIG
CEz#
VSI#
RFU
1 I/O
1 I/O
I/O
I
0
IData Bit 13
IData Bit 14
Data Bit 15
Card Enable 2
Voltage Sense 1
Reserved
IReserved
I
ACTIVE
I
I I 45 Imu
1
1 1 50 IAx
I
I I 1Address Bit 20
I I IAddress Bit 21
1 1 56 IA25
1 1 57 IVS2#
1 1 58 IkESET
I 1 (Address Bit 25
I 0 IVoltage Sense 2
I I (Reset
LOW
I
LOW
HIGH
LOW
-II
I 30 (Do
62
63 (BVD2
IBVD~
I I/O (Data Bit 0
I 0
Battery Voltage Detect 21
1 I/O (Data Bit 8
LOW
1 34 (GND
I
1Ground
1 1 68 (GND
I
(Ground
T1003-01
I
CPSOQ08E.001
SHARP
ID246 SERIES PRODUCT OVERVIEW
6
1
5. Signal Description
Table 2. Signal Description
Function
ADDRESS INPUTS:
These are address bus lines which enable direct addressing of memory
on the card. Signal Ao is not used in word access mode.
40425
,,.
h-D15
I
Pull-down
(250kn @Vcc=Sv)
CARD ENABLE 1 & 2:
CEI# enables D+D7, CE2# enables Da-DIG.
:Ei#,CEz#
OUTPUT ENABLE:
Active low signal gating read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUp
Indicates status of internally timed erase or write activities. ID246
series has two types of Ready/Busy output mode; PCMCIA mode and
High-Performance mode.
In PCMCIA mode, a high output indicates the memory card is ready
to accept accesses. A low output indicates that a device in the memory
card is busy.
In High-Performance mode, the card outputs low when the card is in
default state. A high output indicates at least one of flash memory
devices in the card comes to be ready to accept accesses.
>E#
NE#
IDYlBSY#
:DI#, CDz#
0
0
Pull-down Of2
CARD DETECT 1 & 2:
These signalsprovide for card insertion detection. The signalsare
connectedto groundinternally on the memory card, andwill be forced
low whenevera cardis placedin the socket.The host socketinterface
circuitry shall supply 10K or larger pull-up resistorson thesesignal
pins.
WRITE PROTECT:
Low:PuIl-down On
Write Protect reflects the statusof the Write Protect switch on the
High:Pull-up 1OOkn
memorycard. WP setto high = write protected.
I
o
VP
DATA INPUT/OUTPUT
Do through DIG constitute the bi-directional data bus. Drs is the most
significant bit.
t
(PPI.VPP2
[cc
WRITE / ERASE POWER SUPPLY 1 & 2:
I
CARD POWER SUPPLY:
I
iND
GROUND:
I
EG#
REGISTER SELECT:
Providesaccessto attribute memory when REG# is low.
ESET
RESET
Active high signalfor placingcard in Power-On Default State.
;VDI, BVDz
'Sl#,
vs2#
0
I
Pull-up 1ookQ
o VSI#: Pull-down
VS2#: N.C.
I
BATTERY VOLTAGE DETECT 1 & 2:
Thesesignalsarepulled high to maintainSRAM card compatibility.
VOLTAGE SENSE1 & 2:
Notifiesthe hostsocketof the CIS’sVCC requirements.VS~#
is pulledlawn to ground when using the standard CIS, that indicate 3.3V
operatingis available.
RESERVEDFOR FUTURE USE
T1172E.01
CPS0008E40'
SHARI=
7
ID246 SERIES PRODUCT OVERVIEW
6. Functions
6.1
Common
6. 1. 1
Memory
Common
Memory Architecture
Figure 2 shows common memory architecture of ID246 series flash memory card. Device pair is consisted of two
pieces of flash memory devices. Each device has individually erasable and lockable blocks. All blocks are divided
into odd bytes and even bytes.
Each device pair and block is selected by address bits. Table 3 shows definitions of address bits.
/
DEVICE PAIR 5
DEVll
1
DEVIO
/
/’
Blodc63
/
‘‘IW
‘I
I
I
1
I
I
I
=
=
=
1
Bank1
DEVICi PAIR 2
DEVS
1
DEV4
DEVIti
PAIR 1
DEV3
1I
DEV2
DEVICE PAIR 0
LH28FO32SKD
LH28FO32SKD
- jGx-8&- - -4;I z 8jjii DEVl
I
DEVO
/
/
Bank1
Bank0
Bank0
1
ODD
Word
Odd-Byte
Mode
Mode
EVEN
yte Mode
I\1
D15-D8
Word Mode
Byte Mode
D7-DO
F1076E4)’
Figure 2. Common Memory Architecture
Table 3. Address Difinitions
Address Pifinitions
32MB ,4OMB ,48MB
Select Even / Odd byte in the byte access
mode.
Select address in the block.
Select a block.
Select a bank
Select a device pair.
A0
A16-Al
(64KJ3/Block)
A21 -A17
(32blocks/bank)
A22 (2banks/device)
A25 -A23
T1173E-01
SHARI=
6. 1.2
ID246 SERIES PRODUCT
8
OVERVIEW
Erase
Erase is executed one block at a time. Erasable block size is 64K bytes in byte access mode and 128K bytes in
word access mode.
6. 1.3
Address
Decoding
The higher address area of ID246 series flash memory card which goes beyond common memory area is not
decoded in common memory access. It means that the system will access to random memory address of the
memory card even if system will try to access to the memory address which exceeds memory capacity of the card.
Please do not access to the memory address which goes beyond memory capacity of the card.
As an enhanced function, the memory card enables to output invalid data (either of OOOOhor FFFFh) when system
will access to the memory address which exceeds memory capacity of the card. Please contact our sales & marketing support to find concrete way of setting.
6.2
Attribute
Memory
Figure 3 shows attribute memory map of ID246 series flash memory card. Attribute memory is contained within
the Card Control Logic. Attribute memory contains the Card Information Structure (CIS) and Component Management Registers (CMRs). The CIS contains tuple information and is located at even byte addresses beginning
with address OOOOh(Please refer to section 7). The standard CIS of ID246 series flash memory card is hardwired
and is for read only. As an enhanced function, the hardwired CIS area is switchable to EEPROM so that customer
can program required CIS. Please contact our sales & marketing
support to find concrete way of setting. The
CMRs are located at even byte addresses beginning with address 4000h (Please refer to section 9).
,-“--’
Address
T--“-‘,
ODD
EVEN
F1003-01
Figure 3. Attribute Memory Map
SHARP
ID246 SERIES PRODUCT
6.3 Function
Table
6.3.1
Memory Access
Common
Table 4. Common Memory
OVERVIBW
tcess
Mode
Stand-by
Byte Read
Word Read
Odd Byte Read
Byte Write
H
H
L
H
H
L
Don’t care
Odd
Word Write
H
L
L
X
H
L
Odd
Even
Odd Byte write
H
L
H
X
H
L
Odd
Don’t care
REG#
CE,#
CE,#
A,
OE#
WE#
D,,,
X
H
H
X
X
X
High-Z
High-Z
L
H
L
L
L
H
High-Z
Even
xx
6.3.2 Attribute Memory Access
Table 5. Attribute Memory Access
Mode
Stand-by
Byte Read
D 7-o
L
H
L
H
L
H
High-Z
Word Read
L
L
L
X
L
H
xx
Even
Odd Byte Read
L
L
H
X
L
H
xx
High-Z
L
H
L
L
H
L
Don’t care
Even
L
H
L
H
H
L
Don’t care
Don’t care
Word Write
L
L
L
X
H
L
Don’t care
Even
Odd Byte write
L
L
H
X
H
L
Don’t care
Don’t care
Byte Write
TS1059E-02
XX:Output data is invalid.
The standard CIS is for read only. Write operation is only for CMRs and CIS on EEPROM
7. Card Information
Structure
(CIS)
The CIS is contained within attribute memory (Please refer to section 6.2). Table 6 shows standard CIS tuples, but
it is for read only. As an enhanced function, the hardwired CIS area is switchable to EEPROM so that customer
can program required CIS. Please contact our sales & marketing support to find concrete way of setting.
SHARP
ID246 SERIES PRODUCT
OVERVIEW
Table 6. Standard CIS
, 02h
/ 04h
-1
Address 1 Value 1
Description
1 53h ISProduct Info
1 Address 1 Value
1 OOh 1 Olh
Rash Memory
Access Time 150ns
I I
I
48h
4Ah
4Ch
4Eh
50h
Capacity
32MB
40MB
7Eh
9Eh
08h
52h
54h
56h
02h
57h
10h
12h
58h
5Ah
5Ch
5Eh
60h
Conditions 3Vcc
Flash Memory
Access Time 250ns
62h
64h
66h
6Xh
Capacity
32MB
40MB
48MB
End of Tuple
I
1Ch
1Eh
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
48h
H
41h A
52h R
50h P
OOh END TEXT
4Yh I
4th
D
32h
34h
2
4
53h
52h
S
R
20h SPACE
OOh ENDTEXT
53h S :Maker Info
48h
41h
H
A
6Ah
6Ch
52h R
1 50h IP
1 20h ISPACE
6Eh
70h
72h
43h C
4I=h 0
1 52h IR
74h
76h
I 50h IP
1 4Fh 0
78h
7Ah
7Ch
7Eh
80h
82h
84h
86h
i 52h IR
( 41h A
1 54h IT
49h I
4I=h 0
4Eh N
OOh END TEXT
PFh End of Tuple
1Ah Configuration Info
I
04h Tuple Link
( 1Ph IROM
Access Time 200ns
Capacity 2KB
End of Tuule
28h
2Ah
1 2Cb
2Eh
30h
32h
34h
I
I
1 46h
05h Tuple Link
1 02h IConditions 3Vcc
1 1Ph ROM
2Ab Access Time 2OOr-r~
Olh
PI%
18h
02h
Capacity 2KB
End of Tuple
JEDEC Code ID
Tuple Link
BOh
DOh
OOh
15h
23h
Manufacture Code
Device Code
End of Tuple
Version Info Level 1
Tuple Link
04h
Major Version
Olh
Minor Version
I
I
88h
8Ah
05h
Tuple Link
Last Index of Configuration Table
CPS0008E401
SHARP
ID246 SERIES PRODUCT
OVERVIEW
Table 8. Standard CIS (Continued)
Address
9Ah
1 Value 1
Description
08h Tiple Link
Olh
Index
9Ch
9Eh
02h
AOh
A2h
55h
Vcc Voltage 5V
OCh
06h
06h
23h
ICCStatic
ICCAverage
ICCPeak
ICCPowerdown
A4h
A6h
A8h
AAh
vcc & vpp
79h ParameterSelection
ACh 1 1Bh 1ContieurationTableEntrv 2
AEh
09h Tuple Link
02h Index
BOh
B2h
B4h
B6h
B8h
BAh
I
Olh
79h
B5h
I
Vcc Onry
ParameterSelection
Vcc Voltage 5V
1Eh
OCh ICCStatic
7Dh ICCAverage
7Dh ICCPeark
BCh
BEh
COh 1 1Bh (ICCPowerdown
I
C2h
1Eh Device Geometry
C4h
06h Tuple Link
C6h 1 02h Bus
C8h 1 llh IErase
CAh ) Olh IReadsize
I
CCh
CEh
DOh
D2h
D4h 1
I
Olh Write size
Olh Partation: lblock
0 1h Non-interleaved
20h ManufacturerID
04h ITunle Link
-+E-ta
Manufacturer Code
DEh
21h
Function Identification
EOh
E2h
E4h
E6h
02h
0 1h
OOh
FFh
Tuple Link
Function: MEMORY
System:None
End of CIS
I
CPS0008E-00
SHARP
12
ID246 SERIES PRODUCT OVERVIEW
8. Card Control
8. 1
Reset
The card is in initial state directly after power-up.
But we recommend to do reset operation after power-up
to
make sure to initialize the card.
During block erase, byte write, or lock-bit configuration modes, an active RESET will abort the operation. RDYI
BSY# remains low until the reset operation completes. Memory contents being altered are no longer valid; the
data may be partially erased or written. The host must wait after RESET goes to logic-Low
(VIL) before it can
write another command, as determined by tpt.nvL.
It is important to assert RESET to the card during a system reset. If a CPU reset occurs without a card reset, the
host will not be able to read from the card if that card is in a different mode when the system reset occurs.
For example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt
to read code from the card, but will actually read status register data. Sharp’s ID246 Series Flash Memory Card
allows proper card reset following
8. 2
a system reset through the use of the RESET input.
Status Register
Each flash memory device in the card has status register. The status register may be read to determine when a
write, block erase, or lock-bits
configuration
is complete, and whether that operation completed successfully
(please refer to Table 7). It may be read at any time by writing the Read Status Register command (70h, 7070h)
into the CUI. In word access mode, the status register data of even byte devices are output to D7-0,and the status
register data of odd byte devices are output to D15-8.
8. 3
Write Protect Switch
The ID246 Series Flash Memory Card has a write protect switch on the back of the card. When the switch is in the
write protect position, the card blocks all writes to the common and attribute memory without Card Management
Registers region (see Figure 4 ).
8.4
Read Identifier Codes / Block Status Code
Manufacture Code and Device Code are contained within each flash memory device in the memory card. The
identifier code operation is initiated by writing the Read Identifier Codes command (90h, 9090h) into the CUI of
each memory device. The specific address of each device is necessary to be selected to read these codes (Table 9).
Writeble position
r
I
Write pro=sition
Note: The write protect switch is shown by the black square.
Figure 4. Write Protect Switch
[email protected])ol
SHARP
Table 7(a).
ID246 SERIES PRODUCT OVERVIEW
13
Status Register Definition
WSMS
7
BESS
1 ECBLBS
6
1 WSBLBS
5
4
VPPS
3
wss
2
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE
1 = Ready
0 = Busy
STATUS
Check RY/BY# pin or SR.7 to determine block erase, full
chip erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7=“0”
SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are “1”safter a block erase. full chip
erase,(multi) word/bite write, block lock-bit configuration or
STS configuration attempt, an improper command sequence
was entered.
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS
1 = Error in Erase or Clear Block Lock-Bits
0 = Successful Erase or Clear Block Lock-Bit
5R.4 = WRITE AND SET BLOCK LOCK-BIT
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
STATUS
SR.3 = VP? STATUS
1 = VPP Low Detect, Operation Abort
SR. 1 does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit, and
WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. Itinforms the system, depending on the
attempted operation, If the block lock-bit is set and/or WP#
is not VIH. Reading the block lock configuration codes after
writing the Read Identifier Codes command indicates block
lock-bit status.
0 = VPP OK
3R.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed
jR. 1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
3R.0 = RESERVED
SR.3 does not provide a continuous indication of VPP
level. the WSM interrogates and indicates the VPP level only
after block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration command sequences. SR.3 is
not guaranteed to reports accurate feedback only when
vPPi=vPPn
1.
SR.0 is reserved for future use and should be masked out
when polling the status register.
FOR FUTURJZ ENHANCEMENTS
TllfnC~n,
7
6
5
4
3
2
1
0
NOTES:
XSR.7 = STATE hlACHINE STATUS
1 = Multi Word/byte Write available
0 = Multi Word/byte Write not available
XSR.QO=RESERVED
After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.
FOR FUTURE ENHANCEMENTS
XSR.B-0 is reserved for future use and should be masked
out when oolline the extended status register.
SHARP
Table 8.
ID246 SERIES PRODUCT OVERVIEW
14
Identifier Codes / Block Status
Select Device-pair
k%1
Manufacture Identifier
Code
DPA
Device Identifier Code
DPA
Block Status Code
DPA
Address in Device
hiA,
ooooOh
OCOOlh
00002h
00003h
XOOO4h
XOOO5h
(X: Select Block)
Even/Odd
A0
0:Even
1:Odd
0:Even
1:Odd
0:Even
1:Odd
NOTE: A,, is ignored in word access mode, and D,5-D, outputs the Odd byte data.
DPA: Address as select device pair
BLKD: Block Lock Configuration Data
MLKD: Master Lock Configuration Data
Data Output D,-D,
32MB ,4OMB, 48MB
BOh
DOh
Block Status Code
D,: O=Unlocked, l=Locked
D,: O=Last Erase operation
completed successfully
l=Last Erase operation did
not completed successfully
D,-D,: Reserved
Tl 1MEOl
SHARP
ID246 SERIES PRODUCT
9. Component
Management
Registers
Component Management Registers (CMR)
OVERVIEW
(CMR)
are mapped at even byte locations beginning at address 4000h in
attribute memory.
9. 1
Configuration
Option Register
Bit.6
Address
Bit.7
4000h
SRESET
SRESET:
9. 2
Card Configuration
Address
(Address:4000h)
Bit.4
Bit.3
Bit.5
Bit.4
Bit.3
Reserved
Bit. 1
Bit.0
Reserved
l=Power-Down
Device pairs that apointed by Sleep Control Register(4118h-411 Ah) are in PowerDown.
O=Power-Up
Socket and Copy Register
4006h
Bit.2
PWDN
Reserved
Bit.7
Bit.0
(Address:4002h)
Bit.6
Bit.7
Address
Bit. 1
l=Reset State O=End Reset Cycle
Register
PWDN:
Bit.2
Reserved
4002h
9. 3
Bit.5
(Address:4006h)
Bit.6
Bit.5
Bit.4
Bit.3
Bit.2
Bit.1
Bit.0
Soket No.
Copy No.
Soket No.: Socket Number
Copy No.: Copy Number
I
9. 4
The card may use to distinguish between similar cards installed in a system.
TlOL-01
Card Status Register
(Address:41
Address
Bit7
Bit.6
4100h
ADM
ADS
OOh)
Bit.5
Bit.4
Bit.3
Bit.2
Bit.1
Bit.0
SRESET
CMWP
PWDN
CISWP
WP
RDYIBSY
ADM: ORed value of the Ready/Busy Mask Register.
1 = Any device is masked. 0 = All Devices are not Masked.
ADS: ORed value of the Sleep Control Register.
1 = Any device-pair is Controled power-down by bit.2 of the Card Configuration
Register.
SRESET: Reflects the bit.7 of the Configuration Option Register.
CMWP: Reflects the bit.1 of the Write Protection Register.
PWDN: Reflects the bit.2 of the Card Configuration Register.
CISWP: Reflects the bit.0 of the Write Protection Register.
WP: Indicates the Write Protect Switch status.
1 = Write Protect Switch: ON 1 = Write Protect Switch: OFF
RDY/BSY: Reflects the Ready/Busy StatusRegister.
1 = All devices are READY. 0 = Any device is BUSY.
TIO54-01
SHARP
9. 5
ID246 SERIES PRODUCT OVERVIEW
Write Protection Register
Address
Bit.7
(Address:41
04h)
Bit.6
Bit.5
4104h
Bit.4
Bit.3
Reserved
16
Bit.2
Bit. 1
BLKEN
CMWP
Bit.0
CISWP
BLKEN:
Block Locking Enable
1 = Enable Block Locking
0 = All Block Unlocked
Common Memory Write Protect
CMWP: 1 = Common Memory without CIS region in Write Protect Status
Common Memory CIS Write Protect
CISWP: 1 = Common Memory CIS in Write Protect Status
TI 176E4l
9. 6
Sleep Control Register
Address
(Address:41
Bit.7
18h-411 Ah)
Bit.6
Bit.5
Bit.4
411Al-l
4118h
Bit.3
Bit.2
Bit. 1
Bit.0
DEV4/5
DEV2J3
DEVO/l
Reserved
Reserved
DEV 10/l 1
DEV8/9
DEV6/7
l= Select sleep mode device-pair
If set to “I”, the corresponding device-pairs are putted into deep powerdown
by PWDN bit of Configuration Status Register.
mode
TIW741
9. 7
Ready/Busy
Address
Mask Register
(Address:41
Bit.6
Bit.7
4122h
4120h
20h-4122h)
Bit.5
Bit.4
Reserved
DEV7
DEV6
DEVS
1 DEV4
Bit.3
Bit.2
Bit.1
Bit.0
DEVll
DEVlO
DEV9
DEV8
DEV3
DEV2
DEVl
DEVO
1 =Mask the Rdy/Bsy#
The corresponding device’s Rdy/Bsy# signals to set bit are ignored for cards
RDY/BSY# output.
9. 8
Ready/Busy
Address
Status Register
Bit.7
(Address:41
Bit.6
413231
4130h
30h-4132h)
Bit.5
Bit.4
Reserved
DEV7
DEV6
DEVS
DEV4
Bit.3
Bit.2
Bit. 1
Bit.0
DEVI 1
DEVIO
DEV9
DEV8
DEV3
DEV2
DEVl
DEVO
l=READY
O=BUSY
Each bit indicates the corresponding device’s Rdy/Bsy# signal.
TlOIlOl
9.9
Ready/Busy
Address
Mode Register
Bit.7
4140h
(Address:41
Bit.6
40h)
Bit.5
Reserved
RACK:
MODE:
Bit.4
Bit.3
Bit.2
Bit.1
Bit.0
RACK
MODE
Ready Acknowledge Bit
Must clear this bit after receiving ready status to prepare for next device’s ready
transition.
RDY/BSY# Mode
1 = High-Performance Mode 0 = PCMCIA Mode
TIMSOL
SHARP
10.
ID246 SERIES PRODUCT OVERVIEW
Command
Definitions
Device operations are determined by writing specific commands to the Command User Interface. Table 9 defines
the commands.
Table 9. Command Definitions
Read
Identifier
Word/Byte
Codes
Write
Level-Mode
for Erase
(RY/BY#
Mode)
STS Configuration
Pulse-Mode
for Erase
and
STS Configuration
Pulse-Mode
for Write
STS Configuration
Pulse-Mode
for Erase
and
Write
Write
write
DA
Write
DA
Write
DA
B8h
(BSBSh)
B8h
(BSBSh)
B8h
(BSBSh)
Write
DA
Write
DA
Write
DA
Olh
(OlOlh)
02h
(0202h)
03h
(0303h)
T115oE-m
Data
Address
IA
=Identifier
ID
=IdentiIier
WA
=Write
Address
WD
=Write
BA
=Block
Address
SRD
=Data
QA
=Quety
DA
=Device
QD
=Data
cede
Address
Address
read
Codes
Data
from
Offset
Status
Register
Address
from Query database
Note:
the Read Identifier
Codes command, read operations access manufacture, device, block status
codes.
2. Status Register may be read to determine when a write, block erase, or lock bit configuration
is complete,
and whether that operation completed successfully.
3. If the block is locked, block erase or write operations are desabled.
1. Following
4. Following
command
the Third
‘DOH’.
Bus Cycle,inputs
the write address and write data of ‘N’+l
times.Finally,
input the confirm
CP%008E40
SHARP
10.1
ID246 SERIES PRODUCT
OVERVIEW
Query Command
Query database can be read by writing Query comman d (98H). Following
address shown in Table 1 l-15 retrievethe critical information
the command write, read cycle from
to write, erase and otherwise control the flash
component.
In word mode, Ds-Dis output the Query data of odd Byte Devices.
Table 10.
Example of Query Structure Output
T
Offset Address
A0
(A6 - Al)
A,, A,, A,, A,, A,, A,
X8 mode
1 , 0 , 0 , 0 , 0 , 0 (20H)
1 , 0 , 0 , 0 , 0 , l(21H)
1 ,o,o,o,
1 ,oGw
1,0,0,0,1,1(23H)
0 = Even
1 = Odd
A,, A,, A,, A,, A,
l,O,O,O,O
(10H)
1 ,O,O,O,l
(11H)
Xl6 mode
X
output
I
%-D*
D,-Do
High-z
“Q”
“Q”
High-Z
High-Z
High-Z
“Q”
“R”
“R”
“R”
“Q”
“R”
TllSZE-01
10. 1. 1 Block Status Register
This field provides lock configuration and erase status for the specified block. These informations are only available when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase
status bit will be set to “l”,this
Table 11.
block is invalid.
Query Block Status Register
Offset
(Word Address)
(B A+2)H
NOTE: l.BA=The
Description
Length
OlH
Block Status Register
DO : Block Lock Configuration
O=Block is unlocked
l=Block is locked
Dl : Block Erase Status
O=Last erase operation completed successfully
l=Last erase operation not completed successfully
D2-7: Reserved for future use
beginning of a Block Address.
T1153E41
SHARI=
10. 1.2
ID246 SERIES PRODUCT
CFI Query Identification
The Identification
OVERVIEW
19
String
String provides verification that the component supports the Common Flash Interface specifi-
cation. Additionally,
If indicates which version of the spec and which Vendor-specified
command set(s) istare)
supported.
Table 12.
CR Query Identification
Offset
(Word Address)
String
Length
Description
lOH.1 lHJ2H
03H
Query Unique ASCII string “QRY”
5 lH,52H,59H
13H,14H
02H
Primary Vendor Command Set and Control Interfase ID Code
OlH,OOH (SCS ID Code)
15HJ6H
02H
Addressfor Primary Algorithm Extended Query Table
3 lH,OOH (SCS Extended Query Table Offset)
17HJ8H
02H
I9HJAH
02H
Alternate Vendor Command Set and Control Interfase ID Code
OOOOH (OOOOH means that no alternate exists)
Address for Alternate Algorithm Extended Query Table
OOOOH (OOOOH means that no alternate exists)
T1154E-01
10. 1. 3 System Interface Information
The following device information can be useful in optimizing systeminterface software.
Table 13. SystemInformation String
Offset
(Word Address)
Description
Length
IBH
OlH
V,, Logic Supply Minimum
27H (2.7V)
.
I
Write/Erase voltage
LCH
OlH
IDH
OlH
LEH
OlH
FH
OlH
!OH
OlH
!lH
OlH
!2H
OlH
!3H
OlH
!4H
OIH
!5H
OIH
V, Logic Supply Maximum Write/Erase voltage
55H (5.5V)
V, Programming Supply Minimum Write/Erase voltage
27I.I (2.7V)
V, Programming Supply Maximum Write/Erase voltage
55H (5.5V)
Typical Timeout per Single Byte/Word Write
03H (23=8 usec)
Typical Timeout for Maximum Size Buffer Write (32 Bytes)
03H (2%4 usec)
Typical Timeout per Individual Block Erase
OAH (OAH=lO , 2i”=1024 msec)
Typical Timeout for Full Chip Erase
OFH (OFH=15 , 2iJ=32768 msec)
Maximum Timeout per Single Byte/Word Write, 2N times of typical
04H (r=16 , 8 usec x16=128 usec)
Maximum Timeout Maximum Size Buffer Write, 2N times of typical
04H (24=16, 64 usec x16=1024 usec)
Maximum Timeout per Individual Block Erase, 2N times of typid
04H (2’=16, 1024 msec x16=16384 msec)
:6H
OlH
I
Maximum Timeout for Full Chip Erase, 2N times of typical
04H (24=16, 32768 msec x16=524288 msec)
T1155E.01
L
SHARP
10. 1. 4
ID246 SERIES PRODUCT OVERVIEW
Device Geometry
20
Definition
This field provides critical details of the flash device geometry.
Table 14. Device Geometry Definition
Offsel
(Word
Address)
Length
Description
I
OlH
Device Size
15H (15H=21,22’=2097152=2M
28H. 29H
02H
Flash Device Interface description
02H,OOH (x8/x16 supports x8 and xl6 via BYlE#)
2Ali.
02H
Maximum
Number of Bytes in Multi word/byte
05H.OOH (2’=32 Bytes)
Number of Erase Block Regions within device
01 H (symmetricatly
blocked)
2lH
2BH
Bytes
write
2CH
OlH
2DH, 2EH
02H
Tbe Number of Erase Blocks
lFH,OOH (lFH=31
=>31+1=32
02H
The Number of “256 Bytes” cluster in a Erase block
00H,OlH
(OlOOH=256
=>256
Bytes x 256=643 Bytes in a Erase Block)
T1?5641
2FH. 30H
Blocks
10. 1. 5 SCS OEM Specific Extended Query Table
Certain flash featuresand commandsmay be optional in a vendor-specific algorithm specification. The optional
vendor-specific Query table(s) may be usedto specify this and other types of information. Thesestructuresare
defined solely by the flash vendor(s).
Table 15. SCS OEM Specific Extended Query Table
(Word
offset
Address)
Description
Length
OlH
PRI
50H, 52H, 49H
3 1 H (1) Major Version
Number
, ASCII
OlH
30H (0) Minor
Number,
ASCII
36H. 37H. 38H. 39H
04H
OFH, OOH, OOH, COH
Optional Command support
bitO=l
: Chip Erase Supported
bitl=l
: Suspend Erase Supported
b&2=1 : Suspend Write Supported
bit3=1 : Lock/Unlock
Sqported
bit4=0 : Queued Erase. Not Supported
bit5-31=0
: reserved for future use.
3AH
OIH
OlH
Supported Functions after Suspend
bitO=l
: Write Supported after Erase Suspend
bit l-7=0 : reserved for future use
3BH, 3CH
02H
03H, OOH
Block Status Register Mask
bitOr
: Block Status Register Lock Bit (BSR.01 active
bitl=l
: Block Status Register Valid Bit [BSR.l] active
biQ-15=0
: reserved for future use
3DH
OlH
Vcc Logic Supply
50H (5.OV)
Optimum
3EH
OlH
V, Progr amming
performance)
50H (5.OV)
Supply
3FH
reserved
3lH,32H,33H
03H
34H
35H
Reserved
Version
for future
Write/Erase
Optimum
voltage (highest
Write/Erase
performance)
voltage (highest
versions of the SCS Spccitication
rrrm-ot
SHARP
ID246 SERIES PRODUCT OVERVIEW
10. 2 STS Configuration
The RDY/BSY#
21
Command
pin can be configured to different states using the STS Configuration command. Once the RDYI
BSY# pin has been configured, it remains in that configuration until another configuration command is issued, the
device is powered down or card is reset. Upon initial power-up and after exit from deep power-down
RDY/BSY#
mode. the
pin defaults to RY/BY# operation where STS low indicates that the WSM is busy. STS high indicates
that the WSM is ready for a new operation.
To reconfigure the RDY/BSY#
pin to other modes, the STS Configuration is issued followed by the appropriate
configuration code. The three alternate configurations
Table 16. STS Configuration
are all pulse mode for use as a system interrupt.
Coding Description
Effects
Set STS pin to default level mode (RY/BY#). RY/BY# in the default level-mode of
operation will indicate WSM status condifion.
Set STS pin to plused output signal for specific erase operation. In this mode, STS
provides low pulse at the completion of Block Erase,Full Chip Erase and Clear Block
Lock-bit ooeration.
Set STS pin to pulsed output signal for a specific write operation. In this mode, STS
provides low pulse at the completion of (multi) Byte Write and Set Block Lock-bit
operation.
Set STS pin to pulsed output signal for specific write and erase operation.STS provides low
pulse at the completion of Block Erase, Full Chip Erase, (Multi) Word/Byte Configuration
operations.
T1158E-01
Table 17. Write Protection Alternatives
Operation
I
Block Erase,
(Multi) Word/Byte
Write
Block
Lock-Bit
0
1
Full Chip Erase
CL1
Set Block Lock-Bit
X
X
Clear Block Lock-Bits
X
L
BLKEN bit of Write
Protection Resister
h
I
I
Effect
I
1Block Erase and (Multi) Word/Byte Write
Enabled.
1Block is Locked. Block Erase and (Multi)
Word/Byte Write Disabled.
Block Lock-Bit Override. Block Erase and
(Multi) Word/Byte Write Enabled.
All unlocked blocks are erased, lockd blocks are
not erased.
All Block Lock-Bit Disabled.
Set Block Lock-Bit Disabled.
Set Block Lock-Bit Enabled.
Clear Block Lock-Bit Disabled.
Clear Block Lock-Bit Enabled.
T1159E01
SHARP
11.
ID246 SERIES PRODUCT
Electrical
11. 1 Absolute
OVERVIEW
22
Specifications
Maximum
Ratings
PARAMETER
r
Supply Voltage
1Program Voltage
NOTE
2
2
~Input Voltage
Operating Temperature
1Storage Temperature
1
2
1
RATING
-0.3 to 6.0
-0.2 to 7.0
SYMBOL
V cc
V PP
UNIT
V
V
V
‘C
‘c
T1165E41
-0.3 to Vcc+0.3(Max:6.0)
0 to 60
-20 to 65
vm
T OPFC
TSTG
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. All specified voltages are with respect to GND. During transitions, this level may undershoot to -2.0~ for
periods c20ns or overshoot to Vcc+2.Ov for periods <20ns.
11.2
Recommended
Operating
Coriditions
T1177E-01
11. 3 Capacitance
Ta=25 “c , f= 1MHz
PARAMETER
11.4
SYMBOL
MIN
TYP
MAX
UNIT
CONDITION
Input Capacitance
GIN
-
15
-
PF
v,,=o.ov
Input/Output Capacitance
50
-
25
-
PF
vo,=o.ov
AC Input/Output
Test Conditions
Figure 5. Transient Input/Output Reference Waveform
Figure 5 shows Input/Output level and test level for AC test. Input rise and fall times (10% to 90%) < Ions.
ID246 SERIES PRODUCT
OVERVIEW
23
12. DC Characteristics
(Ta=Oto6O”C)
PARAMETER
TEST CONDITION
Output High Voltage
Vcc Read Current
(Continue
to next page)
T1166E.01
SHARP
DC Characteristics
ID246 SERLES PRODUCT
OVERVIEW
24
(Continued)
(Ta = 0 to 60°C)
SYMBOL
TEST CONDITION
V, Stand-by or Read
V, DeepPower-Down
Current
V,, Word Write or Set
Lock-Bit Current
V,, Block Eraseor
ClearLock-Bit Current
V, Word Write or
I
Block EraseSuspend PPWS 6
4PES
Current
V,, LockoutVoltage
40MB
520
520
,uA
48MB
5.50
550
,u A
32MB
1.6
mA
40MB
48MB
2.0
mA
2.4
mA
V
78
-EL!5
1.5
1.5
V&Vcc
v+vcc
v
Tl lC7E-01
NOTE:
1. Theseparametersare applied to all input pins and all input/output pins in input mode.
2. Theseparametersare applied to AO-&
and D,-Dn in input mode and RESET.
3. Theseparametersare applied to CE,#,CE,#,WB#,OE# and REG#.
4. Theseparametersare applied to RDY/BSY#.
5. Theseparametersare applied to D,-DrS in output mode.
6. All currentsare in RMS unlessotherwise notes.
7. Block erase,word/byte write, and lock-bit configurations are inhibited when V,s
the V, Voltage is Vpp,, or V,.
V,,,
and guaranteedin
8. Sampled.
CPS0008E-00
SHARP
ID246 SERIES PRODUCT
25
OVERVIEW
13. AC Characteristics
Testing Conditions :
1.5 to 3.5v (@vcc=5vk5%,vcc=5v~lo%)
1) Input Pulse Level
0 to 3.ov (@Vcc=3.3kOo.3V)
2) Input Rise/Fall Time
1Ons
3) Input/Output Timing Reference Level
2.5V (@Vcc=5V+5%,Vcc=5V+1oQ)
1.5v (@Vcc=3.3V&.3V)
I-I-l-L,+lOOpF ( @VCC=~V+~%,VCC=~V~IO%)
4) Output Load
(including scope and jig capacitance)
13. 1 Common
,
Memory
Il-I-L+SOpF (@Vcc=3.3V+O.3V)
Read Operations
---- -BOL
(Ta = 0 to 60°C)
vcc=3.3v+
0.3v
Vcc=SVk
5% 1 vcc=sv
+ 10%
[Jnit
ns
*:Time until output becomes floating. (The output voltage is not defined.)
TlC43-01
SHARP
ID246 SERIES PRODUCT OVERVIEW
tFl
1
*
Address
t(A)
w
e
*
b(A)
w
/
CE#, CE2#
\
/
4
////
to3
OE#
Dout
Figure 6. AC Waveforms for ReadOperations
Note) 1. WE# = “HIGH”, during a read cycle.
2. Either “HIGH” or “LOW” in diagonal areas.
3. The output data becomesvalid when last interval, ta (A), ta (CE) or ta (OE) have concluded.
SHARP
13.2
ID246 SERIES PRODUCT
Command
Write Operations
13. 2. 1 WE# Controlled
: Common
27
OVERVIEW
Memory
Write Operations
(Vcc=3.3VrtD.3\I, Ta=Oto 60°C)
PARAMETER
Write Cycle Time
SYMBOL
IEEE 1
PCMCIA
t*“A-J trW
CONDITION
I
I
Address Setup Time
vcc=3.3v -tn.“.a?Vv
MIN
I
MAX
Unit
250
ns
30
ns
Write Recovery Time
Data Setup Time for WE#
Data Hold Time
OE# Hold Time from
WE#
CE# Setup Time for WE#
Address
WE#
Setup Time for
Write Pulse Width
WE# High to RDY/BSY#
going Low
RESET Recovery Time
V, Setun Time
V, Hold Time
Word/Byte
Write Time
Block Erase Time
Set Lock-Bit
Time
Clear Block Lock-Bits
Time
V,,=3.3VkO.3%
fwHQ”4
Word/Byte Suspend
Latency
$IHRHI
Time to Read
Erase Suspend Latency Tie
to Read
v,,=5v+lo%
10.0
S
V,,=3.3V~.3%
10.0
PS
9.3
/IS
vPP=3.3vti.3%
21.1
PS
v,*=5v *lo%
17.2
v,,=w
*lo%
P’s
T1168E-01
SHARP
ID246 SERIES PRODUCT
OVERVIEW
(Vcc=SVfi%,
PARAMETER
Vcc=5V+lO%,,
Ta = 0 t 60°C )
~Unit
~ ns
1 ns
ns
ns
ns
OE# Hold Time from
ns
ns
ns
ns
ns
P’s
ns
ns
PS
S
PS
Clear Block Lock-Bits
S
Erase Suspend Latency Tie
to Read
1169E-01
CPSCW~E~IO
SHARP
ID246 SERIES PRODUCT
t 1
I
Vu Wkl
VU
OVERVIEW
I
th(oE-w-l!)
WHQVLZ.3.4
VIII
\
u
3
,
I-
VU
DATA
VU
WtIRHI.2
VOH
RDY/BSY#
E -4
RESET
VU
I
/
h
I
I
I
VW12
VPP
VU
1.
2.
3.
4.
5.
6.
V,. POWER-UP
AND STANDBY
WRITE DATA WRITE OR ERASE SETUP COMMAND
WRITE VALID
ADDRESS
AND DATA OR ERASE COMFIRM
AUTOMATED
DATA WRITE OR ERASE DELAY
READ STATUS REGISTER
DATA
WRtTE READ ARRAY
COMMAND
COMMAND
FIOIC-03
Figure 7.
Note)
AC Waveforms
for Write Operations (WE# Controlled)
While the data signalis in output mode, do not apply an oppositephaseinput signal.
SHARP
13. 2. 2 CE# Controlled
ID246 SERIES PRODUCT
OVERVIEW
Write Operations
(Vcc=3,3V ti.3V,
Ta = 0 to 60°C )
Erase Suspend Latency Tie
T1170E-01
SHARP
31
ID246 SERIES PRODUCT OVERVIEW
PARAMETER
IEEE
I’“VIIBOL
‘Yb
--_ _--.
Write Cycle Time
t A”.%”
AddressSetup Time
t
Write Recovery Time
LIZ
bvEH
Data Setup Time for CE#
KMCIA
Data Hold Time
&HDx
OE# Hold Time from CE# acL
Write Pulse Width
b.EH
CE# High to RDY/BSY#
going LO*
_
hHRL
I
Clear Block Lock-Bits
Time
Word/Byte Suspend Latency
Time to Read
Erase Suspend Latency Tie
to Read
I kHQV.4
LRHl
(Vcc=SV Y%, Vcc=SV MO%, Ta=Oto 60°C )
vcc=sv +-lo%
vcc=sv Y%
CONDITION
Unit
. I...
. I. wr
. . ..I
I,..,
I
W)
I
t (cm
I
1
80
1
-
1
80
I
-
I
ns I
1 - ( 1401 - 1 1401 ns 1
I
v,=w
*lo%
-
7.0
-
7.0
p s
v,,=5v *lo%
-
13.1
-
13.1
#us
T1171EQl
SHARP
32
ID246 SERIES PRODUCT OVERVIEW
1.
2.
Address
3.
4.
5.
AIN
WE#
VIL
tdA)-
VIII
I
b
MOE-C’3
VIII
4
OEX
VU
hWE-CEH)
i)-
e
lEHQVI.23.4
hi
31#,
cm
VU.
I
VOH
tDYlJsY#
I
I
VOL
VIII
RESET
VLL
VPPl.2
VPP
VU
1.
2.
3.
4.
5.
6.
Vcc POWER-UP
AND STANDBY
WRITr
DATA WRITE OR ERASE SETUP COMMAND
WRITE
VALID
ADDRESS
AND DATA OR ERASE COhtFlRh4
AUTOMATED
DATA WRlTE OR ERASE DELAY
READ STATUS REGISTER
DATA
WRITE READ ARRAY
COMMAND
Figure 8.
COMMAND
AC Waveforms for Write Operations (CE# Controlled)
Note) While the data signal is in output mode, do not apply an opposite phase input signal.
6.
SHARP
ID246 SERIES PRODUCT
OVERVIEW
33
13. 3 Attribute Memory Read Operation
(Ta=O-60°C)
SYMBOL
PARAMETER
IEEE
Read Cycle Time
PCMCIA
tAVAV
t *w-w
Address Access Tie
CE# Access Time
~tm.Qv
fGLQV
OE# AccessTime
Output DisableTime from CEl#,CE2# *
t
Output DisableTime from CE#
t
Output DisableTime from CE 1#,CE2#
Output DisableTime from OE#
Data Valid Tie from AddressChange
Vcc=3.3Vf
Ew2
GHPZ
fn ON7
tcR
MIN
600
MAX
-
L(A)
-
600
wm
-
WEI
vcc=sv
AZ 10%
MM
300
MAX
-
-
300
600
-
300
I
-
300
-
150
fdir(CE)
-
150
-
100
MOE)
-
150
-
100
Mm
5
-
5
-
i t&9
1
0.3v
I
IOI-Iol-I
I
I
I
I
* : Tie until becomes
floating.(Theoutputvoltageis notdefined)
Unil
ns
I
T1056-G
Note) When the CIS constructedby EEPROM, this card requires 5V voltage for Vcc.
Address
CEl#, CE2#
/
OE#
/
I
L&E) 4
Dout
I
ta(OE)
,.j
)
tdis(OE)._
*
hiiKE)
DataOutputisvalid
High-Inpedance
Figure 9.
\\)
/I/
Attribute Memory Read Operation
CPSCWXE-001
SHARP
ID246 SERIES PRODUCT
OVERVIEW
34
13. 4 Attribute Memory Write Operation
(Ta=O-60°C)
SYMBOL
IEEE
t
AVAV
1
PCMCIA
I
t
vcc=3.3v f 0.3v
I
MIN
MIN
1070
1I MAX
Unit
1I MAX
I
1
-
1 250
-
ns
70
150
-
30
80
-
ns
ns
70
-
30
-
150
-
1 600
CW
vcc=5vt
I
i Address Setup Time
~Write Recovery Time
1data Setup Time
i Data Hold Time
LlAx
L(WE)
t DVWH
L UnY
‘[email protected])
[email protected])
/Address SetupTime for WE#
1Write Pulse Width
Setup Time for OE#
Hold Tie for OE#
Setup Tie for CE#
Hold Time for CE#
T1057.01
Note) When the CIS constructed by EEPROM, this card requires 5V voltage for Vcc.
Address
CEl#, CE2#
OE#
WE#
DATA
F1057-01
Figure 10. Attribute
Memory Write Operation
I
SHARP
13.5
ID246 SERIES PRODUCT OVERVIEW
Power-Up/Power
Down
SYMBOL
PARAMETER
CE# Signal Level (O.OV < Vcc < 2.OV)
PCMCIA
NOTES
Vi (CE)
/
MIN
/
MAX
/
UNITS
1
0
ViMAX
V
CE# Signal Level (2.OV c Vcc c VIH)
1
vcc-o. 1
Vih4AX
V
CE# Signal Level (VIH c Vcc)
1
VU4
Vih4AX
V
CE# Setuo Time
L” WCC)
-
20
-
ms
RESET SetupTime
tsu(RESET)
-
20
-
ms
tb (Hi-Z RESET)
-
1
-
ms
0
-
ms
/
CE# Recover Time
VCC Rising Time
VCCFalling Time
RESET Width
RESET Width
RESET Width
ts (Hi-Z RESET)
-
NOTES:
1. VM~ meansAbsolute Maximum Voltage for input in the period of O.OV < Vcc < 2.0 V, Vi (CE#) is only
o.oov-v&fAx
2. The tDrand tpf are defined as “linear waveforms” in the period of 10% to 9010, or vice-versa. Even if the
waveform is not a “liner waveform,” its rising and falling ime must meet this specification.
---
tsu (RESET)
=
t,,(Hi-z RESET)
Hi-Z-----------
3E1#
yz5jK-J
ts(Hi-Z RESET)
-------------_
Hi-Z
F1012-01
Figure Il.
Power-Up/Down Timing
i
SHARP
14. Specification
ID246 SERIES PRODUCT OVERVIEW
Changes
This datasheet is for ID246 series product overview, and final specifications will be submitted for qualification of
the memory card. Please note that contents of this datasheet may be revised without announcement beforehand.
Please do NOT finalize a system design with this information.
15. Other Precautions
. Permanent damage occurs if the memory card is stressed beyond Absolute Maximum
beyond the Recommended
Ratings. Operation
Operating Conditions is not recommended and extended exposure beyond the
Recommended Operating Conditions may affect device reliability.
. Writing to the memory card can be prevented by switching
on the write protect switch
on the end of the
memory card.
. Avoid allowing the memory card connectors to come in contact with metals and avoid touching the connectors, as the internal circuits can be-damaged by static electricity.
+ Avoid storing in direct sunlight, high temperatures (do not place near heaters or radiators), high humidity and
dusty areas.
.
Avoid subjecting the memory card to strong physical abuse. Dropping, bending, smashing or throwing the
card can result in loss of function.
.
When the memory card is not being used, return it to its protective case.
.
Do not allow the memory card to come in contact with fire.
SHARP
ID246 SERIES PRODUCT
OVERVIEW
-
0A
ENLARGEMENT
WR
OF
I TE-PROTECT
THE
SW ITCH
I
16. External
Diagrams
Back
t68
935
6kO.l
onncc
Area)
3.
1.
b,,
50.
II -
8
”
.
_I.
C
3 f0.
t
Protected
\
1 w
50.
1.
8
6
II
I
(Substrate
Area)
(fubrtrate
Area)
4
n
a
-
1.
1
51.
8
I
\&
\2-R2
51.
cS"b¶trOtc
Area)
BACK
FRONT
1.
TIIICKNESS
8
tlATERIAL
51 II I
FINISH
41.
MEMORY
NAME
EXTERNAL
3
CAR0
DIAGRAM
CPSWOGE-00