SHARP LH28F008SC

LH28F008SC
FEATURES
8M (1M × 8) Flash Memory
42-PIN CSP
TOP VIEW
• High-Density Symmetrically-Blocked
Architecture
– Sixteen 64K Erasable Blocks
• High-Performance
1
2
3
4
5
6
7
A
A5
A8
A11
VPP
A12
A15
A17
B
A4
A7
A10
VCC
A13
NC
A18
C
A6
A9
RP
CE
A14
A16
A19
D
A3
DQ1
NC
VCC
DQ4
DQ7
NC
E
A2
A0
DQ3
GND
DQ6
OE
NC
F
A1
DQ0
DQ2
GND
DQ5
RY/BY
WE
– 85 ns Read Access Time
• Enhanced Automated Suspend Options
– Byte Write Suspend to Read
– Block Erase Suspend to Byte Write
– Block Erase Suspend to Read
• Enhanced Data Protection Features
– Absolute Protection with VPP = GND
– Flexible Block Locking
– Block Erase/Byte Write Lockout during
Power Transitions
28F008SC-20
Figure 1. CSP 42-Pin Configuration
• Extended Cycling Capability
– 100,000 Block Erase Cycles
– 1.6 Million Block Erase Cycles/Chip
• Low Power Management
– Deep Power-Down Mode
– Automatic Power Saving Mode Decreases
ICC in Static Mode
• Automated Byte Write and Block Erase
– Command User Interface
– Status Register
40-PIN TSOP
TOP VIEW
A19
1
40
NC
A18
2
39
NC
A17
3
38
WE
A16
4
37
OE
A15
5
36
RY/BY
A14
6
35
DQ7
A13
7
34
DQ6
A12
8
33
DQ5
• SmartVoltage Technology
CE
9
32
DQ4
– 3.3 V or 5 V VCC
– 3.3 V, 5 V, or 12 V VPP
VCC
10
31
VCC
VPP
11
30
GND
• SRAM - Compatible Write Interface
• ETOX™ V Nonvolatile Flash Technology
• Industry - Standard Packaging
– 42-Pin, .67 mm × 8 mm2 CSP Package
– 40-Pin, 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
– 44-Pin, 600-mil, SOP Package
RP
12
29
GND
A11
13
28
DQ3
A10
14
27
DQ2
A9
15
26
DQ1
A8
16
25
DQ0
A7
17
24
A0
A6
18
23
A1
A5
19
22
A2
A4
20
21
A3
28F008SC-1
Figure 2. TSOP 40-Pin Configuration
1
LH28F008SC
8M (1M × 8) Flash Memory
44-PIN SOP
TOP VIEW
VPP
1
44
VCC
RP
2
43
CE
A11
3
42
A12
A10
4
41
A13
A9
5
40
A14
A8
6
39
A15
A7
7
38
A16
A6
8
37
A17
A5
9
36
A18
A4
10
35
A19
NC
11
34
NC
NC
12
33
NC
A3
13
32
NC
A2
14
31
NC
A1
15
30
WE
A0
16
29
OE
DQ0
17
28
RY/BY
DQ1
18
27
DQ7
DQ2
19
26
DQ6
DQ3
20
25
DQ5
GND
21
24
DQ4
GND
22
23
VCC
28F008SC-2
Figure 3. SOP 44-Pin Configuration
INTRODUCTION
SHARP’S LH28F008SC FlashFile™ memory with
SmartVoltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of
applications. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs
and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code and data storage applications. For secure code storage applications, such as
networking, where code is either directly executed out of
flash or downloaded to DRAM, the LH28F008SC offers
three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate
control of their code security needs.
The LH28F008SC is manufactured on SHARP’s
0.4 µm ETOX™ V process technology. It comes in industry-standard packages: the 40-pin TSOP, ideal for
board constrained applications, and the rugged 44-pin
SOP. Based on the 28F008SA architecture, the
LH28F008SC enables quick and easy upgrades for
designs demanding the state-of-the art.
2
New Features
The LH28F008SC SmartVoltage FlashFile memory
maintains backwards-compatiblity with SHARP’S
28F008SA. Key enhancements over the 28F008SA
include:
• SmartVoltage Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
Both devices share a compatible pinout, status register, and software command set. These similarities
enable a clean upgrade from the 28F008SA to
LH28F008SC. When upgrading, it is important to note
the following differences:
• Because of new feature support, the two devices
have different device codes. This allows for software optimization.
• VPPLK has been lowered from 6.5 V to 1.5 V to
support 3.3 V and 5 V block erase, byte write, and
lock-bit configuration operations. Designs that
switch VPP off during read operations should make
sure that the VPP voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow VPP connection to 3.3 V or 5 V.
DESCRIPTION
The LH28F008SC is a high-performance 8M SmartVoltage FlashFile memory organized as 1M of 8 bits. The
1M of data is arranged in sixteen 64K blocks which are
individually erasable, lockable, and unlockable in-system.
The memory map is shown in Figure 5.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in the Voltage Combinations Table, to meet system performance and power
expectations. 3.3 V VCC consumes approximately onefourth the power of 5 V VCC. But, 5 V VCC provides the
highest read performance. VPP at 3.3 V and 5 V eliminates the need for a separate 12 V converter, while
VPP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data
protection when VPP ≤ VPPLK.
VCC and VPP Voltage Combinations
Offered by SmartVoltage Technology
VCC VOLTAGE
VPP VOLTAGE
3.3 V
3.3 V, 5 V, 12 V
5V
5 V, 12 V
8M (1M × 8) Flash Memory
LH28F008SC
DQ0 - DQ7
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
OUTPUT
MULTIPLEXER
STATUS
REGISTER
I/O LOGIC
DATA
REGISTER
DATA
COMPARATOR
A0 - A19
Y-GATING
INPUT
BUFFER
RP
COMMAND
REGISTER
CE
WE
OE
RP
WRITE STATE
MACHINE
RY/BY
Y-DECODER
X-DECODER
...
ADDRESS
LATCH
16 64KB BLOCKS
ADDRESS
COUNTER
PROGRAM/
ERASE
VOLTAGE
SWITCH
VPP
VCC
GND
28F008SC-3
Figure 4. LH28F008SC Block Diagram
Internal VCC and VPP detection Circuitry automatically configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written
to the CUI initiates device automation. An Internal Write
State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write,
and lock-bit configuration operations.
A block erase operation erases one of the device’s
64K blocks typically within 1 second (5 V VCC, 12 V VPP)
independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases
per device). Block erase suspend mode allows system
software to suspend block erase to read or write data
from any other block.
Writing memory data is performed in byte increments
typically within 6 µs (5 V VCC, 12 V VPP). Byte write suspend mode enables the system to read data or execute
code from any other flash memory array location.
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock and
unlock blocks. Block lock-bits gate block erase and byte
write operations, while the master lock-bit gates block
lock-bit modification. Lock-bit configuration operations
(Set Block, Lock-Bit, Set Master Lock-Bit, and Clear
Block Lock-Bits commands) set and cleared lock-bits.
The status register indicates when the WSM’s block
erase, byte write, or lock-bit configuration operation is
finished.
3
LH28F008SC
8M (1M × 8) Flash Memory
PIN DESCRIPTION
SYMBOL
NAME AND FUNCTION
INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
INPUT/OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
INPUT
CHIP ENABLE: Activates the device’s control logic input buffers, decoders, and
sense amplifiers. CE » high deselects the device and reduces power consumption to
standby levels.
RP »
INPUT
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP » high enables normal operation. When driven low, RP» inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP» at VHH enables setting of the
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP » = VHH overrides block lock-bits thereby enabling block erase and byte write
operation to locked memeory blocks. Block erase, byte write, or lock-bit configuration
with VIH < RP » < VHH produce spurious results and should not be attempted.
OE »
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE Pulse.
OUTPUT
READY/BUSY: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY »/BY » high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in
deep power-down mode. RY »/BY » is always active and does not float when the chip
is deselected or data outputs are disabled.
SUPPLY
BLOCK ERASE/BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, writing bytes, or configuring lock-bits. With VPP ≤ VLKO,
memory contents cannot be altered. Block erase, byte write, and lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious results and
should not be attempted.
VCC
SUPPLY
DEVICE POWER SUPPLY: Internal detection configures the device for 3.3 V or 5 V
operation. To switch from one voltage to another, ramp VCC down to GND and then
ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see DC Characteristics) produce spurious results and should not be attempted.
GND
SUPPLY
GROUND: Do not float any pins
A0 - A19
DQ0 - DQ7
CE »
RY »/BY »
VPP
NC
4
TYPE
NO CONNECT: Lead is not internal connected; it may be driven or floated.
8M (1M × 8) Flash Memory
The RY »/BY » output gives an additional indicator of
WSM activity by providing both a hardware signal of
status (versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using RY »/BY » minimizes both
CPU overhead and system power consumption. When
low, RY /» BY » indicates that the WSM is performing a block
erase, byte write, or lock-bit configuration. RY »/BY » high
indicates that the WSM is ready for a new command,
block erase is suspended (and byte write is inactive),
byte write is suspended, or the device is in deep powerdown mode.
The access time is 85 ns (tAVAV) over the commercial temperature range (0°C to +70°C) and VCC supply
voltage range of 4.75 V - 5.25 V. At lower VCC voltages,
the access times are 90 ns (4.5 V - 5.5 V) and 120 ns
(3.0 V - 3.6 V).
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static
mode (addresses not switching). In APS mode, the typical ICCR current is 1 mA at 5 V VCC.
When CE » and RP » pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP » pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP »
switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP »-high until writes
to the CUI are recognized. With RP » at GND, the WSM
is reset and the status register is cleared.
The device is available in 40-pin TSOP (Thin Small
Outline Package, 1.2 mm thick) and 44-pin SOP (Small
Outline Package). Pinouts are shown in Figures 1 and 2.
PRINCIPLES OF OPERATION
The LH28F008SC SmartVoltage FlashFile memory
includes an on-chip WSM to manage block erase, byte
write, and lock-bit configuration functions. It allows for:
100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration,
and minimal processor overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. High
voltage on VPP enables successful block erasure, byte
writing, and lock-bit configuration. All functions associated with altering memory contents–block erase, byte
write, Lock-bit configuration, status, and identifier codesare accessed via the CUI and verified through the status register.
LH28F008SC
Commands are written using standard microprocessor write timings. The CUI contents serve as input to
the WSM, which controls the block erase, byte write,
and lock-bit configuration. The internal algorithms are
regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and
data are internally latch during write cycles. Writing the
appropriate command outputs array data, accesses the
identifier codes, or outputs status register data.
Interface software that initiates and polls progress of
block erase, byte write, and lock-bit configuration can
be stored in any block. This code is copied to and executed from system RAM during flash memory updates.
After successful completion, reads are again possible
via the Read Array command. Block erase suspend allows sytem software to suspend a block. Byte write suspend allows system software to suspend a byte write to
read data from any other flash memory array location.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
64KB BLOCK
15
64KB BLOCK
14
64KB BLOCK
13
64KB BLOCK
12
64KB BLOCK
11
64KB BLOCK
10
64KB BLOCK
9
64KB BLOCK
8
64KB BLOCK
7
64KB BLOCK
6
64KB BLOCK
5
64KB BLOCK
4
64KB BLOCK
3
64KB BLOCK
2
64KB BLOCK
1
64KB BLOCK
0
28F008SC-4
Figure 4. Memory Map
5
LH28F008SC
8M (1M × 8) Flash Memory
Data Protection
Standby
Depending on the application, the system designer
may choose to make the VPP power supply switchable
(available only when memory block erases, byte writes,
or lock-bit configurations are required) or hardwired to
VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processormemory interface.
CE » at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. DQ0 - DQ7 outputs are placed in a highimpedance state independent of OE .» If deselected during block erase, byte write, or lock-bit configuration, the
device continues functioning, and consuming
active power until the operation completes.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase, byte write,
or lock-bit configuration command sequences, provides
protection from unwanted operations even when high
voltage is applied to VPP. All write functions are disabled
when VCC is below the write lockout voltage VLKO or
when RP » is at VIL. The device’s block locking capability
provides additional protection from inadvertent code or
data alteration by gating erase and byte write
operations.
BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Read
Information can be read from any block, identifier
codes, or status register independent of the VPP voltage. RP » can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read, Array, Read Identifier Codes, or Read
Status Register) to the CUI. Upon initial device powerup or after exit from deep power-down mode, the device automatically resets to read array mode. Four
control pins dictate the data flow in and out of the component: CE », OE », WE », and RP ». CE » and OE » must be
driven active to obtain data at the outputs. CE » is the
device selection control, and when active enables the
selected memory device. OE » is the data output
(DQ0 - DQ7) control and when active drives the selected
memory data onto the I/O bus. WE » must be at VIH and
RP » must be at VIH or VHH. Figure 15 illustrates a read
cycle.
Output Disable
With OE » at a logic-high level (VIH), the device otuputs
are disabled. Output pins DQ0 - DQ7 are placed in a
high-impedance state.
6
Deep Power-Down
RP » at VIL initiates the deep power-down mode.
In read modes, RP -» low deselects the memory, places
output drivers in a high-impedance state and turns off
all internal circuits. RP » must be held low for a minimum
of 100 ns. Time tPHQV is required after return from powerdown until initial memory access outputs are valid. After this wake-up interval, normal operation is restored.
The CUI is reset to read array mode and status register
is set to 80H.
During block erase, byte write, or lock-bit configuration modes, RP »-low will abort the operation. RY »/BY »
remains low until the reset operation is complete.
Memory contents being altered are no longer valid; the
data may be partially erased or written. Time tPHWL is
required after RP » goes to logic-high (VIH) before another command can be written.
As with any automated device, it is important to
assert RP » during system reset. When the system comes
out of reset, it expects to read from the flash memory.
Automated flash memories provide status information
when accessed during block erase, byte write, or lockbit configuration modes. If a CPU reset occurs with no
flash memory reset, proper CPU initialization may not
occur because the flash memory may be providing status information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP » input. In this
application, RP » is controlled by the same RESET signal that resets the system CPU.
Read Identifier Codes Operation
The read identifier codes operation outputs the manufacturer code, device code, block lock configuration
codes for each block, and the master lock configuration
code (see Figure 5). Using the manufacturer and device codes, the system CPU can automatically match
the device with its proper algorithms. The block lock and
master lock configuration codes identify locked and
unlocked blocks and master lock-bit setting.
8M (1M × 8) Flash Memory
LH28F008SC
Write
FFFFF
F0004
RESERVED FOR
FUTURE IMPLEMENTATION
F0003
F0002
BLOCK 15 LOCK CONFIGURATION CODE
F0001
RESERVED FOR
FUTURE IMPLEMENTATION
...
...
BLOCK 15
F0000
(BLOCKS 2 THROUGH 14)
1FFFF
10004
RESERVED FOR
FUTURE IMPLEMENTATION
10003
10002
BLOCK 1 LOCK CONFIGURATION CODE
10001
RESERVED FOR
FUTURE IMPLEMENTATION
10000
0FFFF
BLOCK 1
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
VPP = VPPH1/2/3, the CUI additionally controls block erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate command data and an address within the block to be erased.
The Byte Write command requires the command and
address of the location to be written. Set Master and
Block Lock-Bit commands require the command and
address within the device (Master Lock) or block within
the device (Block Lock) to be locked. The Clear Block
Lock-Bits command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE » and CE » are active. The
address and data needed to execute a command are
latched on the rising edge of WE » or CE » (whichever
goes high first). Standard microprocessor write timings
are used. Figures 16 and 17 illustrate WE » and CE » controlled write operations.
COMMAND DEFINITIONS
RESERVED FOR
FUTURE IMPLEMENTATION
00004
00003
MASTER LOCK CONFIGURATION CODE
00002
BLOCK 0 LOCK CONFIGURATION CODE
00001
DEVICE CODE
00000
MANUFACTURER CODE
BLOCK 0
28F008SC-5
Figure 5. Device Identifier Code Memory Map
When the VPP voltage ≤ VPPLK, Read operations
from the status register, identifier codes, or blocks are
enabled. Placing VPPH1/2/3 on VPP enables successful
block erase, byte write and lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. The Command Definitions Table
defines these commands.
Read Array Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the Read
Array command. The device remains enabled for reads
until another command is written. Once the internal
WSM has started a block erase, byte write or lock-bit
configuration, the device will not recognize the Read
Array command until the WSM completes its operation
unless the WSM is suspended via an Erase Suspend
or Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and
RP » can be VIH or VHH.
7
LH28F008SC
8M (1M × 8) Flash Memory
BUS OPERATIONS
RP »
CE »
OE »
WE
ADDRESS
VPP
DQ0 - DQ7
RY »/BY »
NOTE
Read
VIH or VHH
VIL
VIL
VIH
X
X
DOUT
X
1, 2, 3
Output Disable
VIH or VHH
VIL
VIH
VIH
X
X
High-Z
X
3
Standby
VIH or VHH
VIH
X
X
X
X
High-Z
X
3
VIL
X
X
X
X
X
High-Z
VOH
4
Read Identifier Codes VIH or VHH
VIL
VIL
VIH
See Figure 5
X
Note 5
VOH
Write
VIL
VIH
VIL
X
X
DIN
X
MODE
Deep Power Down
VIH or VHH
3, 6, 7
NOTES:
1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for
VPPLK and VPPH1/2/3 voltages.
3. RY »/BY » is VOL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VOH during when
the WSM is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode.
4. RP » at GND ± 0.2 V ensures the lowest deep power-down current.
5. See Read Identifier Codes Command Section for read identifier code data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH1/2/3 and VCC = VCC1/2/3.
Block erase, byte write, or lock-bit configuration with V IH < RP » < VHH produce spurious results and should not be attempted.
7. Refer to Command Definitions Table for valid DIN during a write operation.
8
8M (1M × 8) Flash Memory
LH28F008SC
Command Definitions9
BUS
CYCLES
REQ'D
OPER.1
ADDRESS2
DATA3
1
Write
X
FFH
Read Identifier Codes
≥2
Write
X
Read Status Register
2
Write
Clear Status Register
1
Block Erase
COMMAND
FIRST BUS CYCLE
SECOND BUS CYCLE
NOTE
OPER.1
ADDRESS2
DATA3
90H
Read
IA
ID
X
70H
Read
X
SRD
Write
X
50H
2
Write
BA
20H
Write
BA
D0H
5
Byte Write
2
Write
WA
40H or 10H
Write
WD
5, 6
Block Erase and Byte
Write Suspend
1
Write
X
B0H
Block Erase and Byte
Write Resume
1
Write
X
D0H
Set Block Lock-Bit
2
Write
BA
60H
Write
BA
01H
7
Set Master Lock-Bit
2
Write
X
60H
Write
X
F1H
7
Clear Block Lock Bits
2
Write
X
60H
Write
X
D0H
8
Read Array/Reset
WA
4
5
5
NOTES:
1. Bus operations are defined in Bus Definition Table.
2. X = Any valid address within the device.
IA = Idendifier Code Address: see Figure 5.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3. SRD = Data read from status register. See Status Register for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE » or CE » (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes.
See Read Identifier Code Command Section for read identifier code data.
5. If the block is locked, RP » must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte
write to locked block while RP » is VIH.
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. If the master lock-bit is set, RP » must be at VHH to set a block lock-bit. RP » must be at VHH to set the master lock-bit. If the master
lock-bit is not set, a block lock-bit can be set while RP » is VIH.
8. If the master lock-bit is set, RP » must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all
block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP » is VIH.
9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
9
LH28F008SC
8M (1M × 8) Flash Memory
Read Identifier Codes Command
Clear Status Register Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 5 retrieve the manufacturer, device, block lock
configuration and master lock configuration codes (see
Identifier Code Table for code values). To terminate the
operation, write another valid command. Like the Read
Array command, the Read Identifier Codes command
functions independently of the VPP and RP » can be VIH
or VHH. Following the Read Identifier Codes command,
the following information can be read:
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to '1' by the WSM and can only be reset by the Clear
Status Register command. These bits indicate various
failure conditions (see Status Register). By allowing system software to reset these bits, several operations
(such as cumulatively erasing or locking multiple blocks
or writing several bytes in sequence) may be performed.
The status register may be polled to determine if an
error occurred during the sequence.
Identifier Codes
CODE
ADDRESS
DATA
Manufacturer Code
00000
89
Device Code
00001
A6
Block Lock Configurations
X00021
• Block is Unlocked
DQ0 = 0
• Block is Locked
DQ0 = 1
DQ1 - DQ7
• Reserved for Future Use
Master Lock Configuration
00003
• Device is Unlocked
DQ0 = 0
• Device is Locked
DQ0 = 1
• Reserved for Future Use
DQ1 - DQ7
NOTE:
1. X selects the specific block lock configuration code to be read.
See Figure 5 for the device identifier code memory map.
Read Status Register Command
The status register may be read to determine when
a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the
status register until another valid command is written.
The status register contents are latched on the falling
edge of OE » or CE », whichever occurs. OE » or CE » must
toggle to VIH before further reads to update the status
register latch. The Read Status Register command functions independently of the VPP voltage. RP » can be VIH
or VHH.
10
To clear the status register, the Clear Status Register command (50H) is written. It functions independently
of the applied VPP Voltage. RP » can be VIH or VHH. This
command is not functional during block erase or byte
write suspend modes.
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This command sequence requires appropriate sequencing and
an address within the block to be erased (erase changes
all block data to FFH). Block preconditioning, erase, and
verify are handled internally by the WSM (invisible to
the system). After the two-cycle block erase sequence
is written, the device automatically outputs status register data when read (see Figure 6). The CPU can
detect block erase completion by analyzing the output
data of the RY »/BY » or status register bit SR.7.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not accidentally erased. An invalid Block Erase command
sequence will result in both status register bits
SR.4 and SR.5 being set to '1'. Also, reliable block erasure can only occur when V CC = V CC1/2/3 and
VPP = VPPH1/2/3. In the absence of this high voltage,
block contents are protected against erasure. If block
erase is attempted while VPP ≤ VPPLK, SR.3 and SR.5
will be set to '1'. Successful block erase requires that
the corresponding block lock-bit be cleared or, if set,
that RP » = VHH. If block erase is attempted when the
corresponding block lock-bit is set and RP » = VIH, SR.1
and SR.5 will be set to '1'. Block erase operations with
VIH < RP » < VHH produce spurious results and should
not be attempted.
8M (1M × 8) Flash Memory
Byte Write Command
Byte write is executed by a two-cycle command
sequence. Byte write setup (standard 40H or alternate
10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of
WE )» . The WSM then takes over, controlling the byte write
and write verify algorithms internally. After the byte write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The CPU
can detect the completion of the byte write event by
analyzing the RY »/BY » pin or status register bit SR.7.
When byte write is complete, status register bit SR.4
should be checked. If byte write error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for '1's that do not successfully write to '0's. The CUI remains in read status register mode until it receives another command.
Reliable byte writes can only occur when
VCC = VCC1/2/3 and VPP = VPPH1/2/3. In the absence of
this high voltage, memory contents are protected against
byte writes. If byte write is attempted while VPP ≤ VPPLK,
status register bits SR.4 and SR.5 will be set to '1'. Successful byte write requires that the corresponding block
lock-bit be cleared or, if set, that RP » = VHH. If byte write
is attempted when the corresponding block lock-bit is
set and RP » = VIH, SR.1 and SR.4 will be set to '1'. Byte
write operations with VIH < RP » < VHH produce spurious
results and should not be attempted.
Block Erase Suspend Command
The Block Erase Suspend command allows blockerase interruption to read or byte-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to '1').
RY »/BY » will also transition to VOH. Specification tWHRH2
defines the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is suspended. A Byte Write command sequence can also be
issued during erase suspend to program data in other
blocks. Using the Byte Write Suspend command (see
LH28F008SC
Byte Write Suspend Command Section), a byte write
operation can also be suspended. During a byte write
operation with block erase suspended, status register
bit SR.7 will return to '0' and the RY »/BY » output will transition to VOL. However, SR.6 will remain '1' to indicate
block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY »/BY » will return to VOL. After
the Erase Resume command is written, the device automatically outputs status register data when read (see
Figure 8). VPP must remain at VPPH1/2/3 (the same VPP
level used for block erase) while block erase is suspended. RP » must also remain at VIH or VHH (the same
RP » level used for block erase). Block erase cannot resume until byte write operations initiated during block
erase suspend have completed.
Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory locations. Once the byte write process starts, writing the
Byte Write Suspend command resquests that the WSM
suspend the byte write sequence at a predetermined
point in the algorithm. The device continues to output
status register data when read after the Byte Write Suspend command is written. Polling status register bits
SR.7 and SR.2 can determine when the byte write
operation has been suspended (both will be set to '1').
RY »/BY » will also transition to VOH. Specification tWHRH1
defines the byte write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is suspended. The only other valid commands while byte write
is suspended are Read Status Register and Byte Write
Resume. After Byte Write Resume command is written
to the flash memory, the WSM will continue the byte
write process. Status register bits SR.2 and SR.7 will
automatically clear and RY »/BY » will return to VOL. After
the Byte Write Resume command is written, the device
automatically outputs status register data when read
(see Figure 9). VPP must remain at VPPH1/2/3 (the same
VPP level used for byte write) while in byte write suspend mode. RP » must also remain at VIH or VHH (the
same RP » level used for byte write).
11
LH28F008SC
Set Block and Master
Lock-Bit Commands
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase
operations while the master lock-bit gates block-lock bit
modification. With the master lock-bit not set, individual
block lock-bits can be set using the Set Block Lock-Bit
command. The Set Master Lock-Bit command, in conjunction with RP » = VHH, sets the master lock-bit. After
the master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit command
and VHH on the RP » pin. See Write Protection Analysis
Table for a summary of hardware and software write
protection options.
Set block lock-bit and master lock-bit are executed
by a two-cycle command sequence. The set block or
master lock-bit setup along with appropriate block or
device address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set master lock-bit confirm (and any
device address). The WSM then controls the set lockbit algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 10). The CPU can detect the completion of
the set lock-bit event by analyzing the RY »/BY » pin output or status register bit SR.7.
When the set lock-bit operation is complete, status
register, bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until a new command is issued.
This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An
invalid Set Block or Master Lock-Bit command will
result in status register bits SR.4 and SR.5 being set
to '1'. Also, reliable operations occur only when
VCC = VCC1/2/3 and VPP = VPPH1/2/3. In the absence of
this high voltage, lock-bit contents are protected against
alteration.
A successful set block lock-bit operation requires that
the master lock-bit be cleared or, if the master lock-bit
is set, that RP » = VHH. If it is attempted with the master
lock-bit set and RP » = VIH, SR.1 and SR.4 will be set to
'1' and the operation will fail. Set block lock-bit operations while VIH < RP » < VHH produce spurious results
and should not be attempted. A successful set master
lock-bit operation requires that RP » = VHH. If it is attempted with RP » = VIH, SR.1 and SR.4 will be set to '1'
and the operation will fail. Set master lock-bit operations with VIH < RP » < VHH produce spurious results and
should not be attempted.
12
8M (1M × 8) Flash Memory
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master lockbit not set, block lock-bits can be cleared using only the
Clear Block Lock-Bits command. If the master lock-bit
is set, clearing block lock-bits requires both the Clear
Block Lock-Bits command and VHH on the RP » pin. See
Write Protection Analysis Table for a summary of hardware and software white protection options.
Clear block lock-bits operation is executed by a twocycle command sequence. A clear block lock-bits setup
is first written. After the command is written, the device
automatically outputs status register data when read
(see Figure 11). The CPU can detect completion of the
clear block lock-bits event by analyzing the RY »/BY » Pin
output or status register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until another
command is issued.
This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally
cleared. An invalid Clear Block Lock-Bits command
sequence will result in status register bits SR.4 and SR.5
being set to “1”. Also, a reliable clear block lock bits
operation can only occur when VCC = VCC1/2/3 and
VPP = VPPH1/2/3. If a clear block lock-bits operation is
attempted while VPP ≤ VPPLK, SR.3 and SR.5 will be set
to '1'. In the absence of this high voltage, the block lockbits content are protected against alteration. A successful clear block lock-bits operation requires that the master
lock-bit is not set or, if the master lock-bit is set, that
RP » = VHH. If it is attempted with the master lock-bit set
and RP » = VIH, SR.1 and SR.5 will be set to '1' and the
operation will fail. A clear block lock-bits operation with
VIH < RP » < VHH produce spurious results and should
not be attempted.
If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP »
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
value. Once the master lock-bit is set, it cannont be
cleared.
8M (1M × 8) Flash Memory
LH28F008SC
Write Protection Alternatives
OPERATION
MASTER
LOCK-BIT
BLOCK
LOCK-BIT
0
Block Erase or
Byte Write
Set Block
Lock Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
RP#
VIH or VHH Block Erase and Byte Write Enabled.
X
1
0
X
1
X
X
X
1
X
VIH
Block is locked. Block Erase and Byte Write Disabled.
VHH
Block Lock-Bit Override. Block Erase and Byte Write Enabled.
VIH or VHH Set Block Lock-Bit Enabled.
X
0
EFFECT
VIH
Master Lock-Bit is Set. Set Block Lock-Bit Disabled.
VHH
Master Lock-Bit Override. Set Block Lock-Bit Enabled.
VIH
Set Master Lock-Bit Disabled.
VHH
Set Master Lock-Bit Enabled.
VIH or VHH Clear Block Lock-Bits Enable.
VIH
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled.
VHH
Master Lock-Bit Override. Clear Block Lock-Bits Enabled.
Status Register Definition
WSMS
ESS
ECLBS
BWSLBS
VPPS
BWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7
= WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
NOTES:
1. Check RY »/BY » or SR.7 to determine block erase, byte
write, or lock-bit configuration completion. SR.6 - SR.0 are
invalid while SR.7 = '0'.
SR.6
= ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
2. If both SR.5 and SR.4 are '1's after a block erase or lockbit configuration attempt, an improper command sequence
was entered.
SR.5
= ERASE AND CLEAR LOCK-BIT STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4
= BYTE WRITE AND SET LOCK-BIT STATUS
1 = Error in Byte Write or Set Master/Block Lock Bit
0 = Successful Byte Write or Set Master/Block
0 = Lock-Bit
SR.3
= VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2
= BYTE WRITE SUSPEND STATUS
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR.1
= DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or
1 = RP » Lock Detected, Operation Abort
0 = Unlock
SR.0
= RESERVED FOR FUTURE ENHANCEMENTS
3. SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only
after Block Erase, Byte Write, Set Block/Master Lock-Bit,
or Clear Block Lock-Bits command sequences. SR.3 is not
guaranteed to report accurate feedback only when
VPP = VPPH1/2/3.
4. SR.1 does not provide a continuous indication of master
and block lock-bit values. The WSM interrogates the master
lock-bit, block lock-bit, and RP » only after Block Erase, Byte
Write, or Lock-Bit configuration command sequences. It
informs the system, depending on the attempted operation,
if the block lock-bit is set, master lock-bit is set, and/or RP »
is not VHH. Reading the block lock and master lock configuration codes after writing the Read identifier Codes command indicates master and block lock-bit status.
5. SR.0 is reserved for future use and should be masked out
when polling the status register.
13
LH28F008SC
8M (1M × 8) Flash Memory
START
BUS
OPERATION
WRITE 20H
BLOCK ADDRESS
Write
Erase
Setup
Data = 20H
Addr = Within block to be
erased
WRITE D0H
BLOCK ADDRESS
Write
Erase
Confirm
Data = D0H
Addr = Within block to be
erased
READ STATUS
REGISTER
Read
NO
SR.7 =
0
SUSPEND BLOCK
ERASE LOOP
SUSPEND YES
BLOCK
ERASE?
1
COMMAND
COMMENTS
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or
after a sequence of block erasures.
FULL STATUS
CHECK IF DESIRED
Write FFH after the last operation to place
device in read array mode.
BLOCK ERASE
COMPLETED
FULL STATUS CHECK PROCEDURE
STATUS REGISTER
DATA
(see above)
SR.3 =
BUS
OPERATION
COMMAND
Standby
Check SR.3
1 = VPP Low Detect
1
VPP RANGE
ERROR
Standby
Check SR.1
1 = Device Protect Detect
RP = VIH Block Lock-Bit is Set
Only required for systems
implemening lock-bit
configuration
1
DEVICE
PROTECT
ERROR
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
1
COMMAND
SEQUENCE
ERROR
Check SR.5
1 = Block Erase Error
0
SR.1 =
0
SR.4, 5 =
0
SR.5 =
COMMENTS
1
BLOCK ERASE
ERROR
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
BLOCK ERASE
SUCCESSFUL
28F008SC-6
Figure 6. Automated Block Erase Flowchart
14
8M (1M × 8) Flash Memory
LH28F008SC
START
BUS
OPERATION
WRITE 40H
ADDRESS
Write
Setup
Byte Write
Data = 40H
Addr = Location to be written
Write
Byte
Write
Data = Data to be written
Addr = Location to be written
WRITE BYTE DATA
AND ADDRESS
COMMAND
Read
READ STATUS
REGISTER
SR.7 =
0
Status Register Data
Standy
NO
Check SR.7
1 = WSM Ready
0 = WSM Busy
ERASE SUSPEND
WRITE LOOP
SUSPEND
BYTE
WRITE?
YES
COMMENTS
Repeat for subsequent byte writes.
SR full status check can be done after each byte write or
after a sequence of byte writes.
1
FULL STATUS
CHECK IF DESIRED
Write FFH after the last byte write operation to place
device in read array mode.
BYTE WRITE
COMPLETED
FULL STATUS CHECK PROCEDURE
READ STATUS
REGISTER DATA
(see above)
SR.3 =
BUS
OPERATION
COMMAND
Standby
Check SR.3
1 = VPP Low Detect
1
VPP RANGE
ERROR
Standby
Check SR.1
1 = Device Protect Detect
RP = VIH Block Lock-Bit is Set
Only required for systems
implemening lock-bit
configuration
1
DEVICE
PROTECT
ERROR
Standby
Check SR.4
1 = Data Write Error
0
SR.1 =
0
SR.4 =
COMMENTS
1
0
BYTE WRITE
ERROR
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple locations are written
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
BYTE WRITE
SUCCESSFUL
28F008SC-7
Figure 7. Automated Byte Write Flowchart
15
LH28F008SC
8M (1M × 8) Flash Memory
START
BUS
OPERATION
COMMAND
Write
Erase
Suspend
WRITE B0H
Read
READ
STATUS REGISTER
SR.7 =
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Erase Suspended
0 = Erase Completed
Write
SR.6 =
0
Data = B0H
Addr = X
Status Register Data
Addr = X
0
1
COMMENTS
Erase
Resume
D = D0H
Addr = X
BLOCK
ERASE COMPLETED
1
READ or
BYTE
WRITE ?
Read
Read
Array Data
NO
Byte Write
Byte
Write Loop
DONE ?
YES
WRITE D0H
WRITE FFH
BLOCK
ERASE RESUMED
READ ARRAY DATA
28F008SC-8
Figure 7. Block Erase Suspend/Resume Flowchart
16
8M (1M × 8) Flash Memory
LH28F008SC
START
WRITE B0H
BUS
OPERATION
COMMAND
Write
Byte Write
Suspend
Read
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Byte Write Suspended
0 = Byte Write Completed
0
1
Write
SR.2 =
Data = B0H
Addr = X
Status Register Data
Addr = X
READ
STATUS REGISTER
SR.7 =
COMMENTS
0
BYTE WRITE
COMPLETED
Read
Array
Read
Data = FFH
Addr = X
Read Array locations other
than that being written.
1
Write
WRITE FFH
Byte Write
Resume
Data = D0H
Addr = X
READ ARRAY DATA
DONE
READING
NO
YES
WRITE D0H
WRITE FFH
BYTE
WRITE RESUMED
READ ARRAY DATA
28F008SC-9
Figure 9. Byte Write Suspend/Resume Flowchart
17
LH28F008SC
8M (1M × 8) Flash Memory
START
BUS
OPERATION
WRITE 60H
BLOCK/DEVICE ADDRESS
COMMAND
COMMENTS
Write
Set
Block/Master
Lock-Bit Setup
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Write
Set
Block or Master
Lock-Bit Confirm
Data = 01H (Block)
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
WRITE 01H/F1H
BLOCK/DEVICE ADDRESS
Read
READ STATUS REGISTER
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
0
SR.7 =
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
1
FULL STATUS
CHECK IF DESIRED
Write FFH after the last lock-bit set operation to place device
in read array mode.
SET LOCK-BIT
COMPLETED
FULL STATUS CHECK PROCEDURE
READ STATUS
REGISTER DATA
(see above)
SR.3 =
BUS
OPERATION
1
VPP RANGE
ERROR
1
DEVICE
PROTECT
ERROR
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP = VIH
(Set Master Lock-Bit Operation)
RP = VIH, Master Lock-Bit is Set
(Set Block Lock-Bit Operation)
Standby
Check SR.4, 5
Both 1 = Command
Sequence Error
Standby
Check SR.4
1 = Set Lock-Bit Error
0
SR.4, 5 =
1
COMMAND
SEQUENCE
ERROR
0
SR.4 =
1
SET LOCK-BIT
ERROR
COMMENTS
Standby
0
SR.1 =
COMMAND
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set
before full status is checked.
If error is detected clear the Status Register before attempting
retry or other error recovery.
0
SET LOCK-BIT
SUCCESSFUL
28F008SC-10
Figure 10. Set Block and Master Lock-Bit Flowchart
18
8M (1M × 8) Flash Memory
LH28F008SC
START
BUS
OPERATION
WRITE 60H
COMMAND
COMMENTS
Write
Clear Block
Lock-Bits Setup
Data = 60H
Addr = X
Write
Clear Block
Lock-Bits
Confirm
Data = D0H
Addr = X
WRITE D0H
Status Register Data
Read
READ STATUS REGISTER
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
SR.7 =
Write FFH after the Clear Block Lock-Bits operation to
place device in read array mode.
1
FULL STATUS
CHECK IF DESIRED
CLEAR BLOCK
LOCK-BITS COMPLETE
FULL STATUS CHECK PROCEDURE
READ STATUS
REGISTER DATA
(see above)
SR.3 =
1
BUS
OPERATION
VPP RANGE
ERROR
SR.1 =
1
YES
SR.4, 5 =
1
COMMAND
SEQUENCE
ERROR
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
RP = VIH, Master Lock-Bit is Set
Standby
Check SR.4, 5
Both 1 = Command
Sequence Error
Standby
Check SR.5
1 = Clear Block Lock-Bit Error
0
DEVICE
PROTECT
ERROR
COMMAND
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attemping
retry or other error recovery.
SR.5 =
1
CLEAR BLOCK
LOCK-BITS ERROR
YES
CLEAR BLOCK
LOCK-BITS
SUCCESSFUL
28F008SC-11
Figure 11. Clear Block Lock-Bits Flowchart
19
LH28F008SC
8M (1M × 8) Flash Memory
DESIGN CONSIDERATIONS
VPP Trace on Printed Circuit Boards
Three-Line Output Control
Updating flash memories that reside in the target
system requires that the printed circuit board designer
pay attention to the VPP Power supply trace. The VPP
pin supplies the memory cell current for byte writing and
block erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP
supply traces and decoupling will decrease VPP voltage
spikes and overshoots.
The device will often be used in large memory
arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line
control provides for:
• Lowest possible memory power dissipation
• Complete assurance that data bus contention will
not occur.
To use these control input efficiently, an address
decoder should enable CE » while OE » should be connected
to all memory devices and the system’s READ control line.
This assures that only selected memory devices have active outputs while deselected memory devices are in
standby mode. RP » should be connected to the system
POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also
toggle during system reset.
RY /» BY » and Block Erase, Byte Write, and
Lock-Bit Configuration Polling
RY »/BY » is a full CMOS output that provides a hardware method of detecting block erase, byte write and
block-bit configuration completion. It transitions low after lock erase, byte write, or lock-bit configuration commands and returns to VOH when the WSM has finished
executing the internal algorithm.
RY »/BY » can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
RY »/BY » is also VOH when the device is in block erase
suspend (with byte write inactive), byte write suspend
or deep power-down modes.
VCC, VPP, RP » Transitions
Block erase, byte write and lock-bit configuration are
not guaranteed if VPP falls outside of a valid VPPH1/2/3
range, VCC falls outside of a valid VCC1/2/3 range, or
RP » ≠ VIH or VHH. If VPP error is detected, status register
bit SR.3 is set to '1' along with SR.4 or SR.5,
depending on the attempted operation. If RP » transitions
to VIL during block erase, byte write, or lock-bit configuration, RY »/BY » will remain low until the reset operation
is complete. Then, the opration will abort and the
device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal
operation is restored. Device power-off or RP » transiitions
to VIL clear the status register.
The CUI latches commands issued by system software and is not altered by VPP or CE » transitions or WSM
actions. Its state is read array mode upon power-up,
after exit from deep power-down or after VCC transitions
below VLKO.
After block erase, byte write, or lock-bit configuration, even after VPP transitions down to VPPLK, the CUI
must be placed in read array mode via the Read Array
command if subsequent access to the memory array is
desired.
Power Supply Decoupling
Flash memory power switching characteristics
require careful device decoupling. System designers are
interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE » and OE » .
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its VCC
and GND and between its VPP and GND. These highfrequency, low inductance capacitors should be placed
as close as possible to package leads. Additionally, for
every eight devices, a 4.7 µF electrolytic capacitor
should be placed at the array’s power supply connection betweenV CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductance.
20
Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon power-up, the
device is indifferent as to which power supply (VPP or
VCC) powers-up first. Internal circuitry resets the CUI to
read array mode at power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is active.
Since both WE » and CE » must be low for a command
write, driving either to VIH will inhibit writes. The CUI’s
two-step command sequence archiecture provides
added level of protection against data alteration.
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled while
RP » = VIL regardless of its control inputs state.
8M (1M × 8) Flash Memory
LH28F008SC
Power Dissipation
NOTICE: This datasheet contains information on
products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is available.
Veryify with your local SHARP sales office that you have
the latest datasheet before finalizing a design.
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases
usable battery life because data is retained when system power is removed.
*WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the
“Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may
affect device reliability.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing products and other power sensitive applications that use an
array of devices for solid-state storage can consume
negligible power by lowering RP » to VIL standby or sleep
modes. If access is again needed, the devices can be
read following the tPHQV and tPHWL wake-up cycles required after RP » is first raised to VIH. See AC Characteristics - Read Only and Write Operations and Figures 16
and 17 for more information.
NOTES:
1. Operating temperature is for commercial product defined by
this specification.
2. All specified voltages are with respect to GND. Minimum DC
voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP
pins. During transitions, this level may undershoot to -2.0 V for
periods < 20 ns. Maximum DC voltage on input/output pins and
VCC is VCC + 5.0 V which, during transitions, may overshoot to
VCC + 2.0 V for periods < 20 ns.
3. Maximum DC voltage on VPP and RP » may overshoot to
+14.0 V for periods < 20 ns.
4. Output shorted for no more than on second. No more than one
output shorted at a time.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Commercial Operating Temperature
during Read, Block Erase, Byte Write,
and Lock-Bit Configuration ............... 0°C to +70°C1
Temperature under Bias ...................... -10°C to +80°C
Storage Temperature: ......................... 65°C to +125°C
Voltage On Any Pin
(except VCC, VPP and RP ») ................ -2 V to +7.0 V2
VCC Supply Voltage ........................... -2.0 V to +7.0 V2
VPP Update Voltage during Block Erase,
Byte Write,and Lock-Bit
Configuration ............................ -2.0 V to +14.0 V2, 3
RP » Voltage with Respect to GND
during Lock-Bit Configuration
Operations ...............................-2.0 V to +14.0 V2, 3
Output Short Circuit Current .......................... 100 mA4
Operating Conditions
Temperature and VCC Operating Conditions
SYMBOL
TA
PARAMETER
Operating Temperature
MIN.
MAX.
UNIT
TEST CONDITION
0
+70
°C
Ambient Temperature
VCC1
VCC Supply Voltage (3.3 V ± 0.3 V)
3.0
3.6
V
VCC2
VCC Supply Voltage (5 V ± 5%)
4.75
5.25
V
VCC3
VCC Supply Voltage (5 V ± 10%)
4.50
5.50
V
21
LH28F008SC
8M (1M × 8) Flash Memory
Capacitance
TA = +25°C, f = 1 MHz
SYMBOL
CIN
COUT
PARAMETER
TYP.
MAX.
UNITS
CONDITIONS
Input Capacitance
6
8
pF
VIN = 0.0 V
Output Capacitance
8
12
pF
VOUT = 0.0 V
NOTE:
1. Sampled, not 100% tested.
AC INPUT/OUTPUT TEST CONDITIONS
1.3 V
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
1N914
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
28F008SC-12
Figure 12. Transient Input/Output Reference
Waveform for VCC = 3.3 V ±0.3 V and VCC = 5 V ±5%
(High Speed Testing Configuration)
RL = 3.3 kΩ
DEVICE
UNDER
TEST
OUT
CL
NOTE: CL Includes Jig Capacitance
2.4
INPUT
0.45
2.0
0.8
TEST POINTS
2.0
0.8
OUTPUT
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
28F008SC-14
Figure 14. Transient Equivalent
Testing Load Circuit
Test Configuration Capacitance
Loading Value
28F008SC-13
Figure 13. Transient Input/Output Reference
Waveform for VCC = 5 V ±10%
(Standard Testing Configuration)
22
TEST CONFIGURATION
CL (pF)
VCC = 3.3 V ± 0.3 V
50
VCC = 5 V ± 0.5%
30
VCC = 5 V ± 10%
100
8M (1M × 8) Flash Memory
LH28F008SC
DC CHARACTERISTICS
SYM.
PARAMETER
VCC = 3.3 V
TYP.
MAX.
VCC = 5 V
TYP.
UNIT
TEST CONDITIONS
NOTE
MAX.
ILI
Input Load Current
±0.5
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±0.5
±10
µA
VCC = VCC MAX., VOUT = VCC or GND
1
100
100
µA
CMOS Inputs, VCC = VCC MAX.
CE » = RP » = VCC ±0.2 V
ICCS
ICCD
ICCR
VCC Standby Current
VCC Deep Power-Down
Current
2
2
mA
TTL Inputs, VCC = VCC MAX.
CE » = RP » = VIH
10
10
µA
RP » = GND ±0.2 V IOUT
(RY »/BY ») = 0 mA
12
35
mA
CMOS Inputs VCC = VCC MAX.,
CE » = GND, f = 5 MHz (3.3 V),
f = 8 MHz (5 V), IOUT = 0 mA
mA
TTL Inputs, VCC = VCC MAX.,
CE » = VIH, f = 5 MHz (3.3 V),
f = 8 MHz, (5 V) IOUT = 0 mA
mA
VPP = 3.3 V ±0.3 V
VCC Read Current
14
50
17
ICCW
ICCE
VCC Byte Write or Set
Lock-Bit Current
VCC Block Erase or
Clear Block Lock-Bits
Current
VCC Byte Write or
ICCWS
Block Erase Suspend
ICCES
Current
IPPS
IPPR
VPP Standby or Read
Current
IPPD
VPP Deep Power-Down
Current
IPPW
VPP Byte Write or Set
Lock-Bit Current
17
35
mA
VPP = 5.0 V ±10%
12
30
mA
VPP = 12.0 V ± 5%
mA
VPP = 3.3 V ±0.3 V
17
17
30
mA
VPP = 5.0 V ±10%
12
25
mA
VPP = 12.0 V ±5%
6
10
mA
CE » = VIH
±15
±15
µA
VPP ≤ VCC
200
200
µA
VPP > VCC
5
5
µA
RP » = GND ± 0.2V
mA
VPP = 3.3 V ± 0.3 V
40
40
40
mA
VPP = 5.0 V ±10%
15
15
mA
VPP = 12.0 V ±5%
mA
VPP = 3.3 V ± 0.3 V
20
IPPE
VPP Block Erase or
Clear Lock-Bit Current
VPP Byte Write or
IPPWS
Block Erase Suspend
IPPES
Current
20
20
mA
VPP = 5.0 V ± 105
15
15
mA
VPP = 12.0 V ±5%
200
200
µA
VPP = VPPH1/2/3
1, 3, 6
1
1, 5, 6
1, 7
1, 7
1, 2
1
1
1, 7
1, 7
1
23
LH28F008SC
8M (1M × 8) Flash Memory
DC CHARACTERISTICS (Continued)
SYM.
PARAMETER
VCC = 3.3 V
VCC = 5 V
MIN.
MAX.
MIN.
MAX.
UNIT
TEST CONDITIONS
NOTE
VIL
Input Low Voltage
-0.5
0.8
-0.5
0.8
V
7
VIH
Input High Voltage
2.0
VCC + 0.5
2.0
VCC + 0.5
V
7
VOL
Output Low Voltage
0.45
V
VCC = VCC MIN.,
IOL = 5.8 mA
3, 7
VOH1
Output High Voltage
(TTL)
VOH2
Output High Voltage
(CMOS)
VPPLK
0.4
2.4
2.4
V
VCC = VCC MIN.,
IOH = 2.5 mA
3, 7
0.85 VCC
0.85 VCC
V
VCC = VCC MIN.,
IOH = 2.5 µA
4, 7
VCC - 0.4
VCC - 0.4
V
VCC = VCC MIN.,
IOH = 100 µA
VPP Lockout during
Normal Operations
1.5
1.5
V
VPP during Byte Write,
VPPH1 Block Erase, or LockBit Operations
3.0
3.6
VPP during Byte Write,
VPPH2 Block Erase, or LockBit Operations
4.5
5.5
4.5
5.5
V
VPP during Byte Write,
VPPH3 Block Erase, or LockBit Operations
11.4
12.6
11.4
12.6
V
VLKO
VCC Lockout Voltage
2.0
VHH
RP » Unlock Voltage
11.4
V
2.0
12.6
11.4
V
12.6
V
Set Master Lock-Bit
Override Master and
Block Lock-Bit
8
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact
SHARP’s Application Support Hotline or your local sales office for information about typical specifications.
2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode, the device’s current
draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Includes RY »/BY ».
4. Block erases, byte writes, and lock-bit configurations are inhibited when V PP ≤ VPPLK, and not guaranteed in the range between VPPLK
(MAX.) and VPPH1(MIN.), between V PPH1(MAX.) and VPPH2 (MIN.), between VPPH2 (MAX.) and VPPH3 (MIN.), and above VPPH3 (MAX.).
5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5 V VCC and 3 mA at 3.3 V VCC in static operation.
6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.
7. Sampled, but not 100% tested.
8. Master lock-bit set operations are inhibited when RP » = VIH. Block lock-bit configuration operations are inhibited when the master lock
bit is set and RP » = VIH. Block erases and byte writes are inhibited when the corresponding block-lock bit is set and RP » = VIH.
Block erase, byte write, and lock-bit configuration operations are not guaranteed with V IH < RP » < VHH.
24
8M (1M × 8) Flash Memory
LH28F008SC
AC CHARACTERISTICS - Read Only Operations1
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
SYMBOL
LH28F008SC-120
LH28F008SC-150
MIN.
MIN.
PARAMETER
UNIT
MAX.
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
120
150
ns
tELQV
CE » to Output Delay
120
150
ns
tPHQV
RP » High to Output Delay
600
600
ns
tGLQV
OE » to Output Delay
50
55
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » High to Output in High Z
ns
3
tGLQX
CE » to Output in Low Z
ns
3
tGHQZ
OE » High to Output in High Z
ns
3
ns
3
tOH
120
NOTE
MAX.
150
0
0
55
55
0
0
20
Output Hold from Addresses, CE »
or OE » change, whichever is first
ns
25
0
0
2
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
LH28F00SC-855
VCC ± 5%
MIN.
MAX.
MIN.
MAX.
MIN.
UNIT
NOTE
MAX.
Read Cycle Time
tAVQV
Address to Output Delay
85
90
120
ns
tELQV
CE » to Output Delay
85
90
120
ns
tPHQV
RP » High to Output Delay
400
400
400
ns
tGLQV
OE » to Output Delay
40
45
50
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » High to Output in High Z
ns
3
tGLQX
CE » to Output in Low Z
ns
3
tGHQZ
OE » High to Output in High Z
ns
3
ns
3
Output Hold from Addresses, CE »
or OE » change, whichever is first
90
LH28F00SA-1206
VCC ± 10%
tAVAV
tOH
85
LH28F00SC-906
VCC ± 10%
0
0
55
0
0
55
0
10
0
ns
0
55
10
0
120
15
0
2
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE » may be delayed to to tELQV - tGLQV after the falling edge of CE » without inpact on tELQV.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing
characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing
characteristics.
25
LH28F008SC
8M (1M × 8) Flash Memory
DEVICE AND
ADDRESS
STANDBY SELECTION
ADDRESSES (A)
VIH
VIL
DATA
VALID
ADDRESSES STABLE
...
...
tAVAV
CE (E)
VIH
...
VIL
tAVEL
OE (G)
tEHQZ
VIH
VIL
...
tGHQZ
WE (W)
...
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q) VOH
(DQ0 - DQ7) V
OL
...
...
HIGH-Z
VALID OUTPUT
HIGH-Z
tAVQV
...
VCC
tPHQV
RP (P)
VIH
VIL
...
28F008SC-15
Figure 15. AC Waveforms for Read Operations
26
8M (1M × 8) Flash Memory
LH28F008SC
AC CHARACTERISTICS - Write Operations1
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
LH28F008SC-120
SYMBOL
LH28F008SC-150
PARAMETER
UNIT
MIN.
tAVAV
Write Cycle Time
tPHWL
MAX.
MIN.
NOTE
MAX.
120
150
ns
RP » High Recovery to WE Going Low
1
1
µs
tELWL
CE » Setup to WE Going Low
10
10
ns
tWLWH
WE Pulse Width
50
50
ns
tPHHWH
RP » VHH Setup to WE Going High
100
100
ns
2
tVPWH
VPP Setup to WE Going High
100
100
ns
2
tAVWH
Address Setup to WE Going High
50
50
ns
3
tDVWH
Data Setup to WE Going High
50
50
ns
3
tWHDX
Data Hold from WE High
5
5
ns
tWHAX
Address Hold from WE High
5
5
ns
tWHEH
CE » Hold from WE High
10
10
ns
tWHWL
WE Pulse Width High
30
30
ns
tWHRL
WE High to RY »/BY » Going Low
tWHGL
Write Recovery before Read
0
0
ns
tQVVL
VPP Hold from Valid SRD, RY »/BY » High
0
0
ns
2, 4
tQVPH
RP » VHH Hold from Valid SRD, RY »/BY » High
0
0
ns
2, 4
100
100
2
ns
NOTE:
1. See 5 V VCC AC Characteristics - Write Operations for Notes 1 through 5.
27
LH28F008SC
8M (1M × 8) Flash Memory
AC CHARACTERISTICS - Write Operations1
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
LH28F008SC-856
SYMBOL
LH28F008SC-907
LH28F008SC-1208
PARAMETER
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
NOTE
MAX.
tAVAV
Write Cycle Time
85
90
120
ns
tPHWL
RP » High Recovery to WE
Going Low
1
1
1
µs
tELWL
CE » Setup to WE Going Low
10
10
10
ns
tWLWH
WE Pulse Width
40
40
40
ns
tPHHWH
RP » VHH Setup to WE
Going High
100
100
100
ns
2
tVPWH
VPP Setup to WE
Going High
100
100
100
ns
2
tAVWH
Address Setup to WE
Going High
40
40
40
ns
3
tDVWH
Data Setup to WE
Going High
40
40
40
ns
3
tWHDX
Data Hold from WE High
5
5
5
ns
tWHAX
Address Hold from
WE High
5
5
5
ns
tWHEH
CE » Hold from WE High
10
10
10
ns
tWHWL
WE Pulse Width High
30
30
30
ns
tWHRL
WE High to RY »/BY » Going
Low
tWHGL
Write Recovery before
Read
0
0
0
ns
tQVVL
VPP Hold from Valid SRD,
RY »/BY » High
0
0
0
ns
2, 4
tQVPH
RP » VHH Hold from Valid
SRD, RY »/BY » High
0
0
0
ns
2, 4
90
90
ns
NOTES:
1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are
the same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Command Definitions Table for valid A IN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP » should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration)
for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characters.
28
2
8M (1M × 8) Flash Memory
LH28F008SC
1
ADDRESSES (A)
2
VIH
3
AIN
VIL
tAVAV
4
5
6
VALID
SRD
DIN
AIN
tAVWH
tWHAX
CE (E)
OE (G)
WE (W)
VIH
VIL
tELWL
tWHGL
tWHEH
VIH
VIL
tWHWL
tWHQV1, 2, 3, 4
VIH
VIL
tWLWH
tDVWH
tWHOX
DATA (D/Q)
VIH
HIGH-Z
VIL
DIN
DIN
tWHPL
tPHWL
RY/BY (R)
VIH
VIL
tPHHWH
tQVPH
tVPWH
tQVVL
VHH
RP (P)
VIH
VIL
VPPH3, 2, 1
VPP (V)
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or byte write set-up.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
008SC-16
Figure 16. AC Waveforms for WE » Controlled Write Operations
29
LH28F008SC
8M (1M × 8) Flash Memory
ALTERNATIVE CE » - Controlled Writes1
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
LH28F008SC-120
SYMBOL
UNIT NOTE
MIN.
tAVAV
Write Cycle Time
tPHEL
MAX.
MIN.
MAX.
120
150
ns
RP » High Recovery to CE » Going Low
1
1
µs
tWLEL
WE Setup to CE »# Going Low
0
0
ns
tELEH
CE » Pulse Width
70
70
ns
RP » VHH Setup to CE » Going High
100
100
ns
2
tVPEH
VPP Setup to CE » Going High
100
100
ns
2
tAVEH
Address Setup to CE » Going High
50
50
ns
3
tDVEH
Data Setup to CE » Going High
50
50
ns
3
tEHDX
Data Hold from CE » High
5
5
ns
tEHAX
Address Hold from CE » High
5
5
ns
tEHWH
WE Hold from CE » High
0
0
ns
tEHEL
CE » Pulse Width High
25
25
ns
tEHRL
CE » High to RY »/BY » Going Low
tEHGL
Write Recovery before Read
0
0
µs
tQVVL
VPP Hold from Valid SRD, RY »/BY » High
0
0
ns
2, 4
tQVPH
RP » VHH Hold from Valid SRD, RY »/BY » High
0
0
ns
2, 4
tPHHEH
NOTE:
1. See 5 V VCC Alternative CE » Controlled Writes for Notes 1 through 5.
30
LH28F008SC-150
PARAMETER
100
100
2
ns
8M (1M × 8) Flash Memory
LH28F008SC
ALTERNATIVE CE » - Controlled Writes1 (Continued)
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
LH28F008SC-856
SYMBOL
LH28F008SC-907 LH28F008SC-1207
PARAMETER
UNIT NOTE
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
tAVAV
Write Cycle Time
85
90
120
ns
tPHEL
RP » High Recovery to
CE » Going Low
1
1
1
µs
tWLEL
WE Setup to CE »
Going Low
0
0
0
ns
tELEH
CE » Pulse Width
50
50
50
ns
tPHHEH
RP » VHH Setup to CE »
Going High
100
100
100
ns
2
tVPEH
VPP Setup to CE »
Going High
100
100
100
ns
2
tAVEH
Address Setup to CE »
Going High
40
40
40
ns
3
tDVEH
Data Setup to CE » Going High
40
40
40
ns
3
tEHDX
Data Hold from CE » High
5
5
5
ns
tEHAX
Address Hold from CE » High
5
5
5
ns
tEHWH
WE Hold from CE » High
0
0
0
ns
tEHEL
CE » Pulse Width High
25
25
25
ns
tEHRL
CE » High to RY »/BY » Going Low
tEHGL
Write Recovery before Read
0
0
0
µs
tQVVL
VPP Hold from Valid SRD,
RY »/BY » High
0
0
0
ns
2, 4
tQVPH
RP » VHH Hold from Valid SRD,
RY »/BY » High
0
0
0
ns
2, 4
90
90
90
2
ns
NOTES:
1. In systems where CE » defines the write pulse width (within a longer WE » timing waveform), all setup, hold, and inactive WE »
times should be measured relative to the CE » waveform.
2. Sampled, not 100% tested.
3. Refer to Command Definitions Table for valid A IN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP » should be held at VHH) until determination of block erase, byte write,
or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration)
for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characteristics.
31
LH28F008SC
8M (1M × 8) Flash Memory
1
ADDRESSES (A)
2
VIH
3
AIN
VIL
tAVAV
4
5
6
VALID
SRD
DIN
AIN
tAVEH
tEHAX
WE (E)
OE (G)
CE (E)
VIH
VIL
tWLEL
tEHWH
tEHGL
VIH
VIL
tEHEL
tEHQV1, 2, 3, 4
VIH
VIL
tELEH
tDVEH
tEHDX
DATA (D/Q)
VIH
HIGH-Z
VIL
DIN
DIN
tEHRL
tPHEL
RY/BY (R)
VIH
VIL
tPHHEH
tQVPH
tVPEH
tQVVL
VHH
RP (P)
VIH
VIL
VPPH3, 2, 1
VPP (V)
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or byte write set-up.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 17. Alternate AC Waveform for CE » Controlled Write Operations
32
008SC-17
8M (1M × 8) Flash Memory
LH28F008SC
RESET OPERATIONS
RY/BY (R)
RP (P)
VIH
VIL
VIH
VIL
tPLPH
A. Reset During Read Array Mode
RY/BY (R)
VIH
VIL
tPLRH
RP (P)
VIH
VIL
tPLPH
B. Reset During Block Erase, Byte Write, or Lock-Bit Configuration
28F008SC-18
Figure 18. AC Waveform for Reset Operation
Reset AC Specifications1
VCC = 3.3 V
SYMBOL
VCC = 5 V
PARAMETER
UNIT
MIN.
tPLPH
RP » Pulse Low Time (If RP » is tied to VCC, this
specification is not applicable)
tPLRH
RP » Low to Reset during Block Erase, Byte Write, or
Lock-Bit Configuration
MAX.
100
MIN.
100
20
NOTE
MAX.
ns
12
µs
2,3
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP » is asserted while a block erase, byte write, or lock-bit configuration operation is not executing,
the reset will complete within 100 ns.
3. A reset time tPHQV, is required from the latter of RY »/BY » or RP » going high until outputs are valid.
33
LH28F008SC
8M (1M × 8) Flash Memory
BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE3, 4
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
SYM.
PARAMETER
VPP = 3.3 V
VPP = 53 V
VPP = 12 V
UNIT
NOTE
TBD
µs
2
0.4
TBD
sec
2
1.1
0.8
TBD
sec
2
TBD
11.6
9.7
TBD
µs
2
TBD
1.1
0.8
TBD
sec
2
5
7
5
6
µs
9.6
12
9.6
12
µs
TYP.1
MIN.
MAX.
TYP.1
MIN.
MAX.
TYP.1
MIN.
MAX.
Byte Write Time
17
15
TBD
9.3
8.2
TBD
7.6
6.7
Block Write Time
1.1
1
TBD
0.6
0.5
TBD
0.5
tWHQV2
tEHQV2
Block Erase Time
1.8
1.5
TBD
1.2
1
TBD
tWHQV3
tEHQV3
Set Lock-Bit Time
21
18
TBD
13.3
11.2
tWHQV4
tEHQV4
Clear Block Lock-Bits
Time
1.8
1.5
TBD
1.2
1
tWHRH1
tEHRH1
Byte Write Suspend
Latency Time to Read
6
7
tWHRH2
tEHRH2
Erase Suspend
Latency Time to Read
16.2
20
tWHQV1
tEHQV1
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
SYM.
PARAMETER
VPP = 53 V
VPP = 12 V
UNIT
NOTE
TBD
µs
2
0.3
TBD
sec
2
1.0
0.3
TBD
sec
2
TBD
10
7.8
TBD
µs
2
TBD
1.0
0.3
TBD
sec
2
5
6
4
5
µs
9.6
12
9.6
12
µs
TYP.1
MIN.
MAX.
TYP.1
MIN.
MAX.
8
6.5
TBD
6
4.8
Block Write Time
0.5
0.4
TBD
0.4
tWHQV2
Block Erase Time
tEHQV2
1.1
0.9
TBD
tWHQV3
Set Lock-Bit Time
tEHQV3
12
9.5
tWHQV4
Clear Block Lock-Bits Time
tEHQV4
1.1
0.9
tWHQV1
Byte Write Time
tEHQV1
tWHRH1 Byte Write Suspend
tEHRH1 Latency Time to Read
tWHRH2 Erase Suspend Latency
tEHRH2 Time to Read
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based
on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled but not 100% tested.
34
8M (1M × 8) Flash Memory
LH28F008SC
44SOP (SOP044-P-0600)
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
44
23
13.40 [0.528]
13.00 [0.512]
1
16.40 [0.646]
15.60 [0.614]
14.40 [0.567]
SEE
DETAIL
22
0.20 [0.008]
0.10 [0.004]
28.40 [1.118]
28.00 [1.102]
2.9 [0.114]
2.5 [0.098]
DETAIL
1.275 [0.050]
0.15 [0.006]
1.275 [0.050]
0.25 [0.010]
0.05 [0.002]
2.9 [0.114]
2.5 [0.098]
3.25 [0.128]
2.45 [0.096]
0.25 [0.010]
0.05 [0.002]
1.275 [0.050]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
0 - 10°
0.80 [0.031]
44SOP
35
LH28F008SC
8M (1M × 8) Flash Memory
42CSP (CSP042-P-0808)
8.20 [0.323]
7.80 [0.307]
INDEX
8.20 [0.323]
7.80 [0.307]
0.10 [0.004]
0.40 [0.016]
TYP.
(See Detail)
0.67 [0.026]
TYP.
0.48 [0.019]
0.42 [0.017]
DIMENSIONS IN MM [INCHES]
36
MAXIMUM LIMIT
MINIMUM LIMIT
0.25 [0.010]
MIN.
1.0 [1.039]
TYP.
1.0 [1.039]
TYP.
1.0 [1.039] 1.0 [1.039]
TYP.
TYP.
1.20 [0.047]
MAX.
DETAIL
0.10 [0.004]
0.30 [0.012]
0.15 [0.006]
42CSP
8M (1M × 8) Flash Memory
LH28F008SC
40TSOP (TSOP040-P-1020)
40
1
0.50 [0.020]
TYP.
10.20 [0.402]
9.80 [0.386]
0.25 [0.010]
0.15 [0.006]
20
21
1.10 [0.043]
0.90 [0.035]
SEE DETAIL
1.19
[0.047]
MAX.
0.49 [0.019]
0.39 [0.015]
DETAIL
0.125 [0.005]
18.60 [0.732]
18.20 [0.717]
19.30 [0.760]
18.70 [0.736]
20.30 [0.799]
19.70 [0.776]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
0.49 [0.019]
0.39 [0.015]
0.22 [0.009]
0.02 [0.001]
0 - 10°
0.18 [0.007]
0.08 [0.003]
40TSOP
ORDERING INFORMATION
LH28F008SC
Device Type
X
Package
-85
Speed
85 Access Time (ns)
T 40-pin, 1.2 mm x 10 mm x 20 mm TSOP (Type I) (TSOP040-P-1020)
N 44-pin, 600-mil SOP (SOP044-P-0600)
B 42-pin, .67 mm x 8 mm2 CSP (CSP042-P-0808)
8M (1M x 8) Flash Memory
Example: LH28F008SCT-85 (1M x 8) Flash Memory, 85 ns, 40-pin TSOP)
28F008SC-19
37
LH28F008SC
8M (1M × 8) Flash Memory
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
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Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Reference Code SMT96114