SHARP LH28F016SAT-70

LH28F016SA
FEATURES
•
•
•
•
•
•
•
16M (1M × 16, 2M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
User-Configurable x8 or x16 Operation
User-Selectable 3.3 V or 5 V VCC
3/5
1
56
CE1
2
55
WE
70 ns Maximum Access Time
NC
3
54
OE
0.43 MB/sec Write Transfer Rate
A20
4
53
RY/BY
A19
5
52
DQ15
100,000 Erase Cycles per Block
A18
6
51
DQ7
32 Independently Lockable Blocks (64K)
A17
7
50
DQ14
A16
8
49
DQ6
VCC
9
48
GND
A15
10
47
DQ13
A14
11
46
DQ5
A13
12
45
DQ12
Revolutionary Architecture
– Pipelined Command Execution
– Write During Erase
– Command Superset of
Sharp LH28F008SA
• 50 µA (Typ.) ICC in CMOS Standby
• 1 µA (Typ.) Deep Power-Down
• State-of-the-Art 0.55 µm ETOX™ Flash
Technology
• 56-Pin, 1.2 mm × 14 mm × 20 mm
TSOP (Type I) Package
WP
A12
13
44
DQ4
CE0
14
43
VCC
VPP
15
42
GND
RP
16
41
DQ11
A11
17
40
DQ3
A10
18
39
DQ10
A9
19
38
DQ2
A8
20
37
VCC
GND
21
36
DQ9
A7
22
35
DQ1
A6
23
34
DQ8
A5
24
33
DQ0
A4
25
32
A0
A3
26
31
BYTE
A2
27
30
NC
A1
28
29
NC
28F016SAT-1
Figure 1. TSOP Configuration
1
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
DQ8 - DQ15
DQ0 - DQ7
OUTPUT
BUFFER
OUTPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
I/O
LOGIC
DATA
QUEUE
REGISTERS
ID
REGISTER
3/5
BYTE
CSR
OUTPUT
MULTIPLEXER
PAGE
BUFFERS
CE0
CE1
OE
ESRs
CUI
WE
WP
RP
DATA
COMPARATOR
ADDRESS
COUNTER
...
64KB BLOCK 31
...
64KB BLOCK 30
X-DECODER
64KB BLOCK 1
ADDRESS
QUEUE
LATCHES
Y GATING/SENSING
Y-DECODER
64KB BLOCK 0
INPUT
BUFFER
...
A0 - A20
WSM
PROGRAM/
ERASE
VOLTAGE
SWITCH
RY/BY
VPP
3/5
VCC
GND
28F016SAT-2
Figure 2. LH28F016SA Block Diagram (Architectural Evolution Includes Page Buffers,
Queue Registers and Extended Status Registers)
2
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A0
input buffer is turned off when BYTE is high).
A1 - A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64K block. A6 - A15 selects
1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are
latched during Data Writes.
A16 - A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ0 - DQ7
DQ8 - DQ15 INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CE »0, CE »1
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE »0 or CE »1 high, the device is de-selected and power
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE » 0, CE »1 must be low to select the device. All timing
specifications are the same for both signals. Device Selection occurs with the latter
falling edge of CE »0 or CE »1. The first rising edge of CE »0 or CE »1 disables the device.
RP »
INPUT
RESET/POWER-DOWN: RP » low places the device in a Deep Power-Down state. All
circuits that burn static power, even those circuits enabled in standby mode, are
turned off. When returning from Deep Power-Down, a recovery time of 400 ns
(VCC = 5.0 V ± 0.25 V) is required to allow these circuits to power-up. When RP»
goes low, any current or pending WSM operation(s) are terminated, and the device
is reset. All Status Registers return to ready (with all status flags cleared).
OE »
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE » is high.
NOTE: CE »X overrides OE », and OE » overrides WE.
WE
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
OPEN DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RB »/BY » high indicates that the WSM is ready
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE » or CE »0, CE »1 are high), except if a RY »/BY »
Pin Disable command is issued.
RY »/BY »
3
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
PIN DESCRIPTION (Continued)
SYMBOL
TYPE
NAME AND FUNCTION
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP is low, those locked blocks as reflected by the Block-Lock Status
bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP » transitions low (deep power-down mode).
INPUT
BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output
on DQ0 - DQ7, and DQ8 - DQ15 float. Address A0 selects between the high and low
byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer.
Address A1, then becomes the lowest order address.
3/5»
INPUT
3.3/5.0 VOLT SELECT: 3/5» high configures internal circuits for 3.3 V operation.
3/5» low configures internal circuits for 5.0 V operation.
NOTES: Reading the array with 3/5» high in a 5.0 V system could damage the
device. There is a significant delay from 3/5» » Switching to valid data.
VPP
SUPPLY
ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing
words/bytes/pages into the flash array.
VCC
SUPPLY
DEVICE POWER SUPPLY (3.3 V ±0.3 V, 5.0 V ±0.5 V): Do not leave any
power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
WP
BYTE
NC
NO CONNECT: No internal connection to die, lead may be driven or left floating.
INTRODUCTION
DESCRIPTION
Sharp’s LH28F016SA 16M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
5 V single voltage operation and very high read/write performance, the LH28F016SA is also the ideal choice for
designing embedded mass storage flash memory systems.
The LH28F016SA is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M × 8.
The LH28F016SA includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 3.
The LH28F016SA is a very high density, highest performance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F008SA 8M
Flash memory), extended cycling, low power 3.3 V
operation, very fast write and read performance and
selective block locking provide a highly flexible memory
component suitable for high density memory cards.
Resident Flash Arrays and PCMCIA-ATA Flash Drives.
The LH28F016SA’s dual read voltage enables the
design of memory cards which can interchangeably be
read/written in 3.3 V and 5.0 V systems. Its x8/x16
architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp’s 0.55 µm ETOX™ process technology, the
LH28F016SA is the most cost-effective, high-density
3.3 V flash memory.
4
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F016SA:
• 3.3 V Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection
A 3/5 » input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
The LH28F016SA will be available in a 56-pin,
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) package. This form factor and pinout allow for very high board
layout densities.
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
A Command User Interface (CUI) serves as the system interface between the microprocessor or
microcontroller and the internal memory operation.
• A Compatible Status Register (CSR) which is 100%
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the LH28F008SA 8M Flash memory.
compatible with the LH28F008SA Flash memory’s
Status Register. This register, when used alone, provides a straightforward upgrade capability to the
LH28F016SA from a LH28F008SA-based design.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• A Global Status Register (GSR) which informs the
•
•
•
•
•
•
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes During Erase
Software Locking of Memory Blocks
Two-Byte Successive Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 6 µs, a 33% improvement over the LH28F008SA. A Block Erase operation
erases one of the 32 blocks in typically 0.6 seconds,
independent of the other blocks, which is about 65%
improvement over the LH28F008SA.
The LH28F016SA incorporates two Page Buffers of
256 Bytes (128 Words) each to allow page data writes.
This feature can improve a system write performance
over previous flash memory devices.
All operations are started by a sequence of Write
commands to the device. Three Status Registers (described in detail later) and a RY »/BY » output pin provide
information on the progress of the requested operation.
While the LH28F008SA requires an operation to complete before the next operation can be requested, the
LH28F016SA allows queuing of the next operation while
the memory executes the current operation. This eliminates system overhead when writing several bytes in a
row to the array or erasing several blocks at the same
time. The LH28F016SA can also perform write operations to one block of memory while performing erase of
another block.
The LH28F016SA provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the
block. In addition, the LH28F016SA has a master Write
Protect pin (WP ») which prevents any modifications to
memory blocks whose lock-bits are set.
The LH28F016SA contains three types of Status
Registers to accomplish various functions:
system of command Queue status, Page Buffer status, and overall Write State Machine (WSM) status.
• 32 Block Status Registers (BSRs) which provide
block-specific status information such as the block
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4 and 5.
The LH28F016SA incorporates an open drain
RY »/BY » outpin. This feature allows the user to OR-tie
many RY »/BY » pins together in a multiple memory configuration such as a Resident Flash Array.
The LH28F016SA also incorporates a dual chipenable function with two input pins, CE 0» and CE 1» . These
pins have exactly the same functionality as the regular
chip-enable pin CE » on the LH28F008SA. For minimum
chip designs, CE »1 may be tied to ground and use CE »0
as the chip enable input. The LH28F016SA uses the
logical combination of these two signals to enable or
disable the entire chip. Both CE »0 and CE »1 must be active low to enable the device and if either one becomes
inactive, the chip will be disabled. This feature, along
with the open drain RY »/BY » pin, allows the system designer to reduce the number of control pins used in a
large array of 16M devices.
The BYTE
» » pin allows either x8 or x16 read/writes to
the LH28F016SA. BYTE
» » at logic low selects 8-bit mode
with address A0 selecting between low byte and high
byte. On the other hand, BY T
» E » at logic high enables
16-bit operation with address A1 becoming the lowest
order address and address A0 is not used (don’t care).
A block diagram is shown in Figure 2.
The LH28F016SA is specified for a maximum access
time of each version, as follows:
OPERATING
TEMPERATURE
VCC SUPPLY
MAX. ACCESS
(TACC)
0 - 70°C
4.75 - 5.25 V
70 ns
0 - 70°C
4.5 - 5.5 V
80 ns
0 - 70°C
3.0 - 3.6 V
120 ns
5
LH28F016SA
The LH28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 2 mA at
5.0 V (1 mA at 3.3 V).
A Deep Power-Down mode of operation is invoked
when the RP » (called PWD on the LH28F008SA) pin
transitions low. This mode brings the device power consumption to less than 5 µA, typically, and provides additional write protection by acting as a device reset pin
during power transitions. A reset time of 400 ns
(VCC = 5.0 V ± 0.25 V system) is required from RP »
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR registers are cleared.
A CMOS Standby mode of operation is enabled when
either CE 0» or CE 1» transitions high and RP » stays high with
all input control pins at CMOS levels. In this mode, the
device typically draws an ICC standby current of 10 µA.
16M (1M × 16, 2M × 8) Flash Memory
MEMORY MAP
1FFFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
000000H
64KB BLOCK
31
64KB BLOCK
30
64KB BLOCK
29
64KB BLOCK
28
64KB BLOCK
27
64KB BLOCK
26
64KB BLOCK
25
64KB BLOCK
24
64KB BLOCK
23
64KB BLOCK
22
64KB BLOCK
21
64KB BLOCK
20
64KB BLOCK
19
64KB BLOCK
18
64KB BLOCK
17
64KB BLOCK
16
64KB BLOCK
15
64KB BLOCK
14
64KB BLOCK
13
64KB BLOCK
12
64KB BLOCK
11
64KB BLOCK
10
64KB BLOCK
9
64KB BLOCK
8
64KB BLOCK
7
64KB BLOCK
6
64KB BLOCK
5
64KB BLOCK
4
64KB BLOCK
3
64KB BLOCK
2
64KB BLOCK
1
64KB BLOCK
0
28F016SAT-3
Figure 3. LH28F016SA Memory Map
(Byte-Wide Mode)
6
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
Extended Status Registers Memory Map
x8 MODE
x16 MODE
A[20:0]
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
.
.
.
A[20:1] (NOTE)
1F0006H
RESERVED
1F0005H
GSR
1F0004H
RESERVED
1F0003H
BSR31
1F0002H
RESERVED
1F0001H
RESERVED
1F0000H
.
.
.
010002H
RESERVED
BSR0
RESERVED
RESERVED
F8001H
F8000H
RESERVED
000006H
GSR
F8002H
08001H
RESERVED
RESERVED
F8003H
RESERVED
000005H
GSR
000004H
RESERVED
000003H
BSR0
000002H
RESERVED
000001H
RESERVED
000000H
00003H
00002H
00001H
00000H
28F016SAT-4
Figure 4. Extended Status Register
Memory Map (Byte-Wide Mode)
NOTE: In word-wide mode A0 don't care, address values
are ignored A0.
28F016SAT-5
Figure 5. Extended Status Register
Memory Map (Word-Wide Mode)
7
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations for Word-Wide Mode (BY T
» E » = VIH)
RP »
CE »1
CE »0
OE »
WE
A1
DQ0 - DQ15
RY »/BY »
NOTE
Read
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
1, 2, 7
Output Disable
VIH
VIL
VIL
VIH
VIH
X
High-Z
X
1, 6, 7
Standby
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High-Z
X
1, 6, 7
Deep Power-Down
VIL
X
X
X
X
X
High-Z
VOH
1, 3
Manufacturer ID
VIH
VIL
VIL
VIL
VIH
VIL
0089H
VOH
4
Device ID
VIH
VIL
VIL
VIL
VIH
VIH
66A0H
VOH
4
Write
VIH
VIL
VIL
VIH
VIL
X
DIN
X
1, 5, 6
MODE
Bus Operations For Byte-Wide Mode (BY T
» E » = VIL)
RP »
CE »1
CE »0
OE »
WE
A0
DQ0 - DQ7
RY »/BY »
NOTE
Read
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
1, 2, 7
Output Disable
VIH
VIL
VIL
VIH
VIH
X
High-Z
X
1, 6, 7
Standby
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High-Z
X
1, 6, 7
Deep Power-Down
VIL
X
X
X
X
X
High-Z
VOH
1, 3
Manufacturer ID
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
4
Device ID
VIH
VIL
VIL
VIL
VIH
VIH
A0H
VOH
4
Write
VIH
VIL
VIL
VIH
VIL
X
DIN
X
1, 5, 6
MODE
NOTES:
1. X can be VIH or VIL for address or control pins except for RY »/BY », which is either VOL or VOH .
2. RY »/BY » output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY »/BY » will be at VOH if it is tied to VCC through a resistor. When the RY /» BY » at VOH is independent of OE » while a WSM
operation is in progress.
3. RP » at GND ± 0.2 V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. A 0 and A1, at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully completed when VPP = VPPH.
6. While the WSM is running, RY »/BY » in Level-Mode (default) stays at VOL until all operations are complete. RY »/BY » goes to
VOH when the WSM is not busy or in erase suspend mode.
7. RY »/BY » may be at VOL while the WSM is busy performing various operations. For example, a status register read during a
write operation.
8
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
NOTE
OPER.
ADDRESS
DATA
OPER.
ADDRESS
DATA
Read Array
Write
X
FFH
Read
AA
AD
Intelligent Identifier
Write
X
90H
Read
IA
ID
1
Read Compatible Status Register
Write
X
70H
Read
X
CSRD
2
Clear Status Register
Write
X
50H
Word/Byte Write
Write
X
40H
Write
WA
WD
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
4
Erase Suspend/Resume
Write
X
B0H
Write
X
D0H
4
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
3
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WASM = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued,while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed. When you use Erase Suspend/
Resume command, we recommend to issue serial Block Erase command (20H, D0H) and Resume command (D0H). (Refer to Performance Enhancement Command Bus Definitions.)
9
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA Performance Enhancement Command Bus Definitions
FIRST BUS CYCLE
COMMAND
SECOND BUS CYCLE
THIRD BUS CYCLE
MODE
NOTE
OPER. ADDR.
DATA
OPER. ADDR.
DATA
Read
GSRD
BSRD
OPER.
ADDR.
DATA
Read Extended
Status Register
Write
X
71H
Page Buffer Swap
Write
X
72H
Read Page Buffer
Write
X
75H
Read
PA
PD
Single Load to
Page Buffer
Write
X
74H
Write
PA
PD
x8
Write
X
E0H
Write
X
BCL
Write
X
BCH
4, 6, 10
x16
Write
X
E0H
Write
X
WCL
Write
X
WCH
4, 5,
6, 10
x8
Write
X
0CH
Write
A0
BC
(L, H)
Write
WA
BC (H, L)
3, 4,
9, 10
x16
Write
X
0CH
Write
X
WCL
Write
WA
WCH
4, 5, 10
x8
Write
X
FBH
Write
A0
WD
(L, H)
Write
WA
WD (H, L)
3
Block
Erase/Confirm
Write
X
20H
Write
BA
D0H
Write
X
D0H
11
Lock Block/Confirm
Write
X
77H
Write
BA
D0H
Upload Status
Bits/Confirm
Write
X
97H
Write
X
D0H
Upload Device
Information
Write
X
99H
Write
X
D0H
Erase All Unlocked
Blocks/Confirm
Write
X
A7H
Write
X
D0H
RY »/BY » Enable to
Level-Mode
Write
X
96H
Write
X
01H
8
RY »/BY » Pulse-OnWrite
Write
X
96H
Write
X
02H
8
RY »/BY » Pulse-OnErase
Write
X
96H
Write
X
03H
8
RY »/BY » Disable
Write
X
96H
Write
X
04H
8
Sleep
Write
X
F0H
Abort
Write
X
80H
Sequential Load to
Page Buffer
Page Buffer Write
to Flash
Two-Byte Write
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don’t Care
10
RA
1
7
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
WC (L, H) = Word Count (Low, High)
BC (L, H) = Byte Count (Low, High)
WD (L, H) = Write Data (Low, High)
2
Write
X
D0H
11
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 4 and 5 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual
lock-bit status.
3. A0 is automatically complemented to load second byte of data. BY T
» E » must be at VIL. A0 value determines which WD/BC is supplied
first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.
5. In x16 mode, only the lower byte DQ0 - DQ 7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY »/BY » output to one of two pulse-modes or enable and disable the RY »/BY » function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
LH28F016SU User’s Manual.
10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.
11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.
Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPL and VPPH.
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
11
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
GLOBAL STATUS REGISTER
WSMS
OSS
DOS
DSS
QS
PBAS
PBS
PBSS
7
6
5
4
3
2
1
0
GSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
GSR.6 = OPERATION SUSPEND STATUS (OSS)
1 = Operation Suspended
0 = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS (DOS)
1 = Operation Unsuccessful
0 = Operation Successful or Currently Running
GSR.4 = DEVICE SLEEP STATUS(DSS)
1 = Device in Sleep
0 = Device Not in Sleep
MATRIX 5/4
00
01
10
11
= Operation Successful or currently Running
= Device in Sleep Mode or Pending Sleep
= Operation Unsuccesful
= Operation Unsuccessful or Aborted
GSR.3 = QUEUE STATUS (QS)
1 = Queue Full
0 = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS (PBAS)
1 = One or Two Page Buffers Available
0 = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS (PBS)
1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy
GSR.0 = PAGE BUFFER SELECT STATUS (PBSS)
1 = Page Buffer 1 Selected
0 = Page buffer 0 Selected
12
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Block Lock, Suspend, any
RY »/BY » reconfiguration, Upload Status Bits, Erase or Data
Write) before the appropriate Status bit (OSS or DOS) is
checked for success.
2. If operation currently running, then GSR.7 = 0.
3. If device pending sleep, then GSR.7 = 0.
4. Operation aborted: Unsucccessful due to Abort command.
5. The device contains two Page Buffers.
6. Selected Page Buffer is currently busy with WSM operation.
7. When multiple operations are queued, checking BSR.7
only provides indication of completion for that particular
block. GSR.7 provides indication when all queued operations are completed.
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
BLOCK STATUS REGISTER
BS
BLS
BOS
BOAS
QS
VPPS
R
R
7
6
5
4
3
2
1
0
BSR.7 = BLOCK STATUS (BS)
1 = Ready
0 = Busy
NOTES:
1. RY »/BY » output or BS bit must be checked to determine
completion of an operation (Block Lock, Suspend, Erase or
Data Write) before the appropriate Status bits (BOS, BLS) is
checked for success.
BSR.6 = BLOCK-LOCK STATUS (BLS)
1 = Block Unlocked for Write/Erase
0 = Block Locked for Write/Erase
2. The BOAS bit will not be set until BSR.7 = 1.
BSR.5 = BLOCK OPERATION STATUS (BOS)
1 = Operation Unsuccessful
0 = Operation Successful or Currently Running
4. BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when
polling the BSRs.
BSR.4 = BLOCK OPERATION ABORT STATUS (BOAS)
1 = Operation Aborted
0 = Operation Not Aborted
5. When multiple operations are queued, checking BSR.7 only
provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are
completed.
MATRIX 5/4
00
01
10
11
3. Operation halted via Abort command.
= Operation Successful or Currently Running
= Not a valid Combination
= Operation Unsuccessful
= Operation Aborted
BSR.3 = QUEUE STATUS (QS)
1 = Queue Full
0 = Queue Available
BSR.2 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
13
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
*WARNING: Stressing the device beyond
ELECTRICAL SPECIFICATIONS
the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Absolute Maximum Ratings*
Temperature under bias ......................... 0°C to +80°C
Storage temperature ......................... -65°C to +125°C
VCC = 3.3 V ± 0.3 V Systems4
SYMBOL
TA
PARAMETER
Operating Temperature, Commercial
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
0
70
°C
Ambient Temperature
1
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with Respect to GND
-0.2
14.0
V
2
V
Voltage on any Pin (Except VCC, VPP)
with Respect to GND
-0.5
VCC + 0.5
V
2
I
Current into any Non-Supply Pin
±30
mA
Output Short Circuit Current
100
mA
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
0
70
°C
Ambient Temperature
1
IOUT
3
VCC = 5.0 V ± 0.5 V Systems4
SYMBOL
TA
PARAMETER
Operating Temperature, Commercial
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with Respect to GND
-0.2
14.0
V
2
V
Voltage on any Pin (Except VCC, VPP)
with Respect to GND
-0.5
7.0
V
2
I
Current into any Non-Supply Pin
±30
mA
Output Short Circuit Current
100
mA
IOUT
3
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns.
Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
14
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
Capacitance
For 3.3 V Systems
SYMBOL
TYP.
MAX.
UNITS
Capacitance Looking into an
Address/Control Pin
6
8
pF
TA = 25°C, f = 1.0 MHz
1
COUT
Capacitance Looking into an Output Pin
8
12
pF
TA = 25°C, f = 1.0 MHz
1
CLOAD
Load Capacitance Driven by Outputs for
Timing Specifications
50
pF
For VCC = 3.3 V ±0.3 V
1
Equivalent Testing Load Circuit
2.5
ns
50 Ω transmission line delay
TYP.
MAX.
UNITS
TEST CONDITIONS
Capacitance Looking into an
Address/Control Pin
6
8
pF
TA = 25°C, f = 1.0 MHz
1
COUT
Capacitance Looking into an Output Pin
8
12
pF
TA = 25°C, f = 1.0 MHz
1
Load Capacitance Driven by Outputs for
Timing Specifications
100
pF
For VCC = 5.0 V ±0.5 V
1
CLOAD
30
pF
For VCC = 5.0 V ±0.25 V
Equivalent Testing Load Circuit VCC ± 10%
2.5
ns
25 Ω transmission line delay
Equivalent Testing Load Circuit VCC ± 5%
2.5
ns
83 Ω transmission line delay
CIN
PARAMETER
TEST CONDITIONS
NOTE
For 5.0 V Systems
SYMBOL
CIN
PARAMETER
NOTE
NOTE:
1. Sampled, not 100% tested.
15
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
Timing Nomenclature
For 3.3 V systems timings are measured from where signals cross 1.5 V. For 5.0V systems use the standard JEDEC
crosspoint definitions. Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV
time (t) from CE » (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV
time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)
tDH
tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE » (Chip Enable)
X
Driven, but not necessarily valid
G
OE » (Output Enable)
Z
High Impedance
W
WE (Write Enable)
P
RP » (Deep Power-Down Pin)
R
RY »/BY » (Ready/Busy)
V
Any Voltage Level
Y
3/5 » Pin
5V
VCC at 4.5 V Min.
3V
VCC at 3.0 V Min.
16
PIN STATES
16M (1M × 16, 2M × 8) Flash Memory
2.4
INPUT
0.45
2.0
0.8
TEST POINTS
LH28F016SA
2.0
0.8
2.5 ns OF 50 Ω TRANSMISSION LINE
OUTPUT
FROM OUTPUT
UNDER TEST
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
TEST
POINT
TOTAL CAPACITANCE = 50 pF
28F016SAT-8
28F016SAT-6
Figure 6. Transient Input/Output
Reference Waveform (VCC = 5.0 V)
3.0
INPUT 1.5
0.0
Figure 8. Transient Equivalent Testing
Load Circuit (VCC = 3.3 V)
2.5 ns OF 25 Ω TRANSMISSION LINE
TEST POINTS
1.5 OUTPUT
FROM OUTPUT
UNDER TEST
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
28F016SAT-7
TEST
POINT
TOTAL CAPACITANCE = 100 pF
28F016SAT-9
Figure 7. Transient Input/Output
Reference Waveform (VCC = 3.3 V)
Figure 9. Transient Equivalent Testing
Load Circuit (VCC = 5.0 V)
2.5 ns OF 83 Ω TRANSMISSION LINE
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 30 pF
28F016SAT-10
Figure 10. High Speed Transient Equivalent
Testing Load Circuit (VCC = 5.0 V ±5%)
17
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
DC Characteristics
VCC = 3.3 V ±0.3 V, TA = 0°C to +70°C
3/5 » = Pin Set High for 3.3 V Operations
SYMBOL
PARAMETER
TYP.
MAX.
UNITS
TEST CONDITIONS
NOTE
IIL
Input Load Current
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±10
µA
VCC = VCC MAX., VIN = VCC or GND
1
µA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VCC ±0.2 V
BYTE, WP, 3/5 » = VCC ±0.2 V or GND
±0.2 V
1, 4
50
ICCS
ICCD
ICCR1
18
MIN.
100
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
1
4
mA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VIH
BYTE, WP, 3/5 » = VIH or VIL
1
5
µA
RP » = GND ±0.2 V
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = GND ±0.2 V or VCC ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE »0, CE »1 = VIL,
BYTE = VIL or VIH
Inputs = VIL or VIH
f = 8 MHz, IOUT = 0 mA
1, 3, 4
1, 3, 4
30
35
1
ICCR2
VCC Read Current
15
20
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = VCC ±0.2 V or GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE »0, CE »1 = VIL,
BYTE = VIH or VIL
Inputs = VIL or VIH
f = 4 MHz, IOUT = 0 mA
ICCW
VCC Write Current
8
12
mA
Word/Byte Write in Progress
1
ICCE
VCC Block Erase Current
6
12
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend
Current
3
6
mA
CE »0, CE »1 = VIH
Block Erase Suspended
1, 2
IPPS
VPP Standby Current
±1
±10
µA
VPP ≤ VCC
1
IPPD
VPP Deep Power-Down
Current
0.2
5
µA
RP » = GND ±0.2 V
1
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
DC Characteristics (Continued)
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
3/5 » = Pin Set High for 3.3 V Operations
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
200
µA
VPP > VCC
1
IPPR
VPP Read Current
IPPW
VPP Write Current
10
15
mA
VPP = VPPH, Word/Byte
Write in Progress
1
IPPE
VPP Erase Current
4
10
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend
Current
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
VOL
Output Low Voltage
0.4
V
VCC = VCC MIN. and
IOL = 4 mA
2.4
V
IOH = -2.0 mA
VCC = VCC MIN.
VCC - 0.2
V
IOH = -100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
12.0
0.0
6.5
V
11.4
12.6
V
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3 V, VPP = 5.0 V, T = 25°C. These currents are valid for all
product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in Static operation.
4. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
19
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
DC Characteristics
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
3.5 » Pin Set Low for 5 V Operations
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IIL
Input Load Current
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±10
µA
VCC = VCC MAX., VIN = VCC or GND
1
µA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VCC ±0.2 V
BYTE, WP, 3/5 » # = V CC ±0.2 V or
GND ±0.2 V
1, 4
50
ICCS
ICCD
ICCR1
100
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
2
4
mA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VIH
BYTE, WP, 3/5 » = VIH or VIL
1
5
µA
RP » = GND ±0.2 V
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = GND ±0.2 V or VCC ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE »0, CE »1 = VIL,
BYTE = VIL or VIH
Inputs = VIL or VIH
f = 10 MHz, IOUT = 0 mA
1, 3, 4
1, 3, 4
50
60
1
ICCR2
VCC Read Current
30
35
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = VCC ±0.2 V or GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE »0, CE »1 = VIL,
BYTE = VIH or VIL
Inputs = VIL or VIH
f = 5 MHz, IOUT = 0 mA
ICCW
VCC Write Current
25
35
mA
Word/Byte Write in Progress
1
ICCE
VCC Block Erase Current
18
25
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend
Current
5
10
mA
CE »0, CE »1 = VIH
Block Erase Suspended
1, 2
IPPS
VPP Standby Current
±10
µA
VPP ≤ VCC
1
IPPD
VPP Deep Power-Down
Current
5
µA
RP » = GND ±0.2 V
1
20
0.2
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
DC Characteristics (Continued)
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
3.5 » Pin Set Low for 5 V Operations
SYMBOL
PARAMETER
TYPE
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IPPR
VPP Read Current
65
200
µA
VPP > VCC
1
IPPW
VPP Write Current
7
12
mA
VPP = VPPH, Word/Byte
Write in Progress
1
IPPE
VPP Erase Current
5
10
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend
Current
65
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VCC = VCC MIN. and
IOL = 5.8 mA
VCC 0.85
V
IOH = -2.5 mA
VCC = VCC MIN.
VCC - 0.4
V
IOH = -100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
12.0
0.0
6.5
V
11.4
12.6
V
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 5.0 V, T = 25°C. These currents are valid for all
product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation.
4. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
21
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
AC Characteristics - Read Only Operations1
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 3.3 V ± 0.3V
MIN.
NOTE
tAVAV
Read Cycle Time
120
ns
tAVEL
Address Setup to CE » Going Low
10
ns
3, 4
tAVGL
Address Setup to OE » Going Low
0
ns
3, 4
tAVQV
Address to Output Delay
120
ns
tELQV
CE » to Output Delay
120
ns
tPHQV
RP » High to Output Delay
620
ns
tGLQV
OE » to Output Delay
45
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
22
UNITS
MAX.
Output Hold from Address, CE » or
OE » change, whichever occurs first
0
50
0
30
0
2
tFLQV
tFHQV
BYTE to Output Delay
120
ns
3
tFLQZ
BYTE Low to Output in High Z
30
ns
3
tELFL
tELFH
CE » Low to BYTE High or Low
5
ns
3
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
AC Characteristics - Read Only Operations1 (Continued)
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 5.0 V ± 0.25 V
MIN.
MAX.
VCC = 5.0 V ± 0.5 V
MIN.
UNITS
NOTE
MAX.
tAVAV
Read Cycle Time
70
80
ns
tAVEL
Address Setup to CE » Going Low
10
10
ns
3, 4
tAVGL
Address Setup to OE » Going Low
0
0
ns
3, 4
tAVQV
Address to Output Delay
70
80
ns
tELQV
CE » to Output Delay
70
80
ns
tPHQV
RP » High to Output Delay
400
480
ns
tGLQV
OE » to Output Delay
30
35
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
Output Hold from Address, CE » or
OE » change, whichever occurs first
0
0
25
0
30
0
25
0
30
0
2
tFLQV
tFHQV
BYTE to Output Delay
70
80
ns
3
tFLQZ
BYTE Low to Output in High Z
25
30
ns
3
tELFL
tELFH
CE » Low to BYTE High or Low
5
5
ns
3
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 5 and 6.
2. OE » may be delayed up to t ELQV - tGLQV after the falling edge of CE » without impact on tELQV.
3. Sampled, not 100% tested.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
23
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
VCC
POWER-UP
ADDRESSES (A)
STANDBY
DEVICE AND
ADDRESS
SELECTION
VIH
OUTPUTS ENABLED
ADDRESSES STABLE
VIL
DATA VALID
...
VCC
STANDBY POWER-DOWN
...
tAVAV
CEX (E)
(NOTE)
VIH
...
VIL
tAVEL
OE (G)
tEHQZ
VIH
...
VIL
tAVGL
WE (W)
tGHQZ
...
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q)
VOH
...
HIGH-Z
VALID OUTPUT
HIGH-Z
...
VOL
tAVQV
5.0 V
VCC
GND
tPHQV
RP (P)
VIH
VIL
NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
Figure 11. Read Timing Waveforms
24
28F016SAT-11
16M (1M × 16, 2M × 8) Flash Memory
ADDRESSES (A)
LH28F016SA
...
VIH
ADDRESSES STABLE
VIL
...
tAVAV
CEX (E)
(NOTE)
VIH
...
VIL
tEHQZ
tAVEL = tELFL
OE (G)
VIH
tAVEL
VIL
tELFL
...
tGHQZ
tAVGL
tFLQV = tAVQV
tGLQV
BYTE (F)
VIH
...
VIL
tELQV
tOH
tGLQX
tELQX
DATA (DQ0 - DQ7)
VOH
...
HIGH-Z
DATA
OUTPUT
...
VOL
DATA
OUTPUT
HIGH-Z
tAVQV
tFLQZ
DATA (DQ8 - DQ15)
VOH
VOL
HIGH-Z
DATA
OUTPUT
NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
HIGH-Z
28F016SAT-12
Figure 12. BY »TE » Timing Waveforms
25
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
VCC POWER UP
RP (P)
tYHPH
tYLPH
3/5 (Y)
tPLYL
5.0 V
4.5 V
3.3 V
VCC
(3 V, 5 V)
0V
tPL5V
ADDRESS (A)
VALID
VALID
tAVQV
tAVQV
VALID
3.3 V OUTPUTS
DATA (Q)
VALID
5.0 V OUTPUTS
tPHQV
tPHQV
28F016SAT-13
Figure 13. VCC Power-Up and RP » Reset Waveforms
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTE
tPLYL
tPLYH
RP » Low to 3/5 » Low (High)
0
µs
tYLPH
tYHPH
3/5 » Low (High) to RP » High
2
µs
1
tPL5V
tPL3V
RP » Low to VCC at 4.5 V MIN.
(to VCC at 3.0 V MIN. or 3.6 V MAX.)
0
µs
2
tAVQV
Address Valid to Data Valid for VCC = 5 V ± 10%
80
ns
3
tPHQV
RP » High to Data Valid for VCC = 5 V ± 10%
480
ns
3
NOTES:
CE »0, CE »1 and OE » are switched low after Power-Up.
1. Minimum of 2 µs is required to meet the specified tPHQV times.
2. The power supply may start to switch concurrently with RP » going Low.
3. The address access time and RP » high to data valid time are shown for 5 V VCC operation. Refer to the AC Characteristics Read
Only Operations 3.3 V VCC operation and all other speed options.
26
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
AC Characteristics for WE » - Controlled Command Write Operations1
TA = 0°C to +70°C
SYMBOL
VCC = 3.3 ± 0.3 V
PARAMETER
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
120
ns
tVPWH
VPP Setup to WE Going High
100
ns
tPHEL
RP » Setup to CE » Going Low
480
ns
tELWL
CE » Setup to WE Going Low
10
ns
tAVWH
Address Setup to WE Going High
75
ns
2, 6
tDVWH
Data Setup to WE Going High
75
ns
2, 6
tWLWH
WE Pulse Width
75
ns
tWHDX
Data Hold from WE High
10
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
CE » Hold from WE High
10
ns
tWHWL
WE Pulse Width High
45
ns
tGHWL
Read Recovery before Write
0
ns
tWHRL
WE High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
ns
tPHWL
RP » High Recovery to WE Going Low
1
µs
tWHGL
Write Recovery before Read
95
ns
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
µs
5
µs
4, 5
0.3
s
4
tWHQV1
Duration of Word/Byte Write Operation
tWHQV2
Duration of Block Erase Operation
100
9
3
ns
3
27
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
AC Characteristics for WE » - Controlled Command Write Operations1 (Continued)
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 5.0 ± 0.25 V
TYP.
MIN.
MAX.
VCC = 5.0 ± 0.5 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
70
80
ns
tVPWH
VPP Setup to WE Going High
100
100
ns
tPHEL
RP » Setup to CE » Going Low
480
480
ns
tELWL
CE » Setup to WE Going Low
0
0
ns
tAVWH
Address Setup to WE Going High
50
50
ns
2, 6
tDVWH
Data Setup to WE Going High
50
50
ns
2, 6
tWLWH
WE Pulse Width
40
50
ns
tWHDX
Data Hold from WE High
0
0
ns
2
tWHAX
Address Hold from WE High
10
10
ns
2
tWHEH
CE » Hold from WE High
10
10
ns
tWHWL
WE Pulse Width High
30
30
ns
tGHWL
Read Recovery before Write
0
0
ns
tWHRL
WE High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and
RY »/BY » High
0
0
ns
tPHWL
RP » High Recovery to WE
Going Low
1
1
µs
tWHGL
Write Recovery before Read
60
65
ns
tQVVL
VPP Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY »/BY » High
0
0
µs
4.5
µs
4, 5
0.3
s
4
tWHQV1
Duration of Word/Byte Write
Operation
tWHQV2
Duration of Block Erase Operation
100
6
4.5
100
6
0.3
NOTES:
CE » is defined as the latter of CE »0 or CE »1 going Low or the first of CE »0 or CE »1 going High.
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE » for all Command Write Operations.
28
3
ns
3
16M (1M × 16, 2M × 8) Flash Memory
DEEP
POWER-DOWN
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
LH28F016SA
WRITE VALID
ADDRESS AND DATA
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
WRITE READ
EXTENDED
REGISTER
COMMAND
READ
EXTENDED
STATUS
REGISTER DATA
AIN
tAVAV
A = RA
tAVWH
ADDRESSES (A) VIH
(NOTE 2)
VIL
READ
COMPATIBLE
STATUS
REGISTER DATA
tWHAX
(NOTE 3)
AIN
A = RA
tAVWH tWHAX
tAVAV
CEX (E) VIH
(NOTE 4) V
IL
tWHGL
tWHEH
tELWL
OE (G)
VIH
VIL
tWHWL
tWHQV 1, 2
tGHWL
VIH
WE (W)
VIL
tWLWH
tWHDX
tDVWH
DATA (D/Q)
VIH
HIGH-Z
VIL
DIN
DIN
tPHWL
DIN
DIN
DOUT
tWHRL
VOH
RY/BY (R) V
OL
tRHPL
VIH
RP (P) V
IL
(NOTE 5)
tVPWH
VPP (V)
tQVVL
VPPH
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F016SAT-14
Figure 14. AC Waveforms for Command Write Operations
29
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
AC Characteristics for CE » - Controlled Command Write Operations1
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 3.3 V ± 0.3 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
120
ns
tPHWL
RP » Setup to WE Going Low
480
ns
3
tVPEH
VPP Set up to CE » Going High
100
ns
3
tWLEL
WE Setup to CE » Going Low
0
ns
tAVEH
Address Setup to CE » Going High
75
ns
2, 6
tDVEH
Data Setup to CE » Going High
75
ns
2, 6
tELEH
CE » Pulse Width
75
ns
tEHDX
Data Hold from CE » High
10
ns
2
tEHAX
Address Hold from CE » High
10
ns
2
tEHWH
WE Hold from CE » High
10
ns
tEHEL
CE » Pulse Width High
45
ns
tGHEL
Read Recovery before Write
0
ns
tEHRL
CE » High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
ns
tPHEL
RP » High Recovery to CE » Going Low
1
µs
tEHGL
Write Recovery before Read
95
ns
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
µs
tEHQV1
Duration of Word/Byte Write Operation
5
µs
4, 5
tEHQV2
Duration of Block Erase Operation
0.3
s
4
30
100
9
ns
3
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
AC Characteristics for CE » - Controlled Command Write Operations1 (Continued)
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 5.0 V ± 0.25 V
TYP.
MIN.
MAX.
VCC = 5.0 V ± 0.5 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
70
80
ns
tPHWL
RP » Setup to WE Going Low
480
480
ns
tVPEH
VPP Setup to CE » Going High
100
100
ns
tWLEL
WE Setup to CE » Going Low
0
0
ns
tAVEH
Address Setup to CE » Going High
50
50
ns
2, 6
tDVEH
Data Setup to CE » Going High
50
50
ns
2, 6
tELEH
CE » Pulse Width
40
50
ns
tEHDX
Data Hold from CE » High
0
0
ns
2
tEHAX
Address Hold from CE » High
10
10
ns
2
tEHWH
WE Hold from CE » High
10
10
ns
tEHEL
CE » Pulse Width High
30
50
ns
tGHEL
Read Recovery before Write
0
0
ns
tEHRL
CE » High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and
RY »/BY » High
0
0
ns
tPHEL
RP » High Recovery to CE » Going Low
1
1
µs
tEHGL
Write Recovery before Read
60
80
ns
tQVVL
VPP Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY »/BY » High
0
0
µs
tEHQV1
Duration of Word/Byte Write
Operation
4.5
µs
4, 5
tEHQV2
Duration of Block Erase Operation
0.3
s
4
100
6
4.5
100
6
0.3
3
ns
3
NOTES:
CE » is defined as the latter of CE »0 or CE »1 going Low or the first of CE »0 or CE »1 going High.
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE » for all Command Write Operations.
31
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
DEEP
POWER-DOWN
WRITE VALID
WRITE
ADDRESS AND DATA
DATA-WRITE
(DATA-WRITE) OR
OR ERASE
ERASE CONFIRM
SETUP COMMAND
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
READ
EXTENDED
STATUS
REGISTER DATA
WRITE READ
EXTENDED
REGISTER
COMMAND
AIN
tAVAV
tAVEH
ADDRESSES (A) VIH
(NOTE 2)
VIL
A = RA
(NOTE 3)
AIN
tAVEH
tAVAV
READ
COMPATIBLE
STATUS
REGISTER DATA
tEHAX
tEHAX
VIH
WE (W)
VIL
tEHWH
tWLEL
OE (G)
tEHGL
VIH
VIL
tEHEL
tEHQV 1, 2
tGHEL
CEX (E) VIH
(NOTE 4) VIL
tELEH
tEHDX
tDVEH
DATA (D/Q) VIH
VIL
HIGH-Z
DIN
DIN
DIN
DOUT
tEHRL
tPHEL
RY/BY (R)
DIN
VOH
VOL
tRHPL
RP (P)
VIH
VIL
(NOTE 5)
tVPEH
VPP (V)
tQVVL
VPPH
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 15. Alternate AC Waveforms for Command Write Operations
32
28F016SAT-15
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
AC Characteristics for Page Buffer Write Operations1
TA = 0°C to +70°C
SYMBOL
VCC = 3.3 V ± 0.3 V
PARAMETER
TYP.
tAVAV
Write Cycle Time
tELWL
MIN.
UNITS
NOTE
MAX.
120
ns
CE » Setup to WE Going Low
10
ns
tAVWL
Address Setup to WE Going Low
0
ns
3
tDVWH
Data Setup to WE Going High
75
ns
2
tWLWH
WE Pulse Width
75
ns
tWHDX
Data Hold from WE High
10
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
CE » Hold from WE High
10
ns
tWHWL
WE Pulse Width High
45
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
95
ns
SYMBOL
PARAMETER
VCC = 5.0 V ± 0.25 V
TYP.
MIN.
MAX.
VCC = 5.0 V ± 0.5 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
70
80
ns
tELWL
CE » Setup to WE Going Low
0
0
ns
tAVWL
Address Setup to WE Going Low
0
0
ns
3
tDVWH
Data Setup to WE Going High
50
50
ns
2
tWLWH
WE Pulse Width
40
50
ns
tWHDX
Data Hold from WE High
0
0
ns
2
tWHAX
Address Hold from WE High
10
10
ns
2
tWHEH
CE » Hold from WE High
10
10
ns
tWHWL
WE Pulse Width High
30
30
ns
tGHWL
Read Recovery before Write
0
0
ns
tWHGL
Write Recovery before Read
60
65
ns
NOTES:
CE » is defined as the latter of CE »0 or CE »1 going Low or the first of CE »0 or CE »1 going High.
1. These are WE » controlled write timings, equivalent CE » controlled write timings apply.
2. Sampled, but not 100% tested.
3. Address must be valid during the entire WE » Low pulse.
33
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
tWHEH
CEX (E)
tELWL
WE (W)
tAVWL
tWLWH
tWHWL
tWHAX
ADDRESSES (A)
VALID
tDVWH
DATA (D/Q)
HIGH-Z
tWHDX
DIN
28F016SAT-16
Figure 16. Page Buffer Write Timing Waveforms
Erase and Word/Byte Write Performance
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.(1)
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
tWHRH1
Word/Byte Write Time
tWHRH2
Block Write Time
0.6
2.1
s
Byte Write Mode
2
tWHRH3
Block Write Time
0.3
1.0
s
Word Write Mode
2
Block Erase Time
0.8
10
s
2
Full Chip Erase Time
25.6
s
2
9
µs
2
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.(1)
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
tWHRH1
Word/Byte Write Time
tWHRH2
Block Write Time
0.4
2.1
s
Byte Write Mode
2
tWHRH3
Block Write Time
0.2
1.0
s
Word Write Mode
2
Block Erase Time
0.6
10
s
2
Full Chip Erase Time
19.2
s
2
NOTES:
1. 25°C, VPP = 12.0 V Sampled.
2. Excludes System-Level Overhead.
34
6
µs
2
16M (1M × 16, 2M × 8) Flash Memory
LH28F016SA
56TSOP (TSOP056-P-1420)
56
1
14.20 [0.559]
13.80 [0.543]
0.50 [0.020] TYP.
0.28 [0.011]
0.12 [0.005]
29
28
0.13 [0.005]
0.49 [0.019]
0.39 [0.015]
20.30 [0.799]
19.70 [0.776]
0.22 [0.009]
0.02 [0.001]
18.60 [0.732]
18.20 [0.717]
1.10 [0.043]
0.90 [0.035]
1.19 [0.047] MAX.
0.18 [0.007]
0.08 [0.003]
PACKAGE BASE PLANE
19.30 [0.760]
18.70 [0.736]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
56TSOP
ORDERING INFORMATION
LH28F016SA
Device Type
T
-70
Package Speed
70 Access Time (ns)
56-pin, 1.2 mm x 14 mm x 20 mm TSOP (Type I) (TSOP056-P-1420)
16M (1M x 16, 2M x 8) Flash Memory
Example: LH28F016SAT-70 (16M (1M x 16, 2M x 8) Flash Memory, 70 ns, 56-pin TSOP)
28F016SAT-17
35
LH28F016SA
16M (1M × 16, 2M × 8) Flash Memory
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued June 1995
Reference Code SMT96112