LH532600 CMOS 2M (256K × 8/128K × 16) MROM FEATURES PIN CONNECTIONS • 262,144 words × 8 bit organization (Byte mode) 131,072 words × 16 bit organization (Word mode) • Access time: 100 ns (MAX.) • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply 40-PIN DIP 40-PIN SOP TOP VIEW OE1/OE1/DC 1 40 A8 A7 2 39 A9 A6 3 38 A10 A5 4 37 A11 A4 5 36 A12 A3 6 35 A13 A2 7 34 A14 A1 8 33 A15 A0 9 32 A16 CE 10 31 BYTE GND • Power consumption: Operating: 412.5 mW (MAX.) Standby: 550 µW (MAX.) GND 11 30 OE 12 29 D15/A-1 (LSB) D0 13 28 D7 D8 14 27 D14 • Mask-programmable control pin: Pin 1 = OE1/OE1/DC D1 15 26 D6 • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 48-pin, 10 × 20 mm2 TSOP (Type I) DESCRIPTION D9 16 25 D13 D2 17 24 D5 D10 18 23 D12 D3 19 22 D4 D11 20 21 VCC 532600-1 Figure 1. Pin Connections for DIP and SOP Packages The LH532600 is a 2M-bit mask-programmable ROM organized as 262,144 × 8 bits (Byte mode) or 131,072 × 16 bits (Word mode) that can be selected by BYTE input pin. It is fabricated using silicon-gate CMOS process technology. 1 LH532600 CMOS 2M MROM 48 PIN TSOP (Type I) TOP VIEW BYTE 1 48 A16 2 47 GND A15 3 46 D15/A-1 A14 4 45 D7 A13 5 44 D14 A12 6 43 D6 A11 7 42 D13 A10 8 41 D5 A9 9 40 D12 GND A8 10 39 D4 NC 11 38 VCC GND 12 37 VCC NC 13 36 GND NC 14 35 D11 OE1/OE1/DC 15 34 D3 A7 16 33 D10 A6 17 32 D2 A5 18 31 D9 A4 19 30 D1 A3 20 29 D8 A2 21 28 D0 A1 22 27 OE A0 23 26 GND CE 24 25 GND NOTE: Reverse bend available on request. 532600-2 Figure 2. Pin Connections for TSOP Package 2 CMOS 2M MROM LH532600 A16 32 A15 33 A14 34 29 D15 MEMORY MATRIX (262,144 x 8) (131,072 x 16) 3 A5 4 25 D13 A4 5 A3 6 A2 7 DATA SELECTOR/OUTPUT BUFFER 39 40 2 27 D14 ADDRESS DECODER A9 A8 A7 A6 ADDRESS BUFFER A13 35 A12 36 A11 37 A10 38 COLUMN SELECTOR A1 8 A0 9 23 D12 20 D11 18 D10 16 D9 14 D8 28 D7 26 D6 24 D5 22 D4 19 D3 17 D2 15 D1 CE 10 OE 12 OE1/OE1/ 1 DC BYTE 31 CE BUFFER TIMING GENERATOR 13 D0 SENSE AMPLIFIER OE BUFFER BYTE/WORD SWITCHOVER CIRCUIT ADDRESS BUFFER 29 A-1 21 VCC 11 30 GND NOTE: Pin numbers apply to the 40-pin DIP or SOP. 532600-3 Figure 3. LH532600 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME A–1 – A16 Address input 1 OE Output enable input D0 – D15 Data output 1 OE 1/OE 1/DC Output enable input BYTE Byte/word mode switch 1 VCC Power supply (+5 V) CE Chip enable input GND Ground NOTE 2, 3 NOTES: 1. The D15/A–1 pin becomes LSB address input (A–1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. 2. Active levels of OE1/OE1/DC are mask-programmable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level. Then it is recommended to apply either VIH or VIL to the DC pin. 3. DC = Don’t care. 3 LH532600 CMOS 2M MROM TRUTH TABLE CE OE OE1/OE1 DATA OUTPUT A–1 (D15) BYTE ADDRESS INPUT D0 – D7 D8 – D15 LSB MSB SUPPLY CURRENT H X X X X High-Z High-Z – – Standby L H X X X High-Z High-Z – – Operating L X L/H X X High-Z High-Z – – Operating L L H/L H – D0 – D7 D8 – D15 A0 A16 Operating L L H/L L L D0 – D7 High-Z A–1 A16 Operating L L H/L L H D8 – D15 High-Z A–1 A16 Operating NOTE: X = H or L, High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT VCC – 0.3 to +7.0 V Supply voltage Input voltage VIN – 0.3 to V CC + 0.3 V Output voltage VOUT – 0.3 to V CC + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg –65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MAX. UNIT NOTE Input ‘High’ voltage VIH 2.2 VCC + 0.3 V Input ‘Low’ voltage VIL – 0.3 0.8 V Output ‘High’ voltage VOH IOH = – 400 µA Output ‘Low’ voltage VOL IOL = 2.0 mA 0.4 V Input leakage current | ILl | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 tRC = 100 ns 75 mA 2 ICC2 tRC = 1 µs 65 mA 2 ICC3 tRC = 100 ns 70 mA 3 ICC4 tRC = 1 µs 60 mA 3 ISB1 CE = V IH 3 mA ISB2 CE = V CC – 0.2 V 100 µA f = 1 MHz TA = 25°C 10 pF 10 pF Operating current Standby current Input capacitance Output capacitance CIN COUT NOTES: 1. CE/OE/OE1 = VIH, OE1 = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open 4 MIN. 2.4 V CMOS 2M MROM LH532600 AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT Read cycle time tRC 100 Address access time tAA 100 ns Chip enable access time tACE 100 ns Output enable delay time tOE 55 ns Output hold time tOH CE to output in High-Z tCHZ OE to output in High-Z tOHZ NOTE ns 5 ns 55 ns 1 NOTE: 1. This is the time required for the outputs to become high-impedance. AC TEST CONDITIONS PARAMETER Input voltage amplitude RATING 0.4 to 2.6 V Input rise/fall time 10 ns Input/output reference level 1.5 V Output load condition 1 TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. 5 LH532600 CMOS 2M MROM tRC A-1 - A16 tAA (NOTE) CE tACE tCHZ (NOTE) OE/OE1/ OE1 tOHZ tOE (NOTE) D0 - D7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. 532600-4 Figure 4. Byte Mode (BYTE = VIL) tRC A0 - A16 tAA (NOTE) CE tACE tCHZ (NOTE) OE/OE1/ OE1 tOHZ tOE (NOTE) D0 - D15 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. Figure 5. Word Mode (BYTE = V IH) 6 532600-5 CMOS 2M MROM LH532600 PACKAGE DIAGRAMS 40DIP (DIP040-P-0600) 40 21 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 20 0.30 [0.012] 0.20 [0.008] 52.30 [2.059] 51.70 [2.035] 15.24 [0.600] TYP. 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40DIP 40-pin, 600-mil DIP 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 40 21 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 26.50 [1.043] 26.10 [1.028] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40SOP 40-pin, 525-mil SOP 7 LH532600 CMOS 2M MROM 48TSOP (TSOP048-P-1218) 0.50 [0.020] TYP. 0.30 [0.012] 0.10 [0.004] 25 48 16.60 [0.654] 16.20 [0.638] 1 18.40 [0.724] 17.60 [0.693] 17.00 [0.669] 24 12.20 [0.480] 11.80 [0.465] 0.15 [0.006] 0.425 [0.017] 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] DIMENSIONS IN MM [INCHES] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 48TSOP 48-pin, 10 × 20 mm2 TSOP (Type I) ORDERING INFORMATION LH532600 Device Type X Package D N T TR 40-pin, 600-mil DIP (DIP040-P-0600) 40-pin, 525-mil SOP (SOP040-P-0525) 48-pin, 10 x 20 mm2 TSOP (Type I) (TSOP048-P-1020) 48-pin, 10 x 20 mm2 TSOP (Type I) Reverse bend (TSOP048-P-1020) CMOS 2M (256K x 8 or 128K x 16) Mask-Programmable ROM Example: LH532600D (CMOS 2M (256K x 8 or 128K x 16 ) Mask-Programmable ROM, 40-pin, 600-mil DIP) 532600-6 8