LH5P1632 CMOS 512K (32K × 16) Pseudo-Static RAM FEATURES • 32,768 × 16 bit organization • Access time: 80/150 ns (MAX.) • Cycle time: 140/210 ns (MIN.) • Single +5 V power supply PIN CONNECTIONS 40-PIN DIP 40-PIN SOP TOP VIEW GND 1 40 VCC A9 2 39 UWR LWR A8 3 38 A7 4 37 A10 A6 5 36 A11 A5 6 35 A12 A4 7 34 A13 • TTL compatible I/O A3 8 33 A14 A2 9 32 UOE/TEST1 • 256 refresh cycles/4 ms (MAX.) A1 10 31 LOE/RFSH • Power consumption (MAX.): Operating: 467.5/327.5 mW Standby: 16.5 mW • Available for auto-refresh mode • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP DESCRIPTION The LH5P1632 is a 512K-bit Pseudo-Static RAM organized as 32,768 × 16 bits. It is fabricated using silicon-gate CMOS process technology. A0 11 30 CE I/O1 12 29 I/O16 I/O2 13 28 I/O15 I/O3 14 27 I/O14 I/O4 15 26 I/O13 I/O5 16 25 I/O12 I/O6 17 24 I/O11 I/O7 18 23 I/O10 I/O8 19 22 I/O9 GND 20 21 VCC 5P1632-1 Figure 1. Pin Connections for DIP and SOP Packages 1 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 21 VCC 20 GND A0 11 A1 10 A2 9 A3 8 A4 7 A5 6 A6 5 A7 4 A8 3 A9 2 VBB GENERATOR 1 GND A8 - A14 COLUMN ADDRESS BUFFER A0 - A7 A10 37 A11 36 A12 35 A13 34 A14 40 VCC I/O SELECTOR SENSE AMPS ROW ADDRESS BUFFER REFRESH ADDRESS COUNTER 33 COLUMN DECODER EXT/INT ADDRESS MUX ROW DECODER MEMORY ARRAY DATA IN BUFFER DATA OUT BUFFER I/O2 I/O3 I/O4 I/O5 17 I/O6 18 I/O7 19 I/O8 DATA IN BUFFER CE 30 12 I/O1 13 14 15 16 CLOCK GENERATOR DATA OUT BUFFER REFRESH CONTROLLER 22 I/O9 I/O10 I/O11 23 24 25 26 I/O12 I/O13 27 I/O14 28 I/O15 29 I/O16 LOE/ 31 RFSH UOE/ TEST1 32 LWR 38 LWR 39 5P1632-2 Figure 2. LH5P1632 Block Diagram PIN DESCRIPTION SIGNAL A0 – A14 LWR, UWR LOE/RFSH, UOE CE 2 PIN NAME Address input Write enable Output enable/Refresh input Chip enable input SIGNAL I/O1 – I/O16 VCC GND PIN NAME Data input/output Power Supply Ground CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE 1 Applied voltage on all pins VT –1.0 to +7.0 V Output short circuit current IO 50 mA Power dissipation PD 600 mW Operating temperature Topr 0 to +70 °C Storage temperature Tstg –65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V GND 0 0 0 V Supply voltage Input voltage VIH 2.4 VCC + 0.3 V VIL –0.3 0.8 V NOTE 1 NOTE: 1. VIL (MIN.) = –1.0 V when the pulse width is less than 20 ns. CAPACITANCE (TA = 0 to +70°C, f = 1 MHz, VCC = 5.0 V ±10%) PARAMETER Input capacitance CONDITIONS SYMBOL MAX. UNIT A0 – A14 CIN1 8 pF LWR, UWR CIN2 5 pF CE CIN3 5 pF CIN4 5 pF COUT1 10 pF LOE/RFSH, UOE Input/Output capacitance MIN. I/O1 – I/O16 DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL Average supply current in normal operation tRC = t RC (MIN) ICC1 Supply current in standby mode ICC2 Average supply current in CPU internal cycle (LWR = UWR = LOE/RFSH = UOE = V IH) CONDITIONS MIN. LH5P1632-80 85 LH5P1632-15 65 3.0 LH5P1632-80 ICC3 MAX. UNIT NOTE mA 1, 2 mA 1, 3 mA 1, 2 85 LH5P1632-15 Input leakage current ILI 0 V ≤ VIN ≤ 6.5 V, 0 V except on test pins –10 10 µA I/O leakage current ILO 0 V ≤ VOUT ≤ VCC + 0.3 V, Outputs in high-impedance state –10 10 µA Output HIGH voltage VOH IOUT = –1.0 mA 2.4 Output LOW voltage V OL IOUT = 4.0 mA V 0.4 V NOTES: 1. Specified values are with outputs open. 2. I CC1 and ICC3 depend on the cycle time. 3. CE = High, LOE/RFSH = High. 3 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 AC CHARACTERISTICS 1, 2, 3 (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER –80 ns SYMBOL MIN. –150 ns MAX. MIN. UNIT NOTE MAX. READ OR WRITE CYCLE tRC tRMW 140 205 CE pulse width tCE 80 CE precharge time tP 50 60 ns Address setup time Address hold time tAS tAH 0 20 0 30 ns ns Read command setup time tRCS 0 0 ns 0 Random read, write cycle time Read modify write cycle time 10,000 150 ns ns 10,000 0 ns tRCH tCEA tOEA CE to output in Low-Z tCLZ 10 10 ns OE to output in Low-Z tOLZ 0 0 ns OE setup time for WR Output disable time from CE tOSW 0 0 ns Output disable time from OE tCHZ tOHZ 0 0 25 25 25 80 30 150 70 ns ns 0 0 35 35 ns ns 0 35 ns Output disable time from WR tWHZ 0 OE setup time OE hold time tOES tOEH 10 0 10 0 ns ns OE lead time tOEL 10 10 ns Write command pulse width tWCP 60 85 ns Write command setup time Write command hold time tWCS 60 85 ns Data setup time from WR tWCH tDSW 60 30 85 50 ns ns Data setup time from CE tDSC 30 50 ns Data hold time from WR Data hold time from CE tDHW 0 0 ns Transition time (rise and fall) tDHC tT 0 3 0 3 35 ns ns Refresh time interval tREF 4 ms Auto refresh cycle time tFC REFRESH CYCLE 140 190 Refresh delay time from CE tRFD 50 60 Refresh pulse width (Auto Refresh) Refresh precharge time (Auto Refresh) tFAP 30 tFP 40 30 ns tFCE 160 225 ns 35 4 NOTES: 1. In order to initialize the circuit, CE and OEL/RFSH should be kept VIH for 200 µs after power on and followed by at least 8 dummy cycles. 2. AC characteristics shall be tested with t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Address is latched at the negative edge of CE. 5. Measured with a load equivalent to 2TTL + 100 pF. 6. Data for the lower byte (I/O1 to I/O 8) is latched at the positive edge of LWR or the positive edge of CE. Data for the upper byte (I/O9 to I/O 16) is latched at the positive edge of UWR or the positive edge of CE. 8,000 INPUT OUTPUT 80 4 4 ns Read command hold time CE access time OE access time CE delay time from Refresh active (Auto Refresh) 4 210 280 5 5 ns ns 8,000 ns 2.6 V 2.4 V 0.8 V 0.6 V 2.2 V 0.8 V 5P1632-9 Figure 3. AC Characteristics CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 TRUTH TABLE INPUT OUTPUT MODE UPPER BYTE NOTE CE UOE LOE/RFSH UWR LWR I/O9 – I/O 16 I/O 1 – I/O8 LOWER BYTE H D D D D High-Z High-Z L L L H H DOUT DOUT Read L H L H H High-Z DOUT CE only refresh Read L L H H H DOUT High-Z Read CE only refresh L H H H H High-Z High-Z CE only refresh CE only refresh L D D L L DIN DIN Write Write Standby Read L D H L H DIN High-Z Write CE only refresh L H D H L High-Z DIN CE only refresh Write L D L L H DIN DOUT Write Read Inhibit L L D H L DOUT DIN Read Write Inhibit H D D D High-Z High-Z Auto Refresh NOTES: D = Don’t care. High-Z = High impedance. tRC tP CE tP VIH VIL tAS A0 - A14 tCE VIH VIL tAH ADDRESS INPUT tOEH tOEL tOES LOE/RFSH VIH VIL UOE tRCS tRCH LWR VIH UWR VIL tCEA tCHZ tOEA V I/O1 - I/O16 VOH OL tOHZ VALID-DATA OUTPUT tOLZ tCLZ 5P1632-3 Figure 4. Read Cycle 5 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 tRC tP tCE tP VIH CE VIL tAS VIH A0 - A14 VIL tAH ADDRESS INPUT tOES tOEH V LOE/RFSH IH VIL UOE tWCH tWCS tWCP LWR VIH UWR VIL tDSW tDHW tDSC I/O1 - I/O16 VIH VIL tDHC VALID-DATA INPUT 5P1632-4 Figure 5. Write Cycle 6 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 tRMW tP CE tP VIH VIL tAS V A0 - A14 VIH IL tAH ADDRESS INPUT tOEH LOE/RFSH VIH VIL UOE tRCS tOSW tWCS tWCP LWR VIH UWR VIL tDSW tDHW tDSC VIH VIL tDHC VALID-DATA INPUT tCEA I/O1 - I/O16 tOEA VOH VOL tWHZ tOHZ VALID-DATA OUTPUT tOLZ tCLZ 5P1632-5 Figure 6. Read-Write Cycle 7 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 tRC tP CE tCE tP VIH VIL tAS tAH V A0 - A7 VIH IL ADDRESS INPUT tOEH tOES LOE/RFSH VIH VIL UOE tRCS LWR UWR tRCH VIH VIL I/O1 - I/O16 VOH VOL HIGH - Z NOTE: A8 - A14 = Don't Care 5P1632-6 Figure 7. CE Only Refresh Cycle V CE VIH IL tRFD tFC tFAP tFCE tFP tFAP V LOE/RFSH VIH IL I/O1 - I/O16 VOH VOL HIGH - Z NOTE: A0 - A14, LWR, UWR, UOE = Don't Care 5P1632-7 Figure 8. Auto Refresh Cycle 8 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 PACKAGE DIAGRAMS 40DIP (DIP040-P-0600) 40 21 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 20 0.30 [0.012] 0.20 [0.008] 52.30 [2.059] 51.70 [2.035] 15.24 [0.600] TYP. 4.55 [0.179] 3.95 [0.156] 5.40 [0.213] 4.80 [0.189] 3.55 [0.140] 2.95 [0.116] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40DIP 40-pin, 600-mil DIP 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 40 21 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 20 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 26.50 [1.043] 26.10 [1.028] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 40SOP 40-pin, 525-mil SOP 9 CMOS 512K (32K × 16) Pseudo-Static RAM LH5P1632 ORDERING INFORMATION LH5P1632 Device Type X Package - ## Speed 15 150 Access Time (ns) 80 80 D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) CMOS 512K (32K x 16) Pseudo-Static RAM Example: LH5P1632N-80 (CMOS 512K (32K x 16) Pseudo-Static RAM, 80 ns, 40-pin, 525-mil SOP) 5P1632-8 10