CMOS 1M (128K × 8) CS-Control Pseudo-Static RAM LH5P8129 FEATURES • 131,072 × 8 bit organization PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Access times (MAX.): 60/80/100 ns RFSH 1 32 • Cycle times (MIN.): 100/130/160 ns VCC A16 2 31 A15 • Single +5 V power supply A14 3 30 CS A12 4 29 R/W A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 • Pin compatible with 1M standard SRAM • Power consumption: Operating: 572/385/275 mW (MAX.) Standby (TTL level): 5.5 mW (MAX.) Standby (CMOS level): 1.1 mW (MAX.) • TTL compatible I/O • Available for auto-refresh and self-refresh modes • 512 refresh cycles/8 ms • Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 × 20 mm2 TSOP (Type I) DESCRIPTION The LH5P8129 is a 1M bit Pseudo-Static RAM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo static operation which eliminates external clock inputs, while considering the pinout compatibility with industry standard SRAMs. The advantage is the cost savings realized with the lower cost PSRAM. The LH5P8129 PSRAM has a built-in oscillator, which makes it easy to refresh memories without external clocks. 5P8129-1 Figure 1. Pin Connections for DIP and SOP Packages 32-PIN TSOP (Type I) TOP VIEW A11 1 32 OE A9 2 31 A10 A8 3 30 CE A13 4 29 I/O7 R/W 5 28 I/O6 I/O5 CS 6 27 A15 7 26 I/O4 VCC 8 25 I/O3 RFSH 9 24 GND A16 10 23 I/O2 A14 11 22 I/O1 A12 12 21 I/O0 A7 13 20 A0 A6 14 19 A1 A5 15 18 A2 A4 16 17 A3 NOTE: Reverse bend available on request. 5P8129-2 Figure 2. Pin Connections for TSOP Package 1 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 VBB GENERATOR COLUMN ADDRESS BUFFER COLUMN DECODER 6 5 27 26 A10 23 A11 25 A12 4 A13 28 A14 3 A15 31 SENSE AMPS ROW ADDRESS BUFFER REFRESH ADDRESS COUNTER EXT/INT ADDRESS MUX ROW DECODER I/O SELECTOR 13 I/O0 14 I/O1 15 I/O2 17 I/O3 18 I/O4 MEMORY ARRAY 19 I/O5 20 I/O6 DATA OUT BUFFER A16 2 CE 22 CS 30 DATA IN BUFFER 21 I/O7 CLOCK GENERATOR REFRESH CONTROLLER REFRESH TIMER RFSH 1 OE 24 R/W 29 NOTE: Pin numbers apply to 32-pin DIP or SOP. 5P8129-3 Figure 3. LH5P8129 Block Diagram PIN DESCRIPTION SIGNAL A0 - A16 2 PIN NAME Address input R/W Read/Write input OE Output Enable input CE Chip Enable input SIGNAL CS RFSH I/O0 - I/O7 PIN NAME Chip Select input Refresh input Data input/output CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 TRUTH TABLE CE CS OE R/W RFSH A0 - A16 I/O1 - I/O8 MODE L H L H X VX DOUT Read L H X L X VX DIN Write L H H H X VY High-Z CE only refresh L L X X X X High-Z CS standby H X X X L X High-Z Auto/Self refresh H X X X H X High-Z Standby NOTES: H = High at VIN = VCC + 0.3 V to VIH (MIN.) L = Low at VIN = VIL (MAX.) to -1.0 V X = Don’t care at VCC + 0.3 V to -1.0 V VX = A0-A16 address input when CE = L, then Don’t Care VY = A0-A8 address input when CE = L, then Don’t Care, and A9-A16 address = Don’t Care at VCC + 0.3 V to -1.0 V ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE VT -1.0 to +7.0 V 1 Applied voltage on any pins Output short circuit current IO 50 mA Power dissipation PD 600 mW Operating temperature Topr 0 to +70 °C Storage temperature Tstg -65 to +150 °C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER Supply voltage Input voltage SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V GND 0 0 0 V VIH 2.4 VCC + 0.3 V VIL -1.0 0.8 V CAPACITANCE (TA = 0 to +70°C, f = 1 MHz, VCC = 5.0 V ±10%) PARAMETER Input capacitance Input/output capacitance CONDITIONS SYMBOL MIN. MAX. UNIT A0 - A16 CIN1 8 pF R/W, OE CIN2 5 pF CE, CS CIN3 5 pF RFSH CIN4 5 pF I/O1 - I/O7 COUT1 10 pF 3 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL CONDITIONS ICC1 tRC = tRC (MIN.) MIN. LH5P8129-60 Operating current LH5P8129-80 LH5P8129-10 Standby current Self-refresh average current TTL Input CMOS Input TTL Input CMOS Input 4 UNIT NOTE 104 70 mA 1, 2 50 1 ICC2 0.2 1 ICC3 0.2 Input leakage current ILI 0 V ≤ VIN ≤ 6.5 V 0 V except on test pins I/O leakage current ILO 0 V ≤ VOUT ≤ VCC + 0.3 V Output in high-impedance state -10 Output HIGH voltage VOH IOUT = -1 mA 2.4 Output LOW voltage VOL IOUT = 4 mA NOTES: 1. Specified values are with outputs open. 2. I CC1 depends on the cycle time 3. CE = VIH, RFSH = VIH 4. CE = VCC - 0.2 V, RFSH = VCC - 0.2 V 5. CE = VIH, RFSH = VIL 6. CE = VCC - 0.2 V, RFSH = 0.2 V MAX. mA mA -10 10 µA 10 µA V 0.4 V 1, 3 1, 4 1, 5 1, 6 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 AC ELECTRICAL CHARACTERISTICS 1,2,3 (TA = 0 to +70°C, VCC = 5.0 V ±10%) PARAMETER SYMBOL Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time CS setup time CS hold time Address setup time Address hold time Read command setup time Read command hold time CE access time OE access time CE to output in Low-Z OE to output in Low-Z Output enable from end of write Chip disable to output in High-Z Output disable to output in High-Z Write enable to output in High-Z OE setup time OE hold time Write command pulse width Write command setup time Write command hold time Data setup time from write Data setup time from CE Data hold time from write Data hold time from CE Transition time (rise and fall) Refresh time interval Refresh command hold time Auto refresh cycle time Refresh delay time from CE Refresh pulse width (Auto refresh) Refresh precharge time (Auto refresh) Refresh pulse width (Self refresh) CE delay time from refresh precharge (Self refresh) tRC tRMW tCE tP tCSS tCSH tAS tAH tRCS tRCH tCEA tOEA tCLZ tOLZ tWLZ tCHZ tOHZ tWHZ tOES tOEH tWP tWCS tWCH tDSW tDSC tDHW tDHC tT tREF tRHC tFC tRFD LH5P8129-60 MIN. 100 165 60 40 0 15 0 15 0 0 MAX. 10,000 LH5P8129-80 MIN. 130 195 80 40 0 20 0 20 0 0 60 25 20 0 0 10,000 20 0 0 35 8 15 100 30 LH5P8129-10 MIN. 160 235 100 50 0 25 0 25 0 0 80 30 20 20 20 0 10 30 30 40 25 25 0 0 3 MAX. 10,000 100 35 20 0 0 25 25 25 0 10 30 30 50 30 30 0 0 3 MAX. 35 8 15 130 40 30 30 30 0 10 30 30 60 35 35 0 0 3 35 8 15 160 50 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns tFAP 30 tFP 30 30 30 ns tFAS 8,000 8,000 8,000 ns tFRS 140 160 190 ns NOTES: 1. In order to initialize the circuit, an initial pause of 100 µs with CE = VIH, RFSH = VIH after power-up, followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Measured with a load equivalent to 2TTL + 100 pF. 5. Address is latched at the negative edge of CE. 6. Data is latched at the positive edge of R/W or at the positive edge of CE. 8,000 30 INPUT OUTPUT 8,000 30 8,000 NOTE 4 4 5 5 6 6 6 6 ns 2.6 V 2.4 V 0.8 V 0.6 V 2.2 V 0.8 V 5P8129-4 Figure 4. AC Characteristics 5 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 tRC tP CE CS tCE VIH VIL tCSS tCSH tAS tAH VIH VIL A0 - A16 VIH VIL OE VIH VIL ADDRESS INPUT tRCH tRCS R/W VIH VIL tOEA tCEA tOHZ tOLZ tCLZ I/O0 - I/O7 VOH VOL tCHZ VALID-DATA OUTPUT tFP tFRS RFSH tRHC tRFD VIH VIL 5P8129-5 Figure 5. Read Cycle 6 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 tRC tCE tP CE CS A0 - A16 VIH VIL tCSS tCSH tAS tAH VIH VIL VIH VIL ADDRESS INPUT tOES OE tOEH VIH VIL tWCS tWCH tWP R/W VIH VIL tDSW tDHW tDSC I/O0 - I/O7 VOH VOL tDHC DATA INPUT tFP tFRS RFSH tRHC tRFD VIH VIL 5P8129-6 Figure 6. Write Cycle 1 (OE = HIGH) 7 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 tRC tCE tP CE CS VIH VIL tCSS tCSH tAS tAH VIH VIL A0 - A16 VIH VIL OE VIH VIL ADDRESS INPUT tWCS tWCH tWP R/W VIH VIL tDSW tDHW tDSC DIN VIH VIL tDHC VALID-DATA INPUT tWHZ I/O0 - I/O7 tCLZ tOHZ tOLZ tWLZ tCHZ V DOUT VOH OL tFP tFRS RFSH tRHC tRFD VIH VIL 5P8129-7 Figure 7. Write Cycle 2 (OE Clock) 8 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 tRC tCE tP CE CS VIH VIL tCSS tCSH tAS tAH VIH VIL A0 - A16 VIH VIL OE VIH VIL ADDRESS INPUT tWCS tWCH tWP R/W VIH VIL tDSW tDHW tDSC DIN VIH VIL VALID-DATA INPUT tWHZ I/O0 - I/O7 tCLZ DOUT tDHC tCHZ tWLZ VOH VOL tFP tFRS RFSH tRHC tRFD VIH VIL 5P8129-8 Figure 8. Write Cycle 3 (OE = LOW) 9 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 tRMW tP CE CS VIH VIL tCSS tCSH tAS tAH VIH VIL A0 - A16 VIH VIL OE VIH VIL ADDRESS INPUT tWCS tRCS tWP R/W VIH VIL tOEA tDSW tDSC tCEA DIN VIH VIL tDHC DATA INPUT tOLZ I/O0 - I/O7 tCLZ DOUT tDHW VOH VOL tWHZ tOHZ tCHZ tWLZ DATA OUTPUT tFP tFRS RFSH tRHC tRFD VIH VIL 5P8129-9 Figure 9. Read-Modify-Write Cycle 10 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 tRC tCE tP VIH VIL CE tCSS tCSH tAS tAH VIH VIL CS VIH VIL A0 - A8 ADDRESS INPUT tOES tOEH tRCS tRCH VIH VIL OE R/W VIH VIL I/O0 - I/O7 VOH VOL HIGH-Z tFP tFRS RFSH tRFD tRHC VIH VIL NOTE: A9 - A16 = Don't Care 5P8129-10 Figure 10. CE Only Refresh CE VIH VIL tRFD tFP RFSH VIH VIL I/O0 - I/O7 VOH VOL tFC tFAP tFC tFP tFAP tRHC tFP HIGH-Z NOTE: CS, OE, R/W, A0 -A16 = Don't Care 5P8129-11 Figure 11. Auto Refresh Cycle 11 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 VIH VIL CE tRFD tRHC tFAS tFP RFSH VIH VIL I/O0 - I/O7 VOH VOL tFRS HIGH-Z NOTE: CS, OE, R/W, A0 - A16 = Don't Care 5P8129-12 Figure 12. Self Refresh Cycle tRC tP CE VIH VIL tCSS CS tCE tCSH VIH VIL NOTE: OE, R/W, RFSH, A0 - A16 = Don't Care 5P8129-13 Figure 13. CS Standby Mode 12 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 16 0.30 [0.012] 0.20 [0.008] 41.30 [1.626] 40.70 [1.602] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012] 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 1 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 20.80 [0.819] 20.40 [0.803] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32SOP 32-pin, 525-mil SOP 13 CMOS 1M (128K × 8) Pseudo-Static RAM LH5P8129 32TSOP (Type I) (TSOP032-P-0820) 0.30 [0.012] 0.10 [0.004] 0.50 [0.020] TYP. 32 17 18.60 [0.732] 18.20 [0.717] 1 20.30 [0.799] 19.70 [0.776] 19.00 [0.748] 16 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP 32-pin, 8 × 20 mm2 TSOP (Type I) ORDERING INFORMATION LH5P8129 Device Type X Package - ## Speed 60 60 80 80 Access Time (ns) 10 100 Blank 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820) TR 32-pin, 8 x 20 mm2 TSOP (Type I) Reverse bend (TSOP032-P-0820) CMOS 1M (128K x 8) Pseudo-Static RAM Example: LH5P8129N-60 (CMOS 1M (128K x 8) Pseudo-Static RAM, 60 ns, 32-pin, 525-mil SOP) 5P8129-14 14