LH6V4256 CMOS 1M (256K × 4) Dynamic RAM FUNCTION DESCRIPTION • 262,144 words × 4 bit The LH6V4256 is a 262,144 word × 4-bit dynamic RAM which allows fast page mode access. The LH6V4256 is fabricated on SHARP’s advanced CMOS double-level polysilicon gate technology. With its input multiplexed and packaged in the standard 20-pin DIP, 26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to realize memory systems with low power dissipation and large memory capacity. The LH6V4256 operates on a single +3.3 V power supply and the built-in biasing voltage generator circuit. • Access time: 100 ns (MAX) • Cycle time: 190 ns (MIN) • Fast page mode cycle time: 60 ns (MIN) • Power supply: +3.3 V ±0.3 V • Power consumption (MAX): Operating: 126 mW Standby: 0.54 mW • Built-in latch circuit for row-address, column-address, and input data • OE = Don’t care in early write operation • RAS only refresh, hidden refresh, and CAS before RAS refresh capability • On-chip refresh counter • 512 refresh cycle/8 ms • Packages: 20-pin, 300-mil DIP 26-pin, 300-mil SOJ 28-pin, 8 × 13 mm2 TSOP (Type I) 2-14 PIN CONNECTIONS 20-PIN DIP TOP VIEW 1 20 VSS I/O2 2 19 I/O 4 WE 3 18 I/O3 RAS 4 17 CAS NC 5 16 OE A0 6 15 A8 A1 7 14 A7 A2 8 13 A6 A3 9 12 A5 VCC 10 11 A4 I/O1 6V4256-1 Figure 1. Pin Connections for DIP Package CMOS 1M (256K × 4) Dynamic RAM 26-PIN SOJ LH6V4256 TOP VIEW 28-PIN TSOP (Type I) TOP VIEW I/O1 1 26 VSS NC 1 28 NC I/O2 2 25 I/O4 OE 2 27 A8 WE 3 24 I/O3 CAS 3 26 A7 RAS 4 23 CAS I/O3 4 25 A6 NC 5 22 OE I/O4 5 24 A5 VSS 6 23 A4 NC 7 22 NC NC 8 21 NC A0 9 18 A8 NC 9 20 VCC A1 10 17 A7 I/O1 10 19 A3 A2 11 16 A6 I/O2 11 18 A2 A3 12 15 A5 WE 12 17 A1 VCC 13 14 A4 RAS 13 16 A0 NC 14 15 NC 6V4256-2 6V4256-3 Figure 2. Pin Connections for SOJ Package Figure 3. Pin Connections for TSOP Package 2-15 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 I/O1 1 OE 16 I/O2 2 I/O3 18 OE CLOCK GENERATOR VBB GENERATOR DATA OUT BUFFER DATA IN BUFFER WE 3 I/O4 19 R/W CLOCK GENERATOR 10 VCC RAS 4 RAS CLOCK GENERATOR 20 VSS MEMORY ARRAY 1,048,576 BITS ROW ADDRESS COUNTER COLUMN DECODER CAS CLOCK GENERATOR SENSE AMP. I/O GATE CAS 17 REFRESH CONTROL ROW DECODER ADDRESS BUFFER 6 A0 7 A1 8 A2 9 A3 11 A4 12 A5 13 A6 14 A7 15 A8 NOTE: Pin numbers apply to the 20-pin DIP. 6V4256-4 Figure 4. LH6V4256 Block Diagram PIN DESCRIPTION PIN NAME A0 – A8 2-16 FUNCTION Address input PIN NAME I/O1 – I/O4 FUNCTION Data input/output RAS Row address strobe VCC CAS Column address strobe VSS Power supply (0 V) WE Write enable NC No connection OE Output enable Power supply (+3.3 V) CMOS 1M (256K × 4) Dynamic RAM LH6V4256 I/O1 10 OE 2 I/O2 11 I/O3 4 OE CLOCK GENERATOR DATA OUT BUFFER DATA IN BUFFER WE 12 I/O4 5 VBB GENERATOR R/W CLOCK GENERATOR 20 VCC RAS 13 RAS CLOCK GENERATOR 6 VSS MEMORY ARRAY 1,048,576 BITS ROW ADDRESS COUNTER COLUMN DECODER CAS CLOCK GENERATOR SENSE AMP. I/O GATE CAS 3 REFRESH CONTROL ROW DECODER ADDRESS BUFFER 16 A0 17 A1 18 A2 19 A3 23 A4 24 A5 25 A6 26 A7 27 A8 NOTE: Pin numbers apply to the 28-pin TSOP (Type I). 6V4256-5 Figure 5. LH6V4256 Block Diagram 2-17 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT NOTE Applied voltage on all pins – 0.5 to +5.5 V 1 Output short circuit current 50 mA Power dissipation 1.0 W 0 to +70 °C – 65 to +150 °C Operating temperature Storage temperature NOTE: 1. The maximum applicable voltage on any pin with respect to VSS. RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 3.0 3.3 3.6 V VSS 0 0 0 V VIH 2. 3 VCC + 0.3 V VIL – 0.3 0.6 V Supply voltage Input voltage CAPACITANCE (TA = 0 to +70°C, f = 1 MHz, VCC = 3.3 V ±0.3 V) PARAMETER Input capacitance Input/output capacitance CONDITIONS SYMBOL MIN. MAX. UNIT A0 – A8 CIN1 6 pF RAS, OE, CAS, WE CIN2 7 pF COUT1 7 pF I/O 1 – I/O 4 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT NOTE Average supply current in normal operation ICC1 35 mA 1, 2, 3 Supply current in standby mode ICC2 0.15 mA 1 Average supply current in fast page mode ICC3 30 mA 1, 2 Average supply current in CAS before RAS refresh cycle ICC4 35 mA 1, 2, 3 Average supply current in RAS only refresh cycle ICC5 35 mA 1, 2, 3 RAS = CAS ≥ V CC – 0.2 V Input leakage current 0 V ≤ VIN ≤ 4.8 V 0 V except on test pins ILI –10 10 µA Output leakage current 0 V ≤ VOUT ≤ 4.8 V Output in high-impedance state ILO –10 10 µA Output ‘High’ Voltage IOUT = – 2 0 0 µA VOH 2.15 Output ‘Low’ Voltage IOUT = 1 mA VOL V 0.4 NOTES: 1. Specified values are with outputs open. 2. ICC1, ICC3, ICC4, and ICC5 depend on cycle time. 3. Cycle time is 190 ns. Address transition is once at RAS = VIH and once at RAS = VIL. 2-18 V CMOS 1M (256K × 4) Dynamic RAM LH6V4256 AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4 (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V) READ CYCLE PARAMETER SYMBOL MIN. MAX. UNIT Random read or write cycle time tRC 190 Access time from RAS Access time from column address Access time from CAS Access time from OE tOEA Row address setup time Row address hold time tASR 0 tRAH 15 ns Column address setup time tASC 0 ns Column address hold time (RAS) Column address delay time (RAS) tCAH tRAD 20 20 Column address lead time (RAS) tRAL 50 RAS pulse width tRAS 100 RAS precharge time tRP 80 ns CAS precharge time (RAS ↓) tCRP 0 ns CAS delay time (RAS) tRCD 25 CAS lead time (RAS) tRSL 30 tRAC 100 ns 5 tAA 50 ns 5 tCAC 40 ns 5 ns 5 ns 35 CAS pulse width tCAS 40 CAS hold time tCSH 100 OE lead time (RAS) tROL 0 Output data disable time (CAS) tOFF NOTE ns 50 ns ns 6 ns 10,000 60 ns ns 7 ns 10,000 ns ns ns 30 Output data disable time (OE) tOEZ Output data hold time (CAS) tSOH 0 ns Output data hold time (OE) tOOH 0 ns Read command setup time (CAS) tRCS 0 ns Read command hold time (CAS) tRCH 10 ns 8 Read command hold time (RAS ↑) tRRHP 10 ns 8 Read command hold time (RAS ↓) tRRHN 115 ns 8 tT 3 Transition time (rise and fall) Refresh time interval 30 ns tREF NOTES: 1. For proper memory function, at least 200 µs of pause time should be kept after power on, followed by several dummy cycles. When RAS = VIH is continued for more than 8 ms, the same dummy cycles should be given. Usually eight ordinary refresh cycles should be given. 2. The required VCC current (I CC) during power on depends on the input levels of RAS. If RAS = VIL during power on, the device goes into an active cycle, and ICC exhibits large current transients. It is recommended that RAS tracks with VCC or be held at a valid VIH during power on. 3. AC characteristics assume tT = 5 ns. 4. AC characteristics assume the following condition (see figure at right). 5. Load condition for 1TTL + 30 pF. 6. t RAD (MAX) is the maximum point for tRAD where t RAC (MAX) is ensured, and does not represent a limit of operation. If tRAD ≥ tRAD (MAX), the access time comes under the control of tAA. 7. t RCD (MAX) is the maximum point for tRCD, where tRAC (MAX) is ensured and does not represent a limit of operation. If tRCD ≥ tRCD (MAX), the access time comes under the control of tCAC. 8. The operation is ensured when either tRRHN, tRRHP, or tRCH is satisfied. ns 35 ns 8 ms INPUT LEVEL OUTPUT JUDGMENT LEVEL 2.3 V 0.6 V 2.15 V 0.4 V 6V4256-6 2-19 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 FAST PAGE MODE CYCLE PARAMETER SYMBOL MIN. Fast page mode cycle time tPC 60 ns CAS precharge time tCP 10 ns CAS precharge access time tCACP Read-write cycle time (page mode) tPRWC MAX. 55 125 UNIT NOTE ns ns 1 NOTE: 1. t RWC, tRWD, t AWD, t CWD, and tPRWC are not restrictive operating parameters and does not represent a limit of operation. WRITE CYCLE PARAMETER SYMBOL MIN. MAX. UNIT NOTE ns 1 EARLY WRITE Write command setup time (CAS) tWCS 0 Write command hold time (CAS) tWCH 15 ns Data input setup time tDS 0 ns Data input hold time tDH 20 ns OE CONTROLLED CAS setup time tCWS 0 ns 1 Write command lead time (RAS) tRWL 30 ns Write command lead time (CAS) tCWL 25 ns Write pulse width (WE) tWP 15 ns OE hold time (WE) tOEH 20 ns NOTE: 1. t WCS and tCWS are not restrictive operating parameters. If tWCS ≥ t WCS (MIN), the cycle is an early write cycle and data out buffers remain inactive until CAS rises again. READ-WRITE CYCLE/READ-MODIFY-WRITE CYCLE PARAMETER SYMBOL MIN. Read-write cycle time tRWC 260 MAX. UNIT NOTE ns 1 WE delay time (RAS) tRWD 135 ns 1 Column address delay time (WE) tAWD 85 ns 1 WE delay time (CAS) tCWD 65 ns 1 OE delay time tOED 25 ns NOTE: 1. t RWC, tRWD, t AWD, t CWD, and tPRWC are not restrictive operating parameters and does not represent a limit of operation. CAS BEFORE RAS REFRESH CYCLE/HIDDEN REFRESH CYCLE PARAMETER SYMBOL MIN. MAX. UNIT CAS setup time (RAS) tCSR 0 ns CAS hold time (RAS) tCHR 20 ns RAS • CAS precharge time (RAS ↑) tRPCP 10 ns RAS • CAS precharge time (RAS ↓) tRPCN 115 ns WE precharge time (RAS) tWRP 0 ns 2-20 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 tRC tRAS RAS tRP VIH VIL tCAS tRCD CAS tRSL tCRP VIH VIL tRCS tRCH tCSH tRAD tASR A0 - A8 VIH VIL tRAL tRAH ROW ADDRESS COLUMN ADDRESS tRRHP tRRHN WE VIH VIL tASC tCAH tROL OE VIH VIL tOEA tAA tCAC tRAC I/O1 - I/O4 VOH VOL tOFF tSOH tOEZ tOOH VALID DATA-OUT 6V4256-7 Figure 6. Read Cycle 2-21 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 tRC tRAS RAS tRP VIH VIL tRAD tRSL tRCD CAS tCAS tCRP VIH VIL tCSH tASR A0 - A8 VIH VIL tRAH ROW ADDRESS tCAH tASC COLUMN ADDRESS tWCS WE VIH VIL tDS I/O1 - I/O4 tWCH VIH VIL tDH VALID DATA-IN NOTE: OE = Don't Care 6V4256-8 Figure 7. Write Cycle (Early Write) 2-22 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 tRC tRAS RAS tRP VIH VIL tCSH tRCD tCAS tCRP tCWL CAS VIH VIL tRAD tASR A0 - A8 VIH VIL tASC tRAH ROW ADDRESS tCAH COLUMN ADDRESS tCWS tRWL tWP WE VIH VIL tOEH OE VIH VIL tOED tOEZ I/O1 - I/O4 VIH VIL tDS tDH VALID DATA-IN 6V4256-9 Figure 8. Write Cycle (OE Controlled Write) 2-23 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 tRWC tRAS RAS tRP VIH VIL tRCD CAS tCRP VIH VIL tCSH tRAD tRAH tASR A0 - A8 VIH VIL tASC ROW ADDRESS tCAH COLUMN ADDRESS tRWL tRWD tAWD tRCS tCWL tCWD tWP VIH WE V IL tOEH VIH OE V IL tDS tOEA tCAC tAA tRAC I/O1 - I/O4 VI/OH VI/OL tOED tOEZ tDH tOOH VALID DATA-OUT VALID DATA-IN 6V4256-10 Figure 9. Read/Write Cycle 2-24 VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VIL RAS CAS A0 - A8 WE OE I/O1 - I/O4 tRAH ROW ADDRESS tASR tRCD tRAD tRAC tRCS tASC tCSH tOEA tCAC tAA COLUMN ADDRESS tCAH tCAS tPC tCACP tCAH tCAS VALID DATA-OUT (1) tOFF tCAC tAA COLUMN ADDRESS tASC tCP tRAS tCACP tCAH tOFF tROL tAA tCAC COLUMN ADDRESS tASC tCP VALID DATA-OUT (2) tPC tRSL tCAS VALID DATA OUT (3) tRAL tOEZ tRRHP tCRP tRP 6V4256-11 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 Figure 10. Fast Page Mode Read Cycle 2-25 2-26 VIH VIL A0 - A8 Figure 11. Fast Page Mode Write Cycle VIH VIL NOTE: OE = Don't Care I/O1 - I/O4 VIH WE V IL VIH VIL VIH VIL CAS RAS tRAH ROW ADDRESS tASR tRCD tRAD tASC tDH tWCH COLUMN ADDRESS tCAH VALID DATA-IN (1) tDS tWCS tCSH tCAS tPC tCAH tDH tCAS VALID DATA-IN (2) tDS tWCS COLUMN ADDRESS tASC tCP tRAS tPC tCAH tRSL tDH VALID DATA-IN (3) tDS COLUMN ADDRESS tASC tCP tCAS tCRP tRP 6V4256-12 LH6V4256 CMOS 1M (256K × 4) Dynamic RAM I/OL VI/OH I/O1 - I/O4 V VIH OE VIL VIH WE VIL VIH A0 - A8 V IL VIH CAS VIL VIH RAS VIL ROW ADDRESS tASR tRAH tCAH tOEA tAA tCAC DATA OUT tOOH tCWL DATA IN tDH tWP tPRWC tDS tCAS tOED tOEZ tCWD tAWD COLUMN ADDRESS tASC tRCS tRAC tRCD tRAD tCSH tCAH tOEA DATA OUT tAA tCAC tCACP tPRWC tOEZ tDS tOED tOOH tCAS tCWD tAWD COLUMN ADDRESS tASC tCP tRAS DATA IN tDH tWP tCWL tCAH DATA OUT tAA tOEA tCAC tCACP tCAS tOEZ tOED tOOH tCWD tAWD COLUMN ADDRESS tASC tCP tRSL tDS DATA IN tDH tWP tRWL tCWL tRP 6V4256-13 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 Figure 12. Fast Page Mode Read/Write Cycle 2-27 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 tRC tRAS RAS VIH VIL tASR A0 - A 8 tRP VIH VIL tRAH ROW ADDRESS NOTE: CAS = 'H,' WE, OE = Don't Care 6V4256-14 Figure 13. RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tCSR tCHR tRPCP tRPCN VIH CAS VIL NOTE: WE, OE, A0 - A8 = Don't Care 6V4256-15 Figure 14. CAS Before RAS Refresh Cycle 2-28 VIH VIL I/OL V I/O1 - I/O4 VI/OH V OE VIH IL V WE VIH IL A0 - A 8 V CAS VIH IL V RAS VIH IL tRAH ROW ADDRESS tASR tRAD tRCS tRCD tRAC tASC tRAS tAA tCAC tRRHN tOEA COLUMN ADDRESS tCAH tRAL tRSL tRC tROL tRRHP tRP tWRP VALID DATA-OUT tRAS tCHR tRC tRP tOEZ tOFF tCRP 6V4256-16 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 Figure 15. Hidden Refresh Cycle 2-29 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 PACKAGE DIAGRAMS 20DIP (DIP020-P-0300A) 20 11 7.05 [0.278] 6.65 [0.262] 1 10 24.75 [0.974] 24.25 [0.955] 7.62 [0.300] TYP. 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 0.51 [0.020] MIN 2.54 [0.100] TYP. 0.30 [0.012] 0.20 [0.008] 0.56 [0.022] 0.36 [0.014] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 0° TO 15° 20DIP-3 20-pin, 300-mil DIP 26SOJ (SOJ026-P-0300) 26 22 0.25 [0.010] 0.15 [0.006] 18 14 7.90 [0.311] 8.50 [0.335] 7.50 [0.295] 8.30 [0.327] 1 5 9 17.40 [0.685] 17.00 [0.669] 7.00 [0.276] 6.60 [0.260] 13 0.20 [0.008] 1.10 [0.043] 3.70 [0.146] 1.70 [0.067] 3.30 [0.130] 0.50 [0.020] 1.27 [0.050] TYP. 0.53 [0.021] 0.33 [0.013] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 26SOJ-2 26-pin, 300-mil SOJ 2-30 CMOS 1M (256K × 4) Dynamic RAM LH6V4256 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.12 [0.005] 0.55 [0.022] TYP. 28 15 12.00 [0.472] 11.60 [0.457] 1 13.70 [0.539] 13.10 [0.516] 12.60 [0.496] 12.20 [0.480] 14 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] DETAIL 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] 0 - 10° 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 28TSOP 28-pin, 8 × 13 mm2 TSOP (Type I) ORDERING INFORMATION LH6V4256 Device Type X Package - ## Speed 10 100 Access Time (ns) D 20-Pin, 300-mil DIP (DIP020-P-0300A) K 26-Pin, 300-mil SOJ (SOJ026-P-0300) T 28-Pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) CMOS 1M (256K x 4) Dynamic RAM Example: LH6V4256D-10 (CMOS 1M (256K x 4) Dynamic RAM, 100 ns, 20-Pin, 300-mil DIP) 6V4256-17 2-31