SHARP LHF16KA1

PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S3NS-L10
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA1)
Spec No.: EL128039
Issue Date: August 22, 2000
SHARP
LHFlGKAl
l Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
l When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. in no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
l Office electronics
l instrumentation and measuring equipment
*Machine tools
l Audiovisual equipment
*Home appliance
*Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
l Control and safety devices for airplanes, trains, automobiles,
and other
transportation equipment
aMainframe computers
l Traff ic control systems
*Gas leak detectors and automatic cutoff devices
ORescue and security equipment
mother safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which dem?nds
extremely high performance in terms of functionality, reliability, or accuracy.
*Aerospace equipment
*Communications equipment for trunk lines
*Control equipment for the nuclear power industry
*Medical equipment related to life support, etc.
.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
l Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev.1.9
SHARP
LHFlGKAl
1
CONTENTS
PAGE
I INTRODUCTION
......................................................
3
PAGE
5 DESIGN CONSIDERATIONS
................................
.30
.30
1 .l Product Overview.. ..............................................
3
5.1 Three-Line Output Control ................................
! PRINCIPLES OF OPERATION.. ..............................
2.1 Data Protection ...................................................
6
5.2 STS and Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit Configuration
.30
Polling.. .............................................................
I BUS OPERATION.. ..................................................
3.1 Read ...................................................................
7
3.2 Output Disable .....................................................
3.3 Standby.. .............................................................
3.4 Deep Power-Down ..............................................
3.5 Read Identifier Codes Operation.. .......................
3.6 Query Operation.. ................................................
3.7 Write.. ..................................................................
7
7
7
7
7
8
8
8
5.3 Power Supply Decoupling .................................
.30
5.4 V,, Trace on Printed Circuit Boards.. ............... .3r
3’
5.5 Vc,, V,,, RP# Transitions.. ...............................
5.6 Power-Up/Down Protection.. ............................. .3’
5.7 Power Dissipation ..............................................
SPECIFICATIONS.. ........................
6.1 Absolute Maximum Ratings ...............................
6.2 Operating Conditions ........................................
6 ELECTRICAL
3’
.3:
3:
.3:
3:
6.2.1 Capacitance .................................................
6.2.2 AC Input/Output Test Conditions.. ............... .3:
COMMAND DEFINITIONS.. .....................................
8
4.1 Read Array Command.. .....................................
4.2 Read Identifier Codes Command.. ....................
11
6.2.3 DC Characteristics.. .....................................
.3L
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
4.5 Query Command.. .............................................
11
11
11
12
6.2.4
6.2.5
6.2.6
6.2.7
.3(
.3E
.41
4:
4.51 Block Status Register.. ................................
12
4.5.2 CFI Query Identification String.. ...................
4.5.3 System Interface Information.. .....................
4.5.4 Device Geometry Definition .........................
13
6.2.8 Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit
13
14
4.5.5 SCS OEM Specific Extended Query Table .. 14
4.6 Block Erase Command.. ....................................
15
4.7 Full Chip Erase Command ................................
15
16
4.8 Word/Byte Write Command.. .............................
4.9 Multi Word/Byte Write Command.. .................... 16
4.10 Block Erase Suspend Command.. ...................
17
4.11 (Multi) Word/Byte Write Suspend Command ... 17
4.12 Set Block Lock-Bit Command.. ........................ 18
4.13 Clear Block Lock-Bits Command.. ...................
4.14 STS Configuration Command .........................
AC Characteristics - Read-Only Operations
AC Characteristics - Write Operations.. .......
Alternative CE#Controlled Writes.. .............
Reset Operations .........................................
Configuration
Performance.. ........................
7 ADDITIONAL INFORMATION ...............................
7.1 Ordering Information .........................................
8 PACKAGE AND PACKING SPEClFlCATlbN........4
.44
.4E
.4E
7
.
18
19
Rev. 1.9
SHARP
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2
LH28F160S3NSLIO
16M-BIT (2MBx8/1 MBxl6)
Smart 3 Flash MEMORY
a
Smart 3 Technology
- 2.7V or 3.3V VCC
- 2.7V, 3.3V or 5V Vpp
n
Enhanced Data Protection Features
- Absolute Protection with VpP=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
n
Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
n
Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
n
Automated Write and Erase
- Command User Interface
- Status Register
n
Industry-Standard Packaging
- 56-Lead SSOP
n
ETOXTM’ V Nonvolatile
Technology
n
CMOS Process
(P-type silicon substrate)
n
Not designed or rated as radiation
hardened
n Common Flash Interface (CFI)
- Universal & Upgradable Interface
n
Scalable Command Set (SCS)
n
High Speed Write Performance
- 32 Bytes x 2 plane Page Buffer
- 2.7 @Byte Write Transfer Rate
n
High Speed Read Performance
- 1OOns(3.3Vk0.3V), 120ns(2.7V-3.6V)
n
Operating Temperature
- 0°C to +7O”C
n Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
I
High-Density Symmetrically-Blocked
Architecture
- Thirty-two 64K-byte Erasable Blocks
I
SRAM-Compatible
Write Interface
I
User-Configurable
x8 or x16 Operation
Flash
.
SHARP’s LH28F160S3NS-L10
Flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile,
,ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
Ind extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
iecure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S3NS-L10
offers three levels of protection: absolute protection with V,, at
SND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
-he LH28F160S3NS-LlO
is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface
CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer
ates and minimize device and system-level implementation costs.
-he LH28F160S3NSLlO
is manufactured on SHARP’s 0.35pm ETOX TM* V process technology.
idustry-standard package: the 56-Lead SSOP ideal for board constrained applications.
It come in
ETOX is a trademark of Intel Corporation.
Rev.1.9
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1 INTRODUCTION
This
datasheet
contains
LH28F160S3NS-LlO
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
The LH28F160S3NS-LlO
is a high-performance 16Mbit Smart
3 Flash
memory
organized
as
2MBx8/1MBxlG.
The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 3 technology provides a choice of Vcc and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 2.N
Vc, consumes approximately one-fifth the power of
5v Vcc. VP, at 2.7V, 3.3V and SJ eliminates the
need for a separate 12V converter, while V,,=5V
maximizes erase and write performance. In addition
to flexible erase and program voltages, the dedicated
V,,
pin gives complete data protection when
vPPsvPPLK.
Table 1. I/,.. and Vpp Voltage Combinations
Offe%d by Smart 3 Technology
Vcc Voltage
Vpp Voltage
2.7V
2.7V, 3.3V, 5V
3.3v
3.3v, 5v
Internal
and
detection
Circuitry
VCC
VP,
automatically configures the device for optimized
*cad and write operations.
4 Command
User Interface (CUI) serves as the
nterface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
nternal Write State Machine (WSM) automatically
mecutes the algorithms and timings necessary for
Ilock erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
4 block erase operation erases one of the device’s
i4K-byte blocks typically within 0.41s (3.3V Vcc, 5V
Ipp) independent of other blocks. Each block can be
ndependently
erased 100,000 times (3.2 million
Ilock erases per device). Block erase suspend mode
allows system software to suspend block erase to
ead or write data from any other block.
4 word/byte write is performed in byte increments
ypically within 12.95u.s (3.3V Vcc, 5V V,,). A multi
vord/byte write has high speed write performance of
!.7us/byte (3.3V V,,, 5V VP,). (Multi) Word/byte
3
write suspend mode enables the system to read data
or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software
polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 1OOns (tAvav) over the
commercial temperature range (0% to +7O”C) and
Vc, supply voltage range of 3.OV-3.6V. At lower V,,
voltage, the access time is 120ns (2.7V-3.6V).
The Automatic
Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical lCCR current is 3 mA at 33V V,,.
When either CE,# or CE,#, and RP# pins are at Vcc,
the loo CMOS standby mode is enabled. When the
RP# pin is. at GND, deep power-down mode is
enabled which minimizes power consumption
and
provides write protection during reset. A reset time
(tpHQv) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead SSOP (Shrink
Small Outline Package). Pinout is shown in Figure 2.
Rev. 1.9
SHARP
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C
WEX
00
RP#
WP#
-b
*
IIII I T
STS
Program/Erase
Voltage Switch
*
I
VW
4 kc
+
GND
Figure 1. Block Diagram
CE,,#
A12
A13
A14
4s
NC
CEl#
NC
A20
49
Ale
DQ5
DQ12
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ4
vcc
;3
A17
46
vcc
GND
DQ6
DO14
DQ7
DQls
S-6
OE#
WE#
WP#
DQn
56
55
54
53
52
51
:O
3
4
5
6
2:
56 LEAD SSOP
PINOUT
1.8mm x 16mm x 23.7mm
TOP VIEW
48
47
46
45
44
43
42
41
40
VPP
RP#
41
ho
As
A1
43
A7
.
A¶
GND
DQa
DQo
A0
BYTE#
NC
NC
DQ2
DQlo
DQ3
DQrl
GND
Figure 2. SSOP 56-Lead Pinout
Rev. 1.9
SHARP
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Symbol
*o-*20
DQo-DQ,
CEO%
CE,#
RP#
OE#
WE#
STS
WP#
5
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses durinq read and write operations. Addresses are
internally latched during a write cycle.
Ao: Byte Select Address. Not used in x16 mode(can be floated).
INPUT
AI-AK Column Address. Selects 1 of 16 bit lines.
AsAls: Row Address. Selects 1 of 2048 word lines.
A16420 : Block Address.
DATA INPUT/OUTPUTS:
DQo-DQ,:lnputs data and commands during CUI write cycles; outputs data during memory
array, statusregister, query, and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched
INPUT/
during a write cycle.
OUTPUT
DQs-DQ,s:lnputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in xl 6 mode; not used for status register, query and identifier code read
mode. Data pins float to hiqh-impedance when the chio is deselected, outouts are
disabled, or in x8 mode(By~e#=V,, ). Data is internally iatched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
INPUT
amplifiers. Either CE,# or CE,# Vlu deselects the device and reduces power consumotion
to standby levels. Bo?h CEr# and ‘CE,# must be VI, to select the devices.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V,, enables normal operation: When driven VI,, RP# inhibits
INPUT
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and arrav blocks. Addresses and data are
INPUT
latched on the rising edge of the WE# pulse.
’
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
OPEN
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
DRAIN
configuration). STS High Z indicates that the WSM is ready for new commands, block
OUTPUT erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deer, Dower-down mode. For alternate confiaurations of the
/STATUS pin, see the Configuratidn’command.
1WRITE PROTECT: Master control for block locking. When VI,. Locked blocks can not be
INPUT
Ierased and programmed,
and block lock-bits can not be set and reset.
IBYTE ENABLE: BYTE# VI, places device in x8 mode. All data is then inout or outout on
INPUT
IDQ,.,, and DQ,,, float. BYTE# V,, places the device in x16 mode , and turns off’the A0
i nput buffer.
IBLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCKI31T CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
SUPPLY (:onfiguring block lock-bits. With V,+V,,,,,
memory contents cannot be altered.,Block
terase, full chip erase, (multi) word/bvte write and block lock-bit confiauration with an invalid
\Jpp (see DC Characteristics) produce spurious results and should n’;;t be attempted.
IDEVICE POWER SUPPLY: Internal detection confioures the device for 2.7” or 3.3”
operation. To switch from one voltage to another, ramp Vcc down to GND and then ramp
SUPPLY ;/co to the new voltage. Do not float any power pins. With Vcc5VLk0, all write attempts to
he flash memory are inhibited. Device operations at invalid Vrr voltage (see DC
:zharacteristics ) produce spurious results and should not be afigmpted.
SUPPLY (iROUND: Do not float any ground pins.
r10 CONNECT: Lead is not internal connected: it may be driven or floated.
Type
IL.
BYTE#
“PP
“cc
GND
NC
Rev. 1.9
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6
2 PRINCIPLES OF OPERATION
The LH28F160S3NSLlO
Flash memory includes an
on-chip WSM to manage block erase, full chip erase,
lock-bit
write
and
block
(multi)
word/byte
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of the
VP, voltage. High voltage on VP, enables successful
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration.
All functions
associated with altering memory contents-block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration,
status, query and
identifier codes-are
accessed via the CUI and
verified through the status register.
Commands
are
written
using
standard
nicroprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
‘ull chip erase, (multi) word/byte write and block lockoit configuration.
The internal algorithms
are
*egulated by the WSM, including pulse repetition,
nternal
verification,
and margining
of data.
Addresses and data are internally latch during write
:ycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.
Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
-cad or write data from any other block. Write
suspend allows system software to suspend a (multi)
Nerd/byte write to read data from any other flash
nemory array location.
Figure 3. Memory Map
J
Rev. 1.9
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7
2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer
may choose to make the V,,
power supply
switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to VPPHlj2/a.
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
With OE# at a logic-high level (VI,), the device
outputs are disabled. Output pins DC&-DQ,, arc
placed in a high-impedance state.
memory contents cannot be
When V+VppLK,
altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
Zonfiguration
sequences,
command
provides
orotection from unwanted operations even when high
Joltage is applied to V,,. All write functions are
disabled when Vc, is below the write lockout voltage
dLKO or when RP# is at V,,. The device’s block
ocking capability provides additional protection from
nadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
Iperations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
:onform to standard microprocessor bus cycles.
3.1 Read
nformation can be read from any block, identifier
:odes, query structure, or status register independent
)f the V,, voltage. RP# must be at V,,.
-he first task is to write the appropriate read mode
:ommand (Read Array, Read Identifier Codes, Query
)r Read Status Register) to the CUI. Upon initial
levice power-up or after exit from deep power-down
node, the device automatically resets to read array
node. Five control pins dictate the data flow in and
but of the component: CE# (CE,#, CE,#), OE#, WE#,
3P# and WP#. CE,#, CE,# and OE# must be driven
ctive to obtain data at the outputs. CE,#, CE,# is
ie device selection control, and when active enables
ie selected memory device. OE# is the data output
DQc-DQ,,)
control and when active drives the
elected memory data onto the I/O bus. WE# and
IP# must be at V,,. Figure 17, 18 illustrates a read
ycle.
3.3 Standby
Either CE,# or CE,# at a logic-high level (VI,) place5
the device in standby mode which substantialI\
reduces device power consumption.
DQc-DQ, r
outputs are placed in a high-impedance
stat;
independent
of OE#. If deselected during block
erase, full chip erase, (multi) word/byte write ant
block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at V,, initiates the deep power-down mode.
In read modes, RP#-low deselects the memory
places output drivers in a high-impedance state ant
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tpHav is required after
return from power-down until initial memory access
outputs are valid. After this wakeup interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time t,,,,
is required after RP#
goes to logic-high (V,,) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
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8
,5 Read Identifier Codes Operation
3.6 Query Operation
ie read identifier codes operation outputs the
anufacturer code, device code, block status codes
r each block (see Figure 4). Using the manufacturer
Id device codes, the system CPU can automatically
atch the device with its proper algorithms. The
ock status codes identify locked or unlocked block
!tting and erase completed or erase uncompleted
Indition.
The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowestorder data output (DC&-DQ,) only.
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
Vcc=Vcc1,2 and ‘JPP=VPPH1/2/3,the CUI additionally
controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.
1FFFFFt
.
:
1FOOOC.
IEFFFF:.
..
:. Reserved for
y’‘.. Future Implementation
:
lFOCC6
lFOCiJ5lFOOQ4
lFOCO3
,.
..
l_______lll_---------------------
Block 31 Status Code
_____ -_-----------------------.. Reserved for
Future Implementation
Block 31
y
()2f3Joo;
..
..
:
.. (Blocks 2 through 30)
., : .i
:.
OlFFFF
.
Reserved for
Future tmpfementafion
010006
010005
010004
010003
3.7 Write
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.
___l______-_-l-l--l-________________^_
Block 1 Status Code
________________---------------------Reserved for
Future Implementation
omoo:
Block 1
OOFFFF
Reserved for
Future Implementation
4 COMMAND DEFINITIONS
When the V,, voltage 2 V,,Lk, Read operatrons from
the status register, identifier codes, query, or blocks
are enabled. Placing V,,,,,,,
on V,, enables
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
________-----------------
OOOOO6 -____------_-------------------------000005
Block
Ocmo4
0 Status Code
Device Code
__________--_-_--------------------Manufacturer Code
‘igure 4. Device Identifier
Code Memory Map
Rev. 1.9
SHARP
LHF16KAl
Mode
Read
Output Disable
Table 3. Bus Operations(BYTE#=V&
1 Notes 1 RP# ( CE,# 1 CE,# / OE# 1 WE#
V,,
V,,
V,,
V,H
V,,
V,,
V,H
V,H
VI,
VIH
Standby
VI,
VI,
X
X
1 Address
X
X
X
1 Vpp
X
X
X
I DQnm15 I STS
X
Dn,,r
HighZ
X
High Z
X
IOTES:
. Refer to DC Characteristics. When Vpp<VppLK, memory contents can be read, but not altered.
. X can be V,, or VrH for control pins and addresses, and V,,,, or VppH1/2/s for V,,. See DC Characteristics
vPPLK
and
vPPHll~3
for
vohw-
. STS is VoL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration algorithms. It is floated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power-down mode.
. RP# at GND&O.2V ensures the lowest deep power-down current.
. See Section 4.2 for read identifier code data.
. See Section 4.5 for query data.
. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when Vpp=VppHt/2/s and Vcc=Vcc,,2.
. Refer to Table 4 for valid D,, during a write operation.
. Don’t use the timing both OE# and WE# are V,,.
II
Rev. 1.9
SHARI=
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Command
Read Array/Reset
Read Identifier Codes
Querv
Read Status Register
Clear Status Register
Block Erase Setup/Confirm
Full Chip Erase Setup/Confirm
Word/Byte Write Setup/Write
Alternate Word/Byte Write
Setup/Write
Table 4.
Bus Cycles
Req’d
I
22
I
X
I
98H
I
Write
WA
/
10H
1 Write
Write
WA
1 Write
Write
Write
Write
Write
Write
576
58
Write
1
Read
I
QA
1 WA
I QD
(
WD
=B
Write
WA
N-l
I
3
uun
(Multi) Word/byte Write Resume
2
7
Write
Block Lock-Bit Set Setup/Confirm
60H
Block Lock-Bit Reset
r)
0
Write
L
Cl
60H
Setup/Confirm
STS Configuration
Level-Mode for Erase and Write
I Write I
X
I B8H I Write
(RY/BY# Mode)
STS Configuration
0
I
In,-:&Write
X
VVllLt:
I
x
B8H
OlH
Pulse-Mode for Erase
I
L
I
STS Configuration
2
Write
X
B8H
Write
X
02H
Pulse-Mode for Write
STS Configuration
Write
X
2
Write
X
B8H
03H
Pulse-Mode for Erase and Write
IOTES:
. BUS operations are defined in Table 3 and Table 3.1.
‘. X=Any valid address within the device.
IA=ldentifier Code Address: see Figure 4.
QA=Query Offset Address.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
. SRD=Data read from status register. See Table 14 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
.
ID=Data read from identifier codes.
QD=Data read from query database.
. Following the Read Identifier Codes command, read operations access manufacturer, device and block status
codes. See Section 4.2 for read identifier code data.
. If the block is locked, WP# must be at VI, to enable block erase or (mufti) word/byte write operations. Attempts
to issue a block erase or (multi) word/byte write to a locked block while RP# is V,,.
. Either 40H or 10H are recognized by the WSM as the byte write setup.
A block lock-bit can be set while WP# is V,,.
, WP# must be at V,, to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block
lock-bits.
Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm
command ‘DOH’.
3. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
=I= I X I OOH
Rev. 1.9
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LHFlGKAl
11
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the
Read Array command. The device remains enabled
for reads until another command is written. Once the
internal WSM has started a block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration, the device will not recognize the Read
Array command
until the WSM completes
its
operation unless the WSM is suspended via an Erase
Suspend and (Multi) Word/byte Write Suspend
:ommand.
The Read Array command functions
ndependently of the V,, voltage and RP# must be
The status register may be read to determine when z
block erase, full chip erase, (multi) word/byte write o
block lock-bit configuration is complete and whethe
the operation completed successfully(see Table 14)
It may be read at any time by writing the Read Statu:
Register command. After writing this command, al
subsequent read operations output data from the
status register until another valid command is written
The status register contents are latched on the fallins
edge of OE# or CE#(Either
CEc# or CE,#)
whichever occurs. OE# or CE#(Eithei CE,# or CE,#;
must toggle to Vi, before further reads to update the
status register latch. The Read Status Register
command functions independently of the V,, voltage
RP# must be Vi,.
JIH-
1.2 Read identifier Codes Command
The identifier code operation is initiated by writing the
qead Identifier Codes command.
Following the
:ommand write, read cycles from addresses shown in
‘igure 4 retrieve the manufacturer, device, block lock
:onfiguration and block erase status (see Table 5 for
dentifier code values). To terminate the operation,
vrite another valid command. Like the Read Array
:ommand, the Read Identifier Codes command
unctions independently of the V,, voltage and RP#
nust be Vi,. Following the Read Identifier Codes
:ommand, the following information can be read:
Table 5. Identifier Codes
Code
Address
00000
Manufacture Code
00001
00002
Device Code
00003
Data
BO
DO
*Last erase operation did
DQ,=l
not completed successfully
OReserved for Future Use
DQps7
IOTE:
. X selects the specific block status code to be
read. See Figure 4 for the device identifier code
memory map.
The extended status register may be read tc
determine multi word/byte write availability(see Table
14.1). The extended status register may be read al
any time by writing the Multi Word/Byte Writs
command. After writing this command, all subsequenl
read operations output data from the extended status
register, until another valid command is written. Multi
Word/Byte Write command must be re-issued to
update the extended status register latch.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to “1”s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 14). By allowing
system software
to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled
to determine if an error occurs during the sequence.
To clear the status register, the Clear Status Register
command @OH) is written. It functions independently
of the applied V,, Voltage. RP# must be Vi,. This
command is not functional during block erase, full
chip erase, (multi) word/byte write block lock-bil
configuration,
block erase suspend
or (multi)
word/byte write suspend modes.
Rev. 1.9
SHARP
LHFlGKAl
4.5 Query Command
Query database can be read by writing Query
:ommand (98H). Following the command write, read
cycle from address shown in Table 7-l 1 retrieve the
xitical information to write, erase and otherwise
:ontrol the flash component. Ac of query offset
address is ignored when X8 mode (BYTE#=V,,).
3uery data are always presented on the low-byte
lata output (DQc-DQ,). In x16 mode, high-byte
DQs-DQ,,) outputs OOH. The bytes not assigned to
Iny information or reserved for future use are set to
‘0”. This command functions independently of the
Ipp voltage. RP# must be V,,.
12
Table 6. Example of Query Structure Output
Mode
Offset Address
output
DQ, q-a DQ7-,,
A,, A,, A,, A29 A,, A,
1 , 0 , 0 , 0 , 0 , 0 (20H) High Z
“Q”
X8mode
1,0,0,0,0,1(21H)
HighZ
“Q”
1, O,O,O,l
,0(22H)
HighZ
“R”
1 , 0 , 0 , 0 , 1 , 1 (23H) High Z
“R”
Ag, A,, A,, A,, A,
OOH
X16mode
1 ,O,O,O,O
(10H)
“Q”
l,O,O,O,l
(11H)
OOH
“R”
1.5.1 Block Status Register
-his field provides lock configuration and erase status for the specified block. These informations are only availablt
vhen device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase statu:
rit will be set to “1”. If bit 1 is “l”, this block is invalid.
Table 7. Query Block Status Register
Offset
(Word Address)
(BA+2)H
Description
Length
OlH
Block Status Register
bit0 Block Lock Configuration
O=Block is unlocked
1=Block is Locked
bit1 Block Erase Status
O=Last erase operation completed successfully
1=Last erase operation not completed successfully
bit2-7 reserved for future use
lote:
. BA=The beginning of a Block Address.
.
Rnw
1 a
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4.5.2 CFI Query Identification
13
String
The Identification String provides verification that the component supports the Common Flash Interface
specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are:
supported.
Table 8. CFI Query Identification
Offset
(Word Address)
lOH,l lH,12H
13H,14H
-l5H,16H
Description
Length
03H
02H
02H
17H,18H
02H
lSH,lAH
02H
String
Query Unique ASCII string “QRY”
51 H,52H,59H
Primary Vendor Command Set and Control Interface ID Code
01 H,OiH (SCS ID Code)
Address for Primary Algorithm Extended Query Table
31 H,OOH (SCS Extended Query Table Offset)
Alternate Vendor Command Set and Control Interface ID Code
OOOOH(OOOOHmeans that no alternate exists)
Address for Alternate Algorithm Extended Query Table
OOOOH(OOOOHmeans that no alternate exists)
4.5.3 System Interface Information
The following device information can be useful in optimizing system interface software.
Table 9. System Information
Offset
(Word Address)
1BH
Length
OlH
1CH
01H
1DH
OlH
1EH
OlH
1FH
OlH
20H
OlH
21H
OlH
22H
OlH
23H
OlH
24H
OlH
25H
OlH
26H
OlH
String
Description
Vcc Logic Supply Minimum Write/Erase voltage
27H (2.7V)
Vcc Logic Supply Maximum Write/Erase voltage
55H (5.5V)
V,, Programming Supply Minimum Write/Erase voltage
27H (2.7V)
V,, Programming Supply Maximum Write/Erase voltage
55H (5.5V)
Typical Timeout per Single Byte/Word Write
03H (23=8us)
Typical Timeout for Maximum Size Buffer Write (32 Bytes)
06H (2’-j=64us)
Typical Timeout per Individual Block Erase
OAH (OAH=lO, 2r”=1 024ms)
Typical Timeout for Full Chip Erase
OFH (OFH=15, 215=32768ms)
Maximum Timeout per Single Byte/Word Write, 2N times of typical.
04H (24=16, 8usx16=128us)
Maximum Timeout Maximum Size Buffer Write, 2N times of typical.
04H (24=1 6, 64usx16=1024us)
Maximum Timeout per Individual Block Erase, 2N times of typical.
04H (24=1 6, 1024msxl6~16384ms)
Maximum Timeout for Full Chip Erase, 2N times of typical.
04H (24=1 6, 32768msxl6=524288ms)
Rev. 1.9
SHARI=
LHFlGKAl
14
3.5.4 Device Geometry Definition
rhis field provides critical details of the flash device geometry.
Table 10. Device Geometry
Off set
(Word Address)
27H
Length
OlH
28H,29H
02H
2AH,2BH
02H
2CH
OlH
2DH,2EH
02H
2FH,30H
02H
1.55 SCS OEM Specific
Definition
Description
Device Size
15H (15H=21,221=20971 52=2M Bytes)
Flash Device interface description
02H,OOH (x8/x1 6 supports x8 and xl 6 via BYTE#)
Maximum Number of Bytes in Multi word/byte write
05H,OOH (25=32 Bytes )
Number of Erase Block Regions within device
01 H (symmetrically blocked)
The Number of Erase Blocks
1 FH,OOH (1 FH=31 ==> 31 +1=32 Blocks)
The Number of “256 Bytes” cluster in a Erase block
OOH,OlH (01 OOH-13256==>256 Bytes x 256= 64K Bytes in a Erase Block)
Extended Query Table
:ertain flash features and commands may be optional in a vendor-specific algorithm specification. The optional
endor-specific Query table(s) may be used to specify this and other types of information. These structures are
efined solely by the flash vendor(s).
Tat e 11. SCS OEM Specific Extended
Off set
(Word Address)
31 H,32H,33H
34H
35H
36H,37H,
38H,39H
Length
Query Table
Description
03H
OlH
OlH
04H
Optional Command Support
bitO=l
: Chip
Erase
Supported
bitl=l : Suspend Erase Supported
bit2=1 : Suspend Write Supported
bit3=1 : Lock/Unlock Supported
bit4=0 : Queued Erase Not Supported
bit5-31=0 : reserved for future use
3AH
OlH
iBH,3CH
02H
IDH
OIH
IEH
OlH
IFH
reserved
01H
Supported Functions after Suspend
bitO=l : Write Supported after Erase Suspend
bitl-7=0 : reserved for future use *
03H,OOH
Block Status Register Mask
bitO=l : Block Status Register Lock Bit [BSRO] active
bitl=l : Block Status Register Valid Bit [BSR.l] active
bit2-15=0 : reserved for future use
Vcc Logic Supply Optimum Write/Erase voltage(highest performance)
50H(5OV)
V,, Programming Supply Optimum Write/Erase voltage(highest performance)
50H(5.OV)
Reserved for future versions of the SCS Specification
REV
i a
SHARP
LHFlGKAl
4.6 Block Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by an block erase
confirm.
This
command
sequence
requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically
outputs status
register data when read (see Figure 5). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit SR.7.
iNhen the block erase is complete, status register bit
5R.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
.emains in read status register mode until a new
:ommand is issued.
rhis two-step command sequence of set-up followed
)y execution ensures that block contents are not
tccidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
rnd SR.5 being set to “1’. Also, reliable block erasure
:an only occur when Vcc=Vcc1,2 and VPP=VPPHf,2/3.
n the absence of this high voltage, block contents
Ire protected against erasure. If block erase is
Ittempted while V,,<V,,,k,
SR.3 and SR.5 will be
‘et to “1”. Successful block erase requires that the
:orresponding block lock-bit be cleared or if set, that
VP#=V,,. If block erase is attempted when the
orresponding block lock-bit is set and WP#=V,‘,
iR.1 and SR.5 will be set to “1 ‘I.
15
erase setup is first written, followed by a full chip
erase confirm. After a confirm command is written,
device erases the all unlocked blocks from block 0 to
Block 31 block by block. This command sequence
requires
appropriate
sequencing.
Block
preconditioning,
erase and verify are handled
internally by the WSM (invisible to the system). After
the two-cycle full chip erase sequence is written, the
device automatically outputs status register data
when read (see Figure 6). The CPU can detect fu
chip erase completion by analyzing the output data c
the STS pin or status register bit SR.7.
When the full chip erase is complete, status registe
bit SR.5 should be checked. If erase error ii
detected, the status register should be cleared before
system software attempts corrective actions. The CU
remains in read status register mode until a nev
command is issued. If error is detected on a bloc1
during full chip erase operation, WSM stops erasing
Reading the block valid status by issuing Read IL
Codes command or Query command informs whict
blocks failed to its erase.
This two-step command sequence of set-up followec
by execution ensures that block contents are no
accidentally erased. An invalid Full Chip Erase
command sequence will result in both status registe
bits SR.4 and SR.5 being set to “1”. Also, reliable ful
chip erasure can only occur when Vcc=Vcc1,2 ant
vpp=v PPH1/2/3*
In the absence of this high voltage
block contents are protected against erasure. If ful
chip erase is attempted while Vpp~Vpp,k, SR.3 ant
SR.5 will be set to “1”. When WP#=V,H, all blocks arc
erased independent of block lock-bits status. Wher
WP#=VIL, only unlocked blocks are erased. In thi:
case, SR.1 and SR.5 will not be set to “1“. Full chic
erase can not be suspended.
I.7 Full Chip Erase Command
‘his command followed by a confirm command
IOH) erases all of the unlocked blocks. A full chip
Rev. 1.9
SHARP
LHFlGKAl
4.8 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/Byte Write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word/byte write and write verify
algorithms internally. After the word/byte
write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The
CPU can detect the completion of the word/byte write
event by analyzing the STS pin or status register bit
33.7.
When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is
jetected, the status register should be cleared. The
nternal WSM verify only detects errors for “1”s that
jo not successfully write to “0”s. The CUI remains in
‘cad status register mode until it receives another
zommand.
qeliable word/byte writes can only occur when
~cc=Vcc1,2 and VPP=VPPHln/3. In the absence of
:his high voltage, memory contents are protected
against word/byte writes. If word/byte write is
ittempted while V,@,,,,,
status register bits SR.3
snd SR.4 will be set to “1”. Successful word/byte
Nrite requires that the corresponding block lock-bit be
:leared or, if set, that WP#=V,,. If word/byte write is
ittempted when the corresponding block lock-bit is
;et and WP#=V,,, SR.l and SR.4 will be set to “1”.
Nordlbyte
write operations
with V,,<WP#<V,,
lroduce
spurious results and should not be
ttempted.
1.9 Multi Word/Byte Write Command
lulti word/byte write is executed by at least fourycle or up to 35cycle command sequence. Up to
2 bytes in x8 mode (16 words in x16 mode) can be
jaded into the buffer and written to the Flash Array.
irst, multi word/byte write setup (E8H) is written with
le write address. At this point, the device
utomatically outputs extended status register data
(SR) when read (see Figure 8, 9). If extended
:atus register bit XSR.7 is 0, no Multi Word/Byte
/rite command is available and multi word/byte write
ztup which just has been written is ignored. To retry,
16
continue monitoring XSR.7 by writing multi word/byte
write setup with write address until XSR.7 transition.
to 1. When XSR.7 transitions to 1, the device is read
for loading the data to the buffer. A word/byte coun
(N)-1 is written with write address. After writing i
word/byte count(N)-1, the device automatically turn:
back to output status register data. The word/byte
count (N)-1 must be less than or equal to IFH in xl
mode (OFH in x16 mode). On the next write, devict
start address is written with buffer data. Subsequen
writes provide additional device address and data
depending on the count. All subsequent addres:
must lie within the start address plus the count. Afte
the final buffer data is written, write confirm (DOH
must be written. This initiates WSM to begin copyin!
the buffer data to the Flash Array. An invalid Mull
Word/Byte Write command sequence will result ir
both status register bits SR.4 and SR.5 being set tc
“1”. For additional multi word/byte write, write anothe
multi word/byte write setup and check XSR.7. The
Multi Word/Byte Write command can be queuec
while WSM is busy as long as XSR.7 indicates “1”
because LH28F160S3NS-LlO
has two buffers. If ar
error occurs while writing, the device will stop writin{
and flush next multi word/byte write command loader
in multi word/byte write command. Status register bi
SR.4 will be set to “1”. No multi word/byte write
command is available if either SR.4 or SR.5 are se
to “1”. SR.4 and SR.5 should be cleared before
issuing multi word/byte write command. If a mult
word/byte write command is attempted past an erase
block boundary, the device will write the data to Flasr
Array up to an erase block boundary and then star
writing. Status register bits SR.4 and SR.5 will be se
to “1 I’.
Reliable multi byte writes can only occur when
Vcc=Vcc1,2 and VPP=VPPH1,2,3. In the absence of
this high voltage, memory contents are protected
against multi word/byte writes. If multi word/byte write
is attempted while V,+V,,,,,
status register bits
SR.3 and SR.4 will be set to “1”. Successful multi
word/byte write requires that the correspoiding block
lock-bit be cleared or, if set, that WP#=V,,. If multi
byte write is attempted when the corresponding block
lock-bit is set and WP#=V,,, SR.l and SR.4 will be
set to “1 ‘I.
Rev-l.9
SHARI=
17
LHFl6KAi
4.10 Block Erase Suspend Command
The Block Erase Suspend command allows blockerase interruption to read or (multi) word/byte-write
data in another block of memory. Once the blockerase process starts, writing the Block Erase
Suspend command requests that the WSM suspend
the block erase sequence at a predetermined point in
the algorithm. The device outputs status register data
when read after the Block Erase Suspend command
is written. Polling status register bits SR.7 and 93.6
can determine when the block erase operation has
been suspended (both will be set to “1”). STS will
also transition to High Z. Specification twHRH2 defines
the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A (Multi) Word/Byte Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the (Multi)
Word/Byte Write Suspend command (see Section
4.1 l), a (multi) word/byte write operation can also be
suspended. During a (multi) word/byte write operation
Nith block erase suspended, status register bit 33.7
NilI return to “0” and the STS (if set to RY/BY#)
xrtput will transition to V,,. However, SR.6 will
‘emain “1” to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
:ommand is written to the flash memory, the WSM
NilI continue the block erase process. Status register
Iits SR.6 and SR.7 will automatically clear and STS
will return to Vo,. After the Erase Resume command
s written, the device automatically outputs status
egister data when read (see Figure 10). V,, must
emain at V,,,,,zs
(the same V,, level used for
Jlock erase) while block erase is suspended. RP#
must also remain at V,,. Block erase cannot resume
until (multi) word/byte write operations initiated during
block erase suspend have completed.
4.11
(Multi) Word/Byte
Command
Write
Suspend
The (Multi) Word/Byte Write Suspend command
allows (multi) word/byte write interruption to read data
in other flash memory locations. Once the (multi)
word/byte write process starts, writing the (Multi)
Word/Byte Write Suspend command requests that
the WSM suspend the (multi) word/byte
write
sequence at a predetermined point in the algorithm.
The device continues to output status register data
when read after the (Multi) Word/Byte Write Suspend
command is written. Polling status register bits SR.7
and SR.2 can determine when the (multi) word/byte
write operation has been suspended (both will be set
to “1”). STS will also transition to High Z.
Specification twHRHl defines the (multi) word/byte
write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
(multi) word/byte write is suspended are Read Status
Register and (Multi) Word/Byte Write Resume. After
(Multi) Word/Byte Write Resume command is written
to the flash memory, the WSM will continue the
(multi) word/byte write process. Status register bits
SR.2 and SR.7 will automatically clear and STS will
return to VOL. After ‘the (Multi) Word/Byte Write
command is written, the device automatically outputs
status register data when read (see Figure 11). V,,
must remain at VPPH1,2/3 (the same V,, level used
for (multi) word/byte write) while in (multi) word/byte
write suspend mode. WP# must also remain at V,, or
VI,.
SHARP
LHF16KAl
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations
With WP#=V,,,
individual block lock-bits can be set using the Set
Block Lock-Bit command.
See Table 13 for a
summary of hardware and software write protection
options.
Set block lock-bit is executed
by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 12). The CPU can detect the completion
of the set block lock-bit event by analyzing the STS
pin output or status register bit SR.7.
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an error
s detected, the status register should be cleared.
The CUI will remain in read status register mode until
3 new command is issued.
rhis two-step sequence
of set-up followed by
?xecution ensures that block lock-bits are not
iccidentally set. An invalid Set Block Lock-Bit
:ommand will result in status register bits SR.4 and
jR.5 being set to “1”. Also, reliable operations occur
)nly when Vcc=Vcc1,2 and VPP=VPPH1,2/3. In the
absence of this high voltage, block lock-bit contents
Ire protected against alteration.
4 successful set block lock-bit operation requires
YP#=V,,. If it is attempted with WP#=V,L, SR.l and
jR.4 will be set to “1” and the operation will fail. Set
plock lock-bit operations with WP#<V,, produce
spurious results and should not be attempted.
I.13 Clear Block Lock-Bits
18
block lock-bits can be cleared using only the Clea
Block Lock-Bits command.
See Table 13 for i
summary of hardware and software write protectior
options.
Clear block lock-bits operation is executed by a two
cycle command sequence. A clear block lock-bit!
setup is first written. After the command is written, th6
device automatically outputs status register dat:
when read (see Figure 13). The CPU can detec
completion of the clear block lock-bits event b!
analyzing the STS Pin output or status register bi
SR.7.
When the operation is complete, status register bi
SR.5 should be checked. If a clear block lock-bit erro
is detected, the status register should be cleared
The CUI will remain in read status register mode unti
another command is issued.
This two-step sequence
of set-up followed b)
execution
ensures that block lock-bits are no
accidentally cleared. An invalid Clear Block Lock-Bit:
command sequence will result in status register bit:
SR.4 and SR.5 being set to “1”. Also, a reliable clear
block lock-bits operation
can only occur wher
Vcc=Vcc,,2 and VPP=VPPH11213.If a clear block lockbits operation is attempted while V,+V,,Lk,
SR.C
and SR.5 will be set to “1”. In the absence of this higtvoltage, the block lock-bits content are protectec
against alteration. A successful clear block lock-bits
operation requires WP#=V,,. If it is attempted with
WP#=V,,, SR.l and SR.5 will be set to “1” and the
operation will fail. Clear block lock-bits operations
with V,,cRP# produce spurious results and should
not be attempted.
If a clear block lock-bits operation is aborted due to
V,, or Vc, transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
Command
\I1 set block lock-bits are cleared in parallel via the
Iear Block Lock-Bits command. With WP#=V,,,
.
Rrv
19
SHARI=
LHFlGKAl
4.14 STS Configuration
19
s,
Command
The Status (STS) pin can be configured to different
states using the STS Configuration command. Once
the STS pin has been configured, it remains in that
configuration until another configuration command is
issued, the device is powered down or RP# is set to
VI,. Upon initial device power-up and after exit from
deep power-down mode, the STS pin defaults to
RY/BY# operation where STS low indicates that the
WSM is busy. STS High Z indicates that the WSM is
ready for a new operation.
To reconfigure the STS pin to other modes, the STS
Configuration is issued followed by the appropriate
configuration code. The three alternate configurations
are all pulse mode for use as a system interrupt. The
STS Configuration command functions independently
If the V,, voltage and RP# must be V,,.
Table 12. ST! Configuration
Coding Description
Configuratior
Effects
Bits
Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
OOH
level-mode of operation will indicate
WSM status condition.
Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at
01H
the completion of BLock Erase,
Full Chip Erase and Clear Block
Lock-bits operations.
Set STS pin to pulsed output signal
for a specific write operation. In this
mode, STS provides low pulse at
02H
the completion of (Multi) Byte Write
and Set Block Lock-bit operation.
Set STS pin to pulsed output signal
for specific write and. erase
operation. STS provides low pulse
03H
at the completion of Block Erase,
Full Chip Erase, (Multi) Word/Byte
Write and Block Lock-bit
Configuration operations.
Table 13. Write Protection
Block
Lock-Bit
0
Operation
Block Erase,
(Multi) Word/Byte
Write
WP#
I
1
V,, or VI,,
I
VI,
O,l
Full Chip Erase
X
X
Set Block Lock-Bit
Clear Block Lock-Bits
X
f
Effect
Block Erase and (Multi) Word/Byte Write Enabled
Block is Locked. Block Erase and (Multi)
.
, Word/Bvte
, Write
Disabled
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte
Write Enabled
All unlocked blocks are erased, locked blocks are not erased
All blocks are erased
Set Block Lock-Bit Disabled
Set Block Lock-Bit Enabled
.
Clear Block Lock-Bits Disabled
Clear Block Lock-Bits Enabled
kli
\I,
V
V
V
V
V
V
Alternatives
SHARP
LHFlGKAi
20
Table 14. Status Register Definition
WSMS
7
1
BESS
6
1 ECBLBS
1 WSBLBS
5
4
1
VPi=‘S
3
1
wss
2
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check STS or SR.7 to determine block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7=“?.
SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR.5 and SR.4 are “1”s after a block erase, full
chip erase, (multi) word/byte write, block lock-bit
configuration or STS configuration attempt, an improper
command sequence was entered.
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS
1 = Error in Erase or Clear Bloc1 Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
SR.3 = V,, STATUS
1 = V,, Low Detect, Operation Abort
O=V,,OK
SR.3 does not provide a continuous indication of V,,
level. The WSM interrogates and indicates the V,, level
only after block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V,,#V,,,tIus.
SR.l does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
WP# is not V,,. Reading the block lock configuration
codes after writing the Read Identifier Codes command
indicates block lock-bit status.
SR.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
SR.0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
SMS
R
7
6
Table 14.1. Extended
R
R
5
4
Status Register Definition
R
R
3
2
R
R
1
0
NOTES:
XSR.7 = STATE MACHINE STATUS
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.G-O=RESERVED FOR FUTURE ENHANCEMENTS
XSR.G-0 is reserved for future use and should be
masked out when polling the extended status register.
Rev.l.9
SHARI=
LHFlGKAl
21
Read Status
Rqster
DstalOH
AddhX
I
f
Road Status
Register
Read
Status Re+ter
Data
I
Check SR.7
l-W.%4 Ready
o=.wsM Busy
write
Etase Setup
Writ.3
Data-ZJH
AcklbWitim
Block to be Erased
I
DaQDOH
I A&Jr-Withm
Block to be Erased
I
Repeat for subsequent block emsures.
Full status dwck can t-a done after each block erase or aftor a sequence of
block erasums.
Write FFH after the last operation to place device in mad army mode.
FULL STATUS CHECK PROCEDURE
(E)
Check SR.4.5
Both l=Command Sequence Error
Standby
Standby
.
Check SR.5
l=Block Erase Erm~
SR.S.SR.4.SR.3 and SR.l are only cleared by the Clear ?&ha
Register Command in cases where multiple blocks are erased
before full status is checked.
If wmris detected. clear the Status Register before attempting
“by or other ermr recovery.
Block Erase Successful
Figure 5. Automated
Block Erase Flowchart
SHARP
LHF16KAl
r
!3arl
Bm
Commvld
commenta
Opmaon
*
Wnta 70H
Wrilo
+
Read Status
Read Status
Register
Status Register Data
Read
Check SR.7
l-W%4 Ready
OIWSM Busy
Slandbl
Wit0
Full Chop Erase
SbJP
Writ0
Data70H
AddhX
Futl Chip Erate
conflml
Data&OH
Addr-X
DataPDOH
AddhX
Status Regoster Data
Read
Check SR.7
1PWSM Ready
O=WSM Busy
Standby
Full status check can be done after each full chip emse.
Write FFH after the last operation to place device in mad army mode.
G-tack if Desired
Complete
FULL STATUS CHECK PROCEDURE
Reed status RaglStw
Data(Sw Above)
Blu
OpfdlOn
Command
Standby
Comments
Chedc SR.3
l=Vpp Ermr Detect
Check SR.4,5
B& l-Command
Staml~
Sequence Enor
Check SR.5
t-Full Chip Erase Emx
I
SRS.SR.4.SR.3 and SR.l am only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or olher ermr recovery.
Full Chip Erase
SUCCWdlll
Figure 6. Automated
Full Chip Erase Flowchart
Rev. 1.9
SHARI=
LHFlGKAl
Bus
OprdiOn
23
Command
Writ9
Data-7OH
Addr-X
Read
Status Rogirter Data
Check SR.7
l=WSM Redy
o=WSM susy
Standby
Data and Addmss
commmb
Wlite
Setup wordmyte
Write
Data-4OH or 10H
Addr=Locatfwl to Be Written
Write
wofd/syta
Data-Data to Be Wdtten
Addr=Localion to Be Written
write
Status Regirtm Data
Read
Check SR.7
l=WSM Ready
O=WSM Busy
standby
Repeat for subsequent word/byte writes.
SR lull status check can be done after each wo&byte write. or after a requenee Of
worcuayte wdtes.
Write FFH after the last vmrdmyie write operation to place device in
mad army mode.
Complete
FULLSTATUSCHECKPROCEDURE
Read St&us Register
Data(See Above)
Command
Comments
Standby
check SR.3
l=Vpp Error Detect
Standby
Check SR.1
laDevice Protect Detect
WP#=VIL.Sfock Lock-Sit is Set
Only required for systems
implementing lock-bit configuration
.
Check SR.4
l-Data Write Error
Standby
SR.4.SR.3 and 33.1 am only cleared by the Clear Status Rqster
command in cases where multiple locations are written before
full stahls is checked.
If error is detected. clear tie Status Register before attempting
retry or ouler envr recovery.
Figure 7. Automated
Word/byte
Write Flowchart
I
Ps,,
i
a
SHARP
24
LHFlGKAl
Comments
Command
Write
=w
Multi Wordlsyte Write
DZ9ta-EBH
Addr-Staft Addross
Exb3ti
Read
status Register Data
Check XSR.7
standby
1iM”lti woldByte writs Ready
OMUlti word/Byte write Busy
Write
(Notal)
Data-Word or Byte Count (N)-1
Addr..Start Address
Wflte
(Note2.3)
Data=B”ffer Data
AddwStart Address
Wnte
(Note4.5)
Dataz8uffer Data
Addr-Device Address
write
Data-OOH
Addr-X
Read
Status Register Data
Standby
Check SR.7
I =WSM Ready
o..W.sM BUSY
1. Byte or word count values on DO,,., are loaded into the count register.
2. Write Buffer contents mll be programmed at me start address.
3. Align tie start address on a Write Buffer boundary for maximum
pmgramming performance.
4.The device aborts the Multi Wad/&B
Write command if the current address is
oulside of the original block address.
S.The Status Regtster tindicates an ‘improper command sequence’ if the Multi
Wotiyte
command is aborted. Follow this with a Clear Status Register command.
SR full status check can be done after each multi wrdmyte write,
or after a sequence 01 multi wadbyte writes.
Write FFH after the last multi wordbyte write operation to place device in
read array mode.
Suspend Multi Word/Byte
Full Status
Check if Dewed
Figure 8. Automated
Multi Word/Byte
Write Flowchart
SHARP
LHFlGKAl
25
FULL STATUS CHECIC PROCEDURE FOR
MlLTl WORCMBYIE WRITE OPERATION
Bus
opwalfon
Command
Commmt9
Check SR.3
l=Vpp Error Detect
Check SR.1
1lDwico Pmtect Detect
WP*IV,~.B!G~ L&-Sit is Set
only mquimd for syslams
implementing lock-bit configuration
Device Protect Error
Check SR.4.5
Both f-Command
Sequence Ermr
Check SR.4
1=Data write Error
SR.S.SR.4.SFi.3 and SR.1 are only cleared by the Clear Status Rqster
cammmd in cases where multiple locations am written before
M status is checked.
If enorb detected, clear the Status f?a#er before attempting
mly or other emr mcwety.
Figure 9. Full Status Check Procedure for Automated
Multi Word/Byte
Write
SHARP
LHFlGKAl
Btm
OpWliOn
O
1
c>
caatmanb
Commmd
Writ0
Data-B0H
AddhX
Read
AddhX
Statur Rogistar Data
stancby
Check SA.7
l.WSM Rae&j
OIWSM Busy
standby
ChodcSR.0
11Btock Erase Surpw~Ied
O-Block Erase Completed
SR.7P
Wti
Ento
Rasuma
Da&&OH
Addr-X
(Mulli) WorrUByte Write Loop
Wnte DOH
I
Write FFH
c
I
Figure 10. Block Erase Suspend/Resume
Flowchart
RPV
IQ
SHARP
LHF16KAl
27
Bus
I 0-n I
I
(Multi) Wad/Byte
1
%I.?=
+
wli(e
1
Commenta
Command
Suspend
Wtite
Data-SOH
1 Addh*
0
chedc SR.2
l.(Multl) WordByte
1
(Multi)wofcuBytewrite
Completed
SMpWlded
0+4ulti) WordByte
Completed
i_
Write
Read Array
Data-FFH
Ac!dr=X
F
Wtita FFH
I
Write
Figure 11. (Multi) Word/Byte
Write Suspend/Resume
Flowchart
write
write
SHARP
LHFlGKAl
Bus
Op&iOll
28
Command
Set Block
Write
Resd
t-’
Status Register
SIX?=
Wlile
Leek-Bit Seh~p
fzommmta
DaradOH
Addr=Slock Address
Sat Block
Data-01 H.
Lock-Sit Confin
Addr-Block
Rsad
Address
Status Register Data
Check SR.7
l=WSM Ready
OaWSM Busy
0
1
Check if Desired
Repeat for subsequent block lock-bit set operations.
Full status chock can be done after each block lock-btt set operation
or after a sequence of block lock-bit set operatiwn.
W&e FFH after the last blak lock-bit set operation to place device in
read array mode.
FULLSTATUSCHECKPROCEDtJRE
Read Stah~o Register
Data(see Abwe)
1 OWL” / timmand/
Device Protect Ermr
fhnmsnb
Standby
Check SR.3
trVpp Error Detect
Standby
Check SR.l
l=Dence Pmtect Detect
WP#‘V,L
Standby
Check SR.4.5
Both l=Command
Sequence Error
Standby
Check SR.4
t-Set Block Lock-Sit Error
SRS.SR.4.SR.3 and SR.1 are only dewed by the Clear Status
Regwterccmmand in casas where multiple block lock-bits are set before
full status is checked.
If ermr is detected. clear the Status Register before attempbng
retry or omer error recovery.
Set Block Lock-&t
successful
Figure 12. Set Block Lock-Bit
Flowchart
Rev. 1.9
SHARP
LHFlGKAl
Bus
Opdh
29
Writ9
Ckr Block
Lock-Sits Setup
Wlikl
clear sbck
Lock-Sib Confirm
Read
+
Data&H
AddhX
Data-DOH
Addr=X
Status Register Data
check SR.7
1-WSM Ready
OIWSM Busy
S-W
SR.7..
Comments
Cammmd
Write FFH after the Clear Block Lock-Bits operation to
place dwice in read army mode.
O
1
FULL STATUS CHECK PROCEDURE
Read Status Register
Data&See Above)
I
Bus
Opfirthl
Device Protect Error
Command
Comments
Standby
Check SR.3
l=Vpp Error Detect
standby
Chock SR. 1
l=Devlce Protect Detect
WPiM,L
Standby
Check SR.4,5
Both I-Command
Sequence Error
Standby
Check SR.5
I-Clear Block Lock-Bits Ermr
SR.S.SR.4SR.3 and SR., are onb deared by the Clear Status
Registercommand.
If enor is detected. dear the Stabls Register bebre attempting
Clear Block Lock-Bits
Successful
Figure 13. Clear Block Lock-Bits
Flowchart
Rev-l.9
SHARP
LHFlGKAl
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP
provides
three
control
inputs
to
accommodate multiple memory connections. ThreeLine control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory
devices
have
active
outputs
while
deselected memory devices are in standby mode.
3P#
should
be connected
to the system
‘OWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 STS and Block Erase, Full Chip
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration Polling
5TS is an open drain output that should be
:onnected to Vcc b y a pullup resistor to provide a
lardware method of detecting block erase, full chip
?rase, (multi) word/byte write and block lock-bit
:onfiguration
completion.
In default
mode,
it
ransitions low after block erase, full chip erase,
multi) word/byte write or block lock-bit configuration
:ommands and returns to VOH when the WSM has
inished executing
the internal algorithm.
For
rlternate
STS pin
configurations,
see
the
>onfiguration command.
;TS can be connected to an interrupt input of the
#ystem CPU or controller. It is active at all times.
30
STS, in default mode, is also High Z when the device
is in block erase suspend (with (multi) word/byte writs
inactive), (multi) word/byte write suspend or deeF
power-down modes.
1
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transienl
peaks produced by falling and rising edges of CE#i
and OE#. Transient current magnitudes depend or
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a O.luF ceramic capacitor
connected between its Vcc and GND and between its
V,, and GND. These high-frequency, low inductance
capacitors should be placed as close as possible tc
package leads. Additionally, for every eight devices,
a 4.7uF electrolytic capacitor should be placed at the
array’s power supply connection between Vco and
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 Vpp Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V,, Power supply trace.
The V,, pin supplies’ the memory cell current for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. Use similar trace
widths and layout considerations given to the Vcc
power bus. Adequate
V,,
supply traces and
decoupling will decrease V,, voltage spikes and
overshoots.
.
2
Rev. 1.9
SHARP.
LHFlGKAl
5.5 VcC, Vpp, RP# Transitions
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed if
V,, falls outside of a valid VPPHI12/s range, Vco falls
outside of a valid VCCIR range, or RP#=V,,. If V,,
error is detected, status register bit SR.3 is set to “1”
along with SR.4 or SR.5, depending on the attempted
operation. If RP# transitions to V,, during block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration, STS(if set to RY/BY# mode)
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V,,
clear the status register.
The CUI latches commands
issued by system
software and is not altered by V,, or CE# transitions
or WSM actions. Its state is read array mode upon
Dower-up, after exit from deep power-down or after
Vcc transitions below VLKO.
\fter block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V,,
:ransitions down to V,,,,,
the CUI must be placed in
.ead array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6 Power-Up/Down
Protection
The device is designed to offer protection against
iccidental block and full chip erasure, (multi)
vordlbyte writing or block lock-bit configuration during
)ower transitions. Upon power-up, the device is
ndifferent as to which power supply (V,, or V,,)
powers-up first. Internal circuitry resets the CUI tl
read array mode at power-up.
A system designer must guard against spuriou:
writes for Vcc voltages above VLKO when V,, i:
active. Since both WE# and CE# must be low for i
command write, driving either to VI,..,will inhibit writes
The CUl’s two-step command sequence architecturt
provides added level of protection against dat:
alteration.
In-system block lock and unlock capability prevent!
inadvertent data alteration. The device is disable{
while RP#=V,, regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers mus
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatilio
increases usable battery life because data is retainec
when system power is removed.
In addition,
deep power-down
mode
ensures
extremely low power consumption even when systerr
power is applied. For example, portable computing
products and other power sensitive applications tha
use an array of devices for solid-state storage car
consume negligible power by lowering RP# to V,,
standby or sleep modes. If access is again needed
the devices can be read following the tpHav ant
tPHwL wake-up cycles required after RP# is firsi
raised to V,,. See AC CharacteristicsRead Only
and Write Operations and Figures 17, 18, 19, 20 for
more information.
Rev. 1.9
SHARP
LHF16KAl
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum
Ratings*
Operating Temperature
During Read, Erase, Write and
Block Lock-Bit Configuration . . . .. ...O”C to +7O”C(‘)
Temperature under Bias .. .. .. .. . .. .. . . -10°C to +80X
Storage Temperature .. .. . .. .. . .. .. . .. .. . .. .. -65°C to +125”C
Voltage On Any Pin
(except V,,, V,,) . .. . .. .. . .. .. .. -0.5V to Vcc+0.5V(2)
V,, Suply Voltage .. . .. . .. .. .. . .. .. .. .. . .. . .. . -0.2v to +7.ov(2)
VP, Update Voltage during
Erase, Write and
Block Lock-Bit Configuration
.. .. ..-0.2V to +7.OV(2)
32
*WARNING:
Stressing the device beyond
the
“Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only. Operation
beyond
the
“Operating
Conditions”
is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.
NOTES:
1. Operating
temperature
is for
commercial
temperature product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on Voo and VP, pins. During
transitions, this level may undershoot to -2,OV for
periods
c20ns.
Maximum
DC voltage
on
input/output pins and Vo, is Vco+0.5V which,
during transitions, may overshoot to Vcc+2.0V for
periods <20ns.
3. Output shorted for no more than one second. No
more than one output shorted at a time.
3utput Short Circuit Current . .. .. . .. . .. .. . .. .. . .. .. . 100mA(3)
5.2 Operating Conditions
Temperature and Vcr: Operating Conditions
Symbol
Td
Vcc,
Vcc:,
Parameter
Operating Temperature
Vor: Supply Voltage (2.7V-3.6V)
Vcn Supply Voltage (3.3V*O.3V)
Min.
0
2.7
3.0
Max.
+70
3.6
3.6
Unit
“C
V
v
Test Condition
Ambient Temperature
TA=+25”C, f=l MHz
Typ.
Max.
7
10
9
12
Unit
pF
pF
Condition
V,@O.OV
‘In, ,r=O.OV
i.2.1 CAPACITANCE(l)
Symbol
Parameter
C,M
Input Capacitance
cn, ,T
Output Capacitance
JOTE:
. Sampled, not 100% tested.
.
Rev. 1.9
LHFlGKAl
i.2.2 AC INPUT/OUTPUT
33
TEST CONDITIONS
AC test inputs are driven at 2.N for a Logic “1 ‘* and O.OV for a Logic
Input rise and fall times (10% to 90%) cl0 ns.
Figure 14. Transient
Input/Output
Reference
“0.” Input
timing
Waveform
begins,
and output
timing
ends,
at 1.35V.
ends,
at 1 SV.
for Vcc=2.7V-3.6V
yi-~z+l-Lq~~
‘AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic
Input rise and fall times (10% to 90%) cl0 ns.
Figure 15. Transient
Input/Output
Reference
“0.” Input
timing
Waveform
begins,
and output
timing
for VcC=3.3V*0.3V
Test Configuration
Capacitance
Test Configuration
1.3v
V~,=3.3V*O.3V,2.7V-3.6V
iN914
1
Loading Value
C, (pF)
50
i
CL Includes
Jig
Capacitance
Figure 16. Transient Equivalent
Load Circuit
Testing
.
Rev.1.9
SHARI=
LHFlGKAl
34
5.2.3 DC CHARACTERISTICS
DC Characteristics
Block Erase Full Chi
Rev. 1.9
SHARP
LHFlGKAl
DC Characteristics
IContinued
V,,=2.N
Sym.
VI,
Min. 1 Max.
Min. 1 Max.
7
7
-0.5 1 0.8
-0.5
1 0.8
V
VI,
input Low Voltaae
Input High Voltage
2.0
2.0
Vcc
+0.5
v
VOL
Output Low Voltage
3,7
0.4
v
VoHr
Output High Voltage
u-w
Output High Voltage
(CMOS)
317
3,7
VPPLK V,, Lockout Voltage during
Normal Operations
Vcc
+0.5
0.4
Unit
2.4
0.85
v,,
2.4
0.85
v,,
V
Vcc
-0.4
Vcc
-0.4
V
497
1.5
1.5
v
V,, Voltage during Write or
Erase Operations
2.7
3.6
-
-
V
V,,H,
V,, Voltage during Write or
Erase Operations
3.0
3.6
3.0
3.6
V
Vn,Hs
V,, Voltage during Write or
Erase Ooerations
5.5
4.5
I
1 2.0
5.5
v
1
1 v
VI kO 1Vcc Lockout Voltage
4.5
I
( 2.0
L
j
Vcc=VccMin.
loI =2mA
I”CC=~5C$
OH
*
Vcc=VccMin.
lo,=-2.%lA
Vcc=VccMin.
I,,=-1 OOuA
V
Vrqqrr
I
Test
Conditions
vcc=3.3v
Notes
VOH2
Parameter
I
1
1
(
IOTES:
. All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and TA=+25”C.
* ‘CCWS
and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of ICC,, or IccEs and I,,, or Iccw, respectively.
. Includes STS.
. Block erases, full chip erases, (multi) word/byte wriies and block lock-bit configurations are inhibited when
V&I,,,,,
and not guaranteed in the range between VppLk(max.) and Vpr+n(min.), between VppHt(max.) and
Vpp&min.), between VppH2(max.) and Vp&min.)
and above VppHs(max.).
. Automatic Power Savings (APS) reduces typical ICC, to 3mA at 2.7V and 3.3V Vcc in static operation.
. CMOS inputs are either Vcc+0.2V or GND+0.2V. TTL inputs are either V,, or V,,.
. Sampled, not 100% tested.
.
Rev.1.9
SHARP
LHFlGKAl
6.2.4 AC CHARACTERISTICS
NOTE:
See 3.3V V,,
tELFL
tp, fz!+
36
- READ-ONLY OPERATIONS(‘)
Read-Only Operations for notes 1 through 4.
CE# Low to BYTE# High or Low
3
5
t
ns
JOTES:
I. See AC input/Output Reference Waveform for maximum allowable input slew rate.
.
!. OE# may be delayed up to tELQv-fGLQv after the falling edge of CE# without impact on tELQv.
5. Sampled, not 100% tested.
C. See Ordering Information for device speeds (valid operational combinations).
Rev. 1.9
SHARP
LHFlGKAl
37
,
Device
Address
Selection
Address
Stable
k
OE#(G)
,
\
1::
VIH
WE#(W)
tGLa!,
tELQv l
VIL
.
kLOX
kLOXb
. . . . ...“‘*
tOI-4 --r,
-*
*
VOH
HIGH
DATA( D/Q)
Z
,,......11
VOL
tAVOV
4
l
kc
tPHOV
NOTE:
CE# is defined
as the latter
of CEo# and CE1# going
Low or the first of CE#
Figure 17. AC Waveform
or CE1# going
High.
for Read Operations
Rev. 1.9
SHARP
LHFlGKAl
38
r
Device
Address
Selection
Address
Data Valid
,,,11..111
Stable
VOH
DATA( D/Q)
PQe-DQd
HIGH
HIGH
Z
Z
VOL
NOTE:
CE# is defined
as the latter
of CEo# and CE,#
going
Low or the first of CEo# or CE#
going
High.
Figure 18. BYTE# Timing Waveforms
Rev. 1.9
SHARP
LHFlGKAl
6.2.5 AC CHARACTERISTICS
&,,,,,,,
tlJ#q,
&&jr,,
JflWl
VSI
Sym.
tnvnv
tpww,
4, w,
&, wH
- WRITE OPERATIONS(‘)
WE# Pulse Width High
WE# High to STS Going Low
Write Recovery before Read
VP,, Hold from Valid SRD, STS High Z
WP# VI,, Hold from Valid SRD, STS High Z
NOTE:
See 3.3V Vcc WE#-Controlled
30
0
0
0
2,4
2,4
1
) Write Cycle Time
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
Yetup to WE# Going High
TA=O”C to +7O”C
1 Notes
1
(
2
2
2
-3
3
VE# High
tJ&r,,
h,,,,,
ns
ns
ns
ns
ns
100
Writes for notes 1 through 5.
Vcc=3.3V*0.3V,
Versiond5)
Parameter
.,
39
I High
S Going Low
Write Recovery before Read
slid SRD, STS High Z
1VP,, Hold from V:
I \nrnll
\I
U^lrl
I-“,H
ll”l”
II urn Valid SRD, STS High Z
1 ““Tit
L
2,4
2,4
LH28F16OS3-Ll OO
1 Max.
Min.
100
1
10
50
100
100
50
50
5
5
10
30
100
0
0
0
Unit
ns
p
ns
ns
ns
ns
ns
ns
ns
ns
I
9
ns
ns
ns
ns
ns
I. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit
configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
!. Sampled, not 100% tested.
1. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
I. V,, should be held at V,,,,,z,
until determination of block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration success (SR.1/3/4/5=0).
i. See Ordering Information for device speeds (valid operational combinations).
Rev. 1.9
SHARP
LHFlGKAl
1
-o---o
2
3
40
4
5
6
hi
ADDRESSES(A)
VIL
hi
CE#(E)
VS.
- IL
VIH
OE#(G)
VIL
VIH
WE#(W)
VIL
VIH
DATA( D/Q)
VIL
High
STS(R)
VOL
WP#(S)
NOTES:
1. Vcc power-up
and standby.
2. Write erase or write setup.
3. Write erase confirm or valid address and data.
4. Automated
erase or program
delay.
5. Read status register data.
6. Write Read Array command.
7. CE# is defined as the latter of CEo# and CE,# going
Low or the first of CE.,#
Figure 19. AC Waveform
or CE,#
for WE#-Controlled
going
High.
Write Operations
.
Rev. 1.9
SHARI=
LHFlGKAl
6.2.6 ALTERNATIVE
CE#-CONTROLLED
WRITES(‘)
Vco=2.7V-3.6V,
Sym.
1
T,=O”C to +7O”C
Versions@)
Parameter
) Notes
I
II tFHnv
High
I Data Setup to CE# Going High
1Data Hold from CE# High
I
2
3
3
1
1
I
LH28F16OS3-L120
Min.
1 Max.
100
50
50
Unit
ns
ns
ns
I
NOTE:
See 3.3V V,,
I,
tfw&y
tFHWH
t&HF,
tp ,R,
tfqn,
tnWl
h&l
NOTES:
Alternative CE#-Controlled
Writes for notes 1 through 5.
Vcc=3.3V+0.3V,
Address Hc
WE# Hold
CE# Pulse Width High
CE# High to STS Going Low
Write Reco very before Read
Vpp Hold from Valid SRD, STS High Z
WP# VI,, Hold from Valid SRD, STS High Z
T,
100
1
I
2,4
24
1
I
0
0
0
II
ns
ns
ns
ns
I
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and
inactive WE# times should be measured relative to the CE# waveform. *
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A,, and D,, for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. V,, should be held at VPPH1,2,3 until determination of block erase, full chip erase, (multi) word/byte write or
block lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
1
Rev. 1.9
SHARI=
42
LHFlGKAl
ADDRESSES(A)
NOTES:
1. Vcc power-up
and standby.
2. Write erase or write setup.
3. Write erase confirm or valid address
4. Automated
erase or program delay.
5. Read status register data.
6. Write Read Array command.
7. CE# is defined as the latter of CEo#
and data.
and CE#
going
Low or the first of CEo# or CE,#
Figure 20. AC Waveform
for CE#-Controlled
going
High.
Write Operations
.
Rev. 1.9
SHARP
LHF16KAl
6.2.7 RESET OPERATIONS
High Z
STS(R)
VOL
VIH
RP#(P)
WL
(A)Reset
During
Read
Array
Mode
High Z
STS( R)
VOL
.
bLl?H
VIH
RP#(P)
VIL
-
bLPH
(B)Reset
During Block Erase, Full Chip Erase,
or Block Lock-Bit
Configuretion
(Multi)
Word/Byte
Write
VIH
I
RP#(P)
T
VIL
(C)Vcc
Power
Figure 21. AC Waveform
Up Timing
for Reset Operation
Reset AC Specifications
Symbol
tPLPH
tPLRH
b3VPH
Parameter
RP# Pulse Low Time
(If RP# is tied to Vco, this specification is
not applicable)
RP# Low to Reset during Block Erase,
Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuration
V,, at 2.7V to RP# High
Vcn at 3.OV to RP# High
Notes
V,,=2.7V
Min.
Max.
100
1,2
3
V,,=3.3V
Max.
Min.
ns
100
21.1
21.5
100
Unit
100
IJS
I
ns
NOTES:
If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration
.
operation is not executing, the reset will complete within loons.
2. A reset time, tpHQv, is required from the latter of STS going High Z or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after V,, has been in predefined range
and also has been in stable there.
1.
Rev. 1.9
SHARI=
LHFlGKAl
44
5.2.8 BLOCK ERASE, FULL CHI D ERASE, (MULTI) WORD/BYTE
LOCK-BIT CONFIGURATK IN PERFORMANCE@)
Sym.
Parameter
Word/Bvte Write Time
(using W/B write, in word
mode)
Word/Byte Write Time
(using W/B write, in byte
mode)
Word/Bvte
, Write Time
(using multi word/byte write)
Block Write Time
(using W/B write, in word
mode)
Block Write Time
(using W/B write, in byte
mode)
Block Write Time
(using multi word/byte write)
Block Erase Time
2
5.76
2
1 0.73
1
2
/
2
Set Block Lock-Bit Time
Clear Block Lock-Bits Time
Write Suspend Latency Time
to Read
Erase Suspend Latency
Time to Read
2
2
250
5.76
8.2
1 0.73
1
1 16.5
1 1.31
1 16.5
1 0.87
0.37
4.1
0.18
0.37
2
Full Chip Erase Time
1.31
WRITE AND BLOCK
4.1
0.56
10
250
0.56
8.2
2.76
/
10
0.44
180
1
ps
4.8
1
s
1 10.9
1
s
2
0.42
S
10
S
I
I
I
I
I
I
1 17.9
1 320
1 17.9
1 320
1 13.4
I
1 22.17
1 250
1 22.17
1 250
1 180
1 11s
I
I
1 13.2
I
1
I
10
10
I
I
320
1
I
s
I
) 0.56
1
1 0.56
1
1 0.42
1
I
!
I
I
I
t
I
1 7.24
1 10.2
( 7.24
1 10.2
1 6.73
1 9.48
1 ps
1 15.5
1 21.5
1 15.5
1 21.5
1 12.54
1 17.54
1 us
I
I
I
I
I
IOTE:
ice 3.3V V,, Block Erase, Full Chip Erase, (Multi) Word/Byte Write and Block Lock-Bit Configuration
x notes 1 through 3.
10
s
Performance
.
Rev. 1.5
SHARP
LHFlGKAl
45
I Word/B
Block Write Time
(using W/B write, in word mode)
2
0.72
8.2
0.43
4.8
S
Block
Time in byte mode)
(using Write
W/B write,
2
1.28
16.5
0.85
10.9
s
Block Write Time
(using multi word/byte write)
s-l
L
I\U.JWn)E
“1
0.18
2
S
Block Erase Time
2
0.55
10
0.41
10
S
17.6
320
13.1
320
S
2
21.75
250
12.95
180
IJS
2
0.55
10
0.41
10
S
rWHRH1 Write Susoend Latencv Time to Read
7.1
10
6.6
9.3
US
pHRH2
15.2
21.1
12.3
17.2
IJS
t
b”,wHQV*
I
twHQvs
Full Chip Erase Time
Set Block Lock-Bit Time
t
tFHO”d
WHQV4 Clear Block Lock-Bits Time
Erase Suspend Latency Time to Read
+.
FHFlH7
NOTES:
1. Typical values measured at TA=+25”C and nominal voltages. Assumes corresponding
set. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
block lock-bits are not
Rev. 1.9
SHARP
LHFlGKAl
46
ADDITIONAL INFORMATION
1 Ordering Information
Product line designator for all SHARP Flash products
~~~~1.6101S~~~~~~SI-/L~1~0~
U
Device Density
160 = 16-Mbit PArchitecture
S = Regular Block
Power Supply Type
3 = Smart 3 Technology
Operating Temperature
Blank = 0°C - +7O”C Ii
H = -40°C - +85”C
$tion
1
Order Code
LH28F160S3NS-LlO
w
Access Speed (ns)
10:lOOns (3.3V), 120ns (2.7V)
13: 130ns (3.3V), 150ns (2.7V)
Package
T = 56-Lead TSOP
R = 56-Lead TSOP(Reverse Bend)
NS = 56-Lead SSOP
B = 64-Ball CSP
D = 64-Lead SDIP
Valid Operational Combinations
v~~=3.3v*O.3v
V,,=2.7V-3.6V
5OpF load,
5OpF load,
1.5V I/O Levels
1.35V l/O Levels
LH28F16OS3-Ll OO
LH28F16OS3-L120
Rev. 1.9
SHARP
47
8 Package and packing specification
I
lAorage
Conditions.
I-1Storage conditions required before opening the dry packing.
* Normal temperature
: 5-40°C
Normal humidity : 80% R.H. max.
l
1-2.Storage conditions required after opening the dry packing.
In order to prevent moisture absorption after opening, ensure the following
storage
conditions apply:
(1) Storage conditions for one-time soldering. (Convection reflow, IWConvection reflow,
V.P.S., or Manual soldering. >
* Temperature : 5-25°C
* Humidity : 60% R .H. max.
Period : 72 hours max. after opening.
(2) Storage conditions for two-time soldering. (Convection reflow, IRKonvection reflow.)
a. Storage conditions following opening and prior to performing the 1st reflow.
Temperature : 5-25°C.
Humidity : 60% R.H. max.
* Period : 72 hours max. after opening.
b. Storage conditions following completion of the 1st reflow and prior to performing
the 2nd reflow.
* Temperature : 5-25”c,
* Humidity : 60 % R .H. max.
* Period : 72 hours max. after completion of the 1st reflow.
l
l
l
1-3.Temporai-y storage after opening.
To restore the devices before soldering, do so only once and use a dry box or place desiccant
(with a blue humidity indicator) with the devices and perform dry packing again using
heat-sealing.
The storage period, temperature and humidity must be as follows :
(1) Storage temperature
and humidity.
Z 1 : External atmosphere temperature and humidity of the dry packing.
Re-openingb
X2---,
Mounting
First opening+
Xl---+
Re-sealing +
Y __)
Zl Temperature : 5-4Ocl
Humidity : 80%R.H. maxi
5-25°C
60%R.H. max.
II
II
%1 5-40°C
80%R.H. max.
(2) Storage period.
- Xl +X2 : Refer to Section l-2(1) and (2)a , depending
*Y
: Two weeks max.
A
II
I
I
5-25°C
60%R.H. max.
on the mounting
method.
0
f
I
I’
*
SHARP
46
LHFlGKAl
2. Baking Condition.
(1) Situations requiring baking before mounting.
Storage conditions exceed the limits specified in Section l-2 or l-3.
Humidity indicator in the desiccant was already pink when opened.
( Also for re-opening.)
(2) Recommended baking conditions.
Baking temperature and period :
120°C for 16-24 hours.
* The above baking conditions apply since the trays are heat-resistant.
(3) Storage after baking.
* After baking, store the devices in the environment specified in Section 1-2 and mount
immediately.
l
l
l
3Surface mount conditions.
The following soldering condition are recommended to ensure device quality.
3- 1 .Soldering.
(1) Convection reflow or WConvection.
(one-time soldering only)
* Temperature and period :
Peak temperature of 240°C max., above 230°C for 15 sec. max.
Above 200°C for 50 sec. max.
Preheat temperature of 140- 160°C for 90f 30 sec.
Temperature increase rate of lb3”C/sec.
* Measuring point : IC package surface.
* Temperature profile :
240°C max.
160°C
.
Temp. increase lbS”C/sec.
Time
SHARP
49
LHFIGKAl
(2) Convection reflow or IFUConvection. (two-time soldering only)
* Temperature and period :
Peak temperature of 230°C max.
Above 200°C for 50 sec. max.
Preheat temperature of 140- 160°C for 90* 30 sec.
Temperature increase rate of l-3”C/sec.
- Measuring point : IC package surface.
* Temperature profile :
230°C max.
Temp. increase l--S”C/sec.
Time
(3) V.P.S.( one-time soldering only >
Temperature and period :
Peak temperature of 215°C max., above 200°C for 40 sec. max.
Preheat temperature of 140- 160°C for 90+ 30 sec.
Temperature increase rate of 1&4”C/sec.
- Measuring point : IC package surface.
* Temperature profile
l
215°C max.
k .._.____.____.___
. Preheating
.
( .90 .+. 30 .sec.)
.
.
......... .. .?
’
Time
Temp. increase
l-4YZ/sec.
I
/
SHARP
LHFl6KAI
(4) Manual soldering ( soldering iron ) ( one-time soldering only >
Soldering iron should only touch the IC’s outer leads.
- Temperature and period :
350°C max. for 3 sec. I pin max., or 260°C max. for 10 sec. I pin max.
(Soldering iron should only touch the It’s outer leads.)
Measuring point : Soldering iron tip.
l
4. Condition for removal of residual flax.
(1) Ultrasonic washing power : 25 watts / liter max.
(2) Washing time : Total 1 minute max.
(3) Solvent temperature
: 15-40°C
50
SHARP
51
LHFlGKAl
5. Package outline spec.i&ation.
Refer to the attached drawing.
6. Markings.
6-l.Marking
details. (The information on the package should be given as follows.)
( 1) Product name
: LH28F160S3NS-L.10
(2) Company name
: SHARP
(3) Date code
(Example) W
WW
* Denotes the production ref. code (l-3 digits).
Denotes the production week. (01 * 02 * 52 53)
Denotes the production year. (Last two digits of the year.)
G
(4) “JAPAN” indicates the country of origin.
6-2.Marking layout.
The layout is shown in the attached drawing.
(However, this layout does not specify the size of the marking character and marking position.)
l
l
Sl-tARP
52
LH-FIGKAI
SEE DETAIL
DETAIL
A
A
"
.
?
&
‘J - F6EB@
!
LEAD FINISH
I
5%
i
AME i
i
l\i9+%
0. 8 f0.
y,
TIN-LEAD PLATING
SSOPO56-P-0600
I0
*4il
bRAWING NO. j AA2021
UNIT
i
i
mm
15
.
1I
‘I - FW@
I
cu
LEAD MATERIAL
G&5 ~~JZ5=~9/~~9=-5?9l-%~~i~,
/X'JQ
-23E7kt~BcD~T~~
NOTEPlastic body dimensions do not include burr
of resin.
2000080E
SHARP
T-9 L-r79 bEI
Marking layout
LH28F160S3NS-LlO
SHARP
JAPAN
YYWWxxx
0
ii
1 Pin
-
SHARP
LHFI6KAl
7.Packing Specifications (Dry packing for surface mount packages.)
7- l.Packing materials.
Material name
Inner carton
I
nay
Upper cover tray
Laminated aluminum
) Material specifications
1 Cardboard
(500 devices / inner carton
! max. >
f Conductive plastic (50 devices I tray)
j Conductive plastic (1 tray / inner carton)
f Aluminum polyethylene
1 Purpose
j Packing the devices.
j (10 trays I inner carton)
) Securing the devices.
/ Securing the devices.
i Keeping the devices dry.
j Silica gel
1 Paper
j Keeping the devices dry.
I Indicates part number,
1 quantity, and packed date.
i Securing the devices.
1 Outer packing.
bag
Desiccant
Label
PP band
Outer carton
I
1 Polypropylene
(3 pcs. / inner carton >
/ Cardboard
(2000 devices / outer carton
II max. )
..
( Devices must be placed on the tray in the same direction.)
7-2.0utline
Refer to
7-3.0utline
Refer to
I
dimension of tray.
the attached drawing.
dimension of carton.
the attached drawing.
8. Precautions for use.
(1)
Opening must be done on an anti-ESD treated workbench.
All workers must also have undergone anti-ESD treatment.
(2)
The trays have undergone either conductive or anti-ESD treatment.
If another tray is used, make sure it has also undergone conductive or anti-ESD
treatment.
(3)
The devices should be mounted the devices within one year of the date of delivery.
200008OI i
.
3 IS. 8 !I:3
e
18.
r
d
_a 18.4.
31.0*0.3*9=279.0*0.5
m
m
m
m
m
t
m
A
h-%3-
SHARP
56
\
Outer
carton
label
Two
6%
ME
DRAWING
i
i
l-L-f!%
a%&&
Packing specifications
,I
I &CL i
UNIT i mm
NO. [ BJ433
L X WX H
Inner carton - Outer dimensions : 335X150X80
Outer carton - Outer dimensions : 340X310X175
*tkt%a%Q6~~7mosE3
#ii*
XRBS;73~%&D%G.
NOTE There is a possibility
different
from this
specification
when the number of shipments
is fractions.
rows