LR38266 Digital Signal Processor for Color CCD Cameras LR38266 DESCRIPTION The LR38266 is a CMOS digital signal processor for color CCD camera systems of 270 k/320 k/410 k/470 k-pixel CCD with complementary color filters. FEATURES • Designed for 270 k/320 k/410 k/470 k color CCDs with Mg, G, Cy, and Ye complementary color filters • Switchable between NTSC and PAL modes • External performance control • Variable GAMMA and KNEE response • 8 to 10-bit digital input • Analog Y&C output by built-in 8-bit 2 ch DA converter • Switchable between Y, U/V (16 bits) and U/Y/V/Y (8 bits) digital video output • Line-lock and external lock function • CPU interface input/output • Accumulator to control auto exposure and auto white balance • Single +3.3 V power supply • Package : 100-pin LQFP (LQFP100-P-1414) 0.5 mm pin-pitch In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38266 PIN CONNECTIONS TOP VIEW 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 52 25 51 50 53 24 49 54 23 48 55 22 47 56 21 46 57 20 45 58 19 44 59 18 43 60 17 42 61 16 41 62 15 40 63 14 39 64 13 38 65 12 37 66 11 36 67 10 35 68 9 34 69 8 33 70 7 32 71 6 31 72 5 30 73 4 29 3 28 74 27 75 2 26 1 VRI GND FI CBLK CSYO VDD GND TST1 TST2 TST3 TST4 DCK2 GND CO0 CO1 CO2 CO3 GND VDD CO4 CO5 CO6 CO7 TST5 TST6 ACL ADI0 ADI1 ADI2 ADI3 ADI4 VDD GND ADI5 ADI6 ADI7 ADI8 ADI9 GND VDD OCP1 CSYN GND CKI1 CKI2 GND CKI0 GND HP VD 99 100 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND VDD MCO1 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 VDD GND SDI SCK SLDI GND ENC 100-PIN LQFP (LQFP100-P-1414) 2 HD1 DOC EOO VDD GND DCK1 YO7 YO6 YO5 YO4 GND VDD YO3 YO2 YO1 YO0 VREF DA GND DA VDD IREF2 IREF1 VB2 VB1 CENCO YENCO LR38266 BLOCK DIAGRAM YOUT [7 : 0] ADI [9 : 0] OBCP 1H, 2H DELAY LINE LUMINANCE SIGNAL PROCESS DAC YENCO, VB1 CKI0, CKI1 VREF CKI2, ENC IREF1, IREF2 ADD [6 : 0] COUT [7 : 0] SDI, SCK, SLDI DATA [7 : 0] MICROCOMPUTER INTERFACE COLOR SIGNAL PROCESS SSG DAC CENCO, VB2 HP, CSYO, HD1 DCK1, DCK2 CSYN, OCP1, VD, FI CBLK, EOO, VRI DOC 3 LR38266 PIN DESCRIPTION PIN NO. SYMBOL I/O POLARITY DESCRIPTION All reset input. The internal circuit is initialized at power-on with a capacitor of 1 ACL ICU 2 ADI0 IC 3 4 ADI1 ADI2 IC IC ADI0 to ADI9 are digital signal inputs. ADI0 is LSB. 5 6 ADI3 ADI4 IC IC ADI9 is MSB. 7 VDD – Supply of +3.3 V power. 8 9 GND – A grounding pin. ADI5 IC 10 11 ADI6 ADI7 IC IC ADI0 to ADI9 are digital signal inputs. ADI0 is LSB. 12 ADI8 IC ADI9 is MSB. 13 14 ADI9 GND IC – A grounding pin. 15 16 VDD OCP1 – O Supply of +3.3 V power. Optical black clamp pulse output. 0.01 µF. 17 CSYNC O Composite synchronous pulse output for analog video output. 18 GND – A grounding pin. Clock input. The frequency is below for each CCD. 19 CKI1 IC 270 k, 410 k CCD : 14.31818 MHz 320 k, 470 k CCD : 14.1875 MHz Clock input. The frequency is below for each CCD. 20 CKI2 IC 21 GND – 22 CKI0 IC 270 k CCD : 9.5454 MHz 410 k CCD : 14.3181 MHz 320 k CCD : 9.4583 MHz 470 k CCD : 14.1875 MHz A grounding pin. Clock input. The frequency is below for each CCD. 270 k, 410 k CCD : 28.6363 MHz 320 k, 470 k CCD : 28.3750 MHz 23 GND – A grounding pin. 24 25 HP VD O O Horizontal drive pulse output. Vertical drive pulse output. 26 VRI ICS Vertical reset input. Built-in vertical counter is reset by a low-input of more than one horizontal period. 27 GND – A grounding pin. 28 29 FI CBLK O O Field index pulse output. Composite blanking pulse output. 30 CSYO O Composite synchronous pulse output. Output timing is variable by output mode. 31 VDD – Supply of +3.3 V power. 32 GND – A grounding pin. 4 LR38266 PIN NO. SYMBOL 33 TST1 I/O ICD POLARITY DESCRIPTION Test input. Connected to low or open. 34 TST2 ICD Test input. Connected to low or open. 35 36 TST3 TST4 ICD ICD Test input. Connected to low or open. Test input. Connected to low or open. 37 38 DCK2 GND O – 39 40 CO0 TO CO1 TO 41 CO2 TO 42 43 CO3 GND TO – 44 45 VDD CO4 – TO 46 CO5 TO 47 48 CO6 CO7 TO TO 49 50 TST5 TST6 ICD ICD Test input. Connected to low or open. Test input. Connected to low or open. 51 YENCO DAO Analog Y signal output. 52 CENCO DAO 53 VB1 DAO Analog C signal output. Bias voltage output of built-in DA converter, connected to GND through a Clock output for digital COUT. A grounding pin. 8-bit digital color signal output. CO0 is LSB. CO7 is MSB. A grounding pin. Supply of +3.3 V power. 8-bit digital color signal output. CO0 is LSB. CO7 is MSB. capacitor. Bias voltage output of built-in DA converter, connected to GND through a 54 VB2 DAO 55 IREF1 DAO Bias current output of built-in DA converter, connected to GND through a resistor. 56 IREF2 DAO Bias current output of built-in DA converter, connected to GND through a resistor. 57 58 DA VDD DA GND – – 59 VREF DAI 60 61 YO0 TO YO1 TO 62 63 YO2 YO3 TO TO 64 VDD – 65 66 GND YO4 – TO 67 YO5 68 YO6 TO TO 69 YO7 TO capacitor. Supply of +3.3 V power input for built-in DA converter. A grounding pin for built-in DA converter. Bias voltage input of built-in DA converter, connected to +1.0 V power supply. Y digital outputs. YO0 is LSB. YO7 is MSB. Supply of +3.3 V power. A grounding pin. Y digital outputs. YO0 is LSB. YO7 is MSB. 5 LR38266 PIN NO. SYMBOL 70 DCK1 I/O O POLARITY DESCRIPTION Clock output for YO output. 71 GND – A grounding pin. 72 VDD – Supply of +3.3 V power. 73 EOO XTO Phase detector output comparing internal HD and HD1. 74 75 DOC HD1 ICD O Control input of YO and CO. H level sets both YO and CO high-impedance. Horizontal drive pulse generated from ENC (pin 76). 76 ENC IC Clock input to encode color signal. Internal Synchronous mode : CKI2 77 GND – A grounding pin. 78 SLDI IC Data input to set each coefficient of DSP. 79 80 SCK SDI IC IC Clock pulse input to set SLDI data to DSP. Timing pulse input to set SLDI data to DSP. Line Lock mode : same as CCD clock from outside or 4 fSC. 81 GND – A grounding pin. 82 VDD Supply of +3.3 V power. 83 ADD0 – IC 84 85 ADD1 ADD2 IC IC Address input to select an output data of DATA pins used in auto white 86 ADD3 IC balance and auto exposure. 87 88 ADD4 ADD5 IC IC For details, see "Data Interface Timing". 89 ADD6 IC 90 MCO1 O 91 92 VDD GND – – 93 94 DATA0 DATA1 O O 95 96 DATA2 DATA3 O O 97 DATA4 O 98 99 DATA5 DATA6 O O 100 DATA7 O IC ICU ICD ICS : : : : Control output to update internal data stored in DSP register. Data is updated at the rising edge of MCO1. Supply of +3.3 V power. A grounding pin. Data output to control auto white balance and auto exposure. Data of address set by ADD inputs is output. For details, see "Data Interface Timing". Input pin (CMOS level) Input pin (CMOS level with pull-up resistor) Input pin (CMOS level with pull-down resistor) Input pin (CMOS schmitt-trigger level with pulldown resistor) DAI O TO XTO DAO 6 : : : : : Input pin for DA converter Output pin Tri-state output pin Tri-state output pin DA converter output pin LR38266 INTERNAL COEFFICIENT TABLE ADDRESS NAME 00h 01h STB_DA 02h 03h 04h 06h BIT CONTENTS OUTPUT2 6 5 Not used Standby of DA converter Output format option bit 4 = 0 OUTPUT1 TVMD 4 3 Output format option TV format option bit 4 = 1 Y, U/V (bit 5 = 0) Prohibited (bit 5 = 1) 0 : NTSC 1 : PAL TYPE2 2 CCD option TYPE1 1 CCD option bit 2 = 0 bit 2 = 1 bit 1 = 0 270 k/320 k with mirror Prohibited MIR ADTI1 0 6 Image type option 0 : Normal Input data is delayed by 1 clock cycle 0 : Not delayed 1 : Delayed ADTI2 APTVC 5 4 The clock type to input the data Vertical edge enhancement 0 : Non-inverted 0 : ON 1 : Inverted 1 : OFF APTHC 3 Horizontal edge enhancement 0 : ON 1 : OFF CKIL MUTE_D 2 1 Color killer function Muting digital signal outputs 0 : ON 0 : OFF 1 : OFF 1 : ON MUTE_A 0 4 Muting analog signal outputs The polarity of EOO output 0 : OFF 0 : Normal 1 : ON EOOCTRL INVSP 3 The polarity of SP1, SP2 0 : Normal HGCO INTL 2 1 The polarity of HG Interlace/Non-Interlace 0 : Normal 0 : Interlace EX_SXB TESYL 0 5 Standby of EOO function Set YL zero in color processing 0 : Standby 0 : OFF K1 4 Prohibited to change 0 : Should be kept as is RAM_ST SEL_UV 2 1 Standby of delay lines The option of U/V sequence 0 : OFF 0 : Normal SEL_RB 0 CSYNCVARI 8 bits The option of R/B sequence 0 : Normal Position tuning of CSYNC with the range from +8 clock to –7 clock of CKI1. 1 : Standby Y/C (bit 5 = 0) U/Y/V/Y (bit 5 = 1) bit 1 = 1 270 k/320 k 07h Upper 4 bits : CSYNC, Lower 4 bits : CSYO CBLKBALI 8 bits Position tuning of CBLK with the ditto range. 08h CBK_Y 7 CBK_Y 6 CBLK_C 5 CBLK_C 4 CBLK_UV 3 CBLK_UV 2 BFVARI 1 BFVARI 0 The position tuning of color burst signal by CKI2 clock 7 1 : ON 1 : ON bit 7 = 0 bit 7 = 1 –1 clock –1 clock bit 5 = 0 No tune bit 5 = 1 –1 clock 1 clock –1 clock bit 3 = 0 No tune bit 3 = 1 –1 clock bit 2 = 1 1 clock bit 1 = 0 –1 clock bit 1 = 1 bit 0 = 0 No tune –1 clock bit 0 = 1 1 clock –1 clock The position tuning of modulated C-CBLK by bit 4 = 0 CKI2 clock bit 4 = 1 CKI2 clock 1 : Mirror No tune 1 clock The position tuning of Y-CBLK by CKI2 clock bit 6 = 0 bit 6 = 1 The position tuning of baseband C-CBLK by 410 k/470 k bit 2 = 0 LR38266 ADDRESS NAME 11h CSP_R1 12h 13h BIT CONTENTS 8 bits Coefficient to extract red color component CSP_B1 8 bits Coefficient to extract blue color component CSP_R2 CSP_B2 7 bits Coefficient to tune the base level of red signal 7 bits Coefficient to tune the base level of blue signal CB_R1 CB_R2 Coefficient of the black balance of red signal 6 bits (15h) MSB : sign, other 5 bits : upper 5 bits of coefficient 8 bits (16h) lower 8 bits of coefficient CB_B1 6 bits CB_B2 8 bits 19h WB_R1 1 bit 1Ah WB_R2 8 bits (19h) MSB of coefficient 1Bh WB_B1 1 bit 1Ch WB_B2 8 bits (1Bh) MSB of coefficient 1Dh 1Eh MAT R – Y 6 bits Coefficient of R – Y matrix MAT B – Y 6 bits Coefficient of B – Y matrix 1Fh 20h GA R – Y 6 bits Coefficient of R – Y gain GA B – Y 6 bits Coefficient of B – Y gain 21h ENC_TI 3 The clock type of encoder input 0 : Non-Inverted 1 : Inverted L_fsc MO_ENC 2 1 Latched by fsc clock before encoding Encoding phase of PAL 0 : Latched 0 : 4 phases 1 : Non-latched 1 : 16/5 phases MUTE_E 0 Muting color signal at encoder 0 : Normal 1 : Muting 14h 15h 16h 17h 18h Coefficient of the black balance of blue signal (17h) MSB : sign, other 5 bits : upper 5 bits of coefficient (18h) lower 8 bits of coefficient Upper coefficient to make white balance of red signal (1Ah) lower 8 bits Upper coefficient to make white balance of blue signal (1Ch) lower 8 bits (MSB) sign bit (MSB) sign bit 22h BAS R – Y 8 bits Coefficient of color burst level at R – Y (MSB) sign bit 23h 24h BAS B – Y 8 bits Coefficient of color burst level at B – Y (MSB) sign bit 25h WBA_IP WBA_IM 8 bits Positive range of white color signal at I-axis 8 bits Negative range of white color signal at I-axis 26h WBA_QP 8 bits Positive range of white color signal at Q-axis 27h WBA_QM 8 bits Negative range of white color signal at Q-axis 28h 29h I/Q or R – Y/B – Y WBA_SEL 2 bits Option of color signal type WB_HCL 8 bits Limiter of AWB function at higher luminance level 2Ah WB_LCL 2Bh 2Ch CKI_HCL 8 bits Color suppression point at higher luminance level CKI_LCL 8 bits Color suppression point at lower luminance level 2Dh Luminance level to suppress color signal CKI_HLGA 8 bits Upper 4 bits : higher luminance level 8 bits Limiter of AWB function at lower luminance level Lower 4 bits : lower luminance level 8 LR38266 ADDRESS 2Eh NAME BIT HT_SIG 6 HT_1 5 HT_0 4 LT_SIG 2 LT_1 1 LT_0 0 CONTENTS bit 6, bit 5, bit 4 000 : No tuning Color killer timing at higher luminance 001 1 clock cycle delay 010, 011 100, 101, 110 2 clock cycles delay Color killer timing at lower luminance 010, 011 100, 101, 110 2 clock cycles delay 2 clock cycles advance 111 1 clock cycle advance 2Fh CKI_HECL 8 bits Horizontal aperture level to suppress color signal 30h 31h CKI_VECL 8 bits Vertical aperture level to suppress color signal Aperture level to suppress color signal CKI_EGA 8 bits Upper 4 bits : vertical aperture level SEL_ESFT 7 Lower 4 bits : horizontal aperture level Level of edge signal 32h VET_SIG 6 VET_1 5 0 : 1/4 times 4 HET_SIG 2 HET_1 1 HET_0 0 Color killer timing at vertical transient portion 010, 011 111 Color killer timing at horizontal transient portion 33h 34h CKI_LEV 5 bits Level to suppress color signal NSUP_R – Y 8 bits Coring level of R – Y signal 35h NSUP_B – Y 8 bits Coring level of B – Y signal C_NE1 2 The polarity of color signal 36h 37h 38h C_NE2 1 BLK_CTRL 0 1 : 1 time bit 6, bit 5, bit 4 000 : No tuning 001 1 clock cycle delay 100, 101, 110 VET_0 2 clock cycles advance 111 1 clock cycle advance bit 2, bit 1, bit 0 000 : No tuning 001 1 clock cycle delay 39h YL_AMP 40h 41h CGAM-A1 8 bits 1st input range of color gamma correction CGAM-A2 8 bits 2nd input range of color gamma correction 8 bits YL signal level to make R – Y and B – Y 42h 43h CGAM-A3 8 bits 3rd input range of color gamma correction CGAM-A4 8 bits 4th input range of color gamma correction 44h CGAM-A5 8 bits 5th input range of color gamma correction 9 2 clock cycles advance 1 clock cycle advance bit 2, bit 1, bit 0 000 : No tuning 001 1 clock cycle delay 010, 011 2 clock cycles delay 100, 101, 110 111 2 clock cycles advance 1 clock cycle advance 0 : Normal The polarity of color signal at gamma output 0 : Normal CBLK availability at output Base level of YL signal YL_SFT1 2 bits (37h) Upper 2 bits of coefficient YL_SFT2 8 bits (38h) Lower 8 bits of coefficient 2 clock cycles delay 0 : ON 1 : Inverted 1 : Inverted 1 : OFF LR38266 ADDRESS NAME BIT CONTENTS 45h CGAM-A6 8 bits 6th input range of color gamma correction 46h CGAM-A7 8 bits 7th input range of color gamma correction 47h CGAM-A8 8 bits 8th input range of color gamma correction 48h CGAM-A9 8 bits 9th input range of color gamma correction 49h 4Ah CGAM-P1 8 bits Offset of 1st straight line at color gamma correction 4Bh 4Ch CGAM-P3 8 bits Offset of 3rd straight line at color gamma correction CGAM-P4 8 bits Offset of 4th straight line at color gamma correction 4Dh CGAM-P5 8 bits Offset of 5th straight line at color gamma correction 4Eh 4Fh CGAM-P6 8 bits Offset of 6th straight line at color gamma correction CGAM-P7 8 bits Offset of 7th straight line at color gamma correction 50h 51h CGAM-P8 8 bits Offset of 8th straight line at color gamma correction CGAM-P9 8 bits Offset of 9th straight line at color gamma correction CGAM-P2 8 bits Offset of 2nd straight line at color gamma correction 52h CGAM-P10 8 bits Offset of 10th straight line at color gamma correction 53h 54h CGAM-F 1 bit Polarity of color gamma correction 0:+ CGAM-S1 8 bits Slope of 1st straight line at color gamma correction 55h 56h CGAM-S2 8 bits Slope of 2nd straight line at color gamma correction CGAM-S3 8 bits Slope of 3rd straight line at color gamma correction 57h 58h CGAM-S4 8 bits Slope of 4th straight line at color gamma correction 59h CGAM-S5 8 bits Slope of 5th straight line at color gamma correction CGAM-S6 8 bits Slope of 6th straight line at color gamma correction 5Ah 5Bh CGAM-S7 8 bits Slope of 7th straight line at color gamma correction CGAM-S8 8 bits Slope of 8th straight line at color gamma correction 5Ch 5Dh CGAM-S9 8 bits Slope of 9th straight line at color gamma correction 60h CGAM-S10 8 bits Slope of 10th straight line at color gamma correction SETUP 6 bits Set up level of luminance signal 61h 62h APT_HGA 5 bits Horizontal aperture gain APT_HCL 7 bits Coring level of horizontal aperture signal 63h 64h APT_VGA 5 bits Vertical aperture gain APT_VCL 7 bits Coring level of vertical aperture signal 65h 66h 67h Not used VARI_MASK 4 bits Position to erase color signal by luminance mask signal 6ADV 4 1 : 6 clocks advance of luminance signal 0 : No variation 8ADV 4DLY 3 2 1 : 8 clocks advance of luminance signal 1 : 4 clocks delay of luminance signal 0 : No variation 0 : No variation 1 1 : 2 clocks delay of luminance signal 2DLY 68h 1DLY HVARI 0 1 : 1 clock delay of luminance signal 2 bits Position of horizontal aperture signal 10 0 : No variation 0 : No variation 1:– LR38266 ADDRESS NAME 69h Y_MUTE BIT 3 CONTENTS Muting analog luminance signal output 0 : Normal 1 : Muting CBLK_OFF 2 CBLK availability for luminance signal 0 : ON 1 : OFF SEL_BLK Y_NEGA 1 0 Pedestal level of luminance signal The polarity of luminance signal 0 : 16th step 0 : Normal 1 : 0 step 1 : Inverted 6Ah 6Bh Y_NESFT 6Ch 6Dh MASK_NE 8 bits Masking level of luminance signal Not used 6Eh 8 bits Base level of luminance signal Y_NEAMP 8 bits Luminance signal level Not used 6Fh 70h Not used CGAM-A1 8 bits 1st input range of color gamma correction 71h 72h CGAM-A2 8 bits 2nd input range of color gamma correction CGAM-A3 8 bits 3rd input range of color gamma correction 73h CGAM-A4 8 bits 4th input range of color gamma correction 74h 75h CGAM-A5 8 bits 5th input range of color gamma correction CGAM-A6 8 bits 6th input range of color gamma correction 76h 77h CGAM-A7 8 bits 7th input range of color gamma correction CGAM-A8 8 bits 8th input range of color gamma correction 78h 79h CGAM-A9 8 bits 9th input range of color gamma correction 7Ah CGAM-P1 8 bits Offset of 1st straight line at color gamma correction CGAM-P2 8 bits Offset of 2nd straight line at color gamma correction 7Bh 7Ch CGAM-P3 8 bits Offset of 3rd straight line at color gamma correction CGAM-P4 8 bits Offset of 4th straight line at color gamma correction 7Dh 7Eh CGAM-P5 8 bits Offset of 5th straight line at color gamma correction 7Fh CGAM-P6 8 bits Offset of 6th straight line at color gamma correction CGAM-P7 8 bits Offset of 7th straight line at color gamma correction 80h 81h CGAM-P8 8 bits Offset of 8th straight line at color gamma correction CGAM-P9 8 bits Offset of 9th straight line at color gamma correction 82h 83h CGAM-P10 8 bits Offset of 10th straight line at color gamma correction 0:+ CGAM-F 1 bit Polarity of color gamma correction 84h CGAM-S1 8 bits Slope of 1st straight line at color gamma correction 85h 86h CGAM-S2 8 bits Slope of 2nd straight line at color gamma correction CGAM-S3 8 bits Slope of 3rd straight line at color gamma correction 87h 88h CGAM-S4 8 bits Slope of 4th straight line at color gamma correction CGAM-S5 8 bits Slope of 5th straight line at color gamma correction 89h CGAM-S6 8 bits Slope of 6th straight line at color gamma correction 8Ah 8Bh CGAM-S7 8 bits Slope of 7th straight line at color gamma correction CGAM-S8 8 bits Slope of 8th straight line at color gamma correction 8Ch 8Dh CGAM-S9 8 bits Slope of 9th straight line at color gamma correction CGAM-S10 8 bits Slope of 10th straight line at color gamma correction 8Eh Not used 11 1:– LR38266 ADDRESS 8Fh NAME BIT A0h The option of white balance data equation SEL_WBD 7 PEAK4_8 6 PEAHA_H A1h A2h A3h CONTENTS Not used 5 0 : Accumulated data/Image area 1 : Accumulated data/Number of data The option to detect peak level to control the exposure 0 : Accumulated data of 4 pixels 1 : Accumulated data of 8 pixels The area in horizontal to detect peak level to control the exposure 0 : OFF 1 : ON PEAKA_V 4 The area in vertical to detect peak level to control the exposure 0 : OFF 1 : ON I_WBA_H 3 The area in horizontal to detect average level to control both the exposure and white balance 0 : OFF 1 : ON I_WBA_V 2 MASK_H 1 The area in vertical to detect average level to control both the exposure and white balance Horizontal mask signal availability 0 : OFF 0 : OFF 1 : ON 1 : ON MASK_V 0 Vertical mask signal availability 0 : OFF HMSKF_U 2 bits Upper 2 bits of starting point to mask in horizontal 1 : ON HMSKF_L 8 bits Lower 8 bits of starting point to mask in horizontal A4h HMSKR_U 2 bits Upper 2 bits of ending point to mask in horizontal HMSKR_L 8 bits Lower 8 bits of ending point to mask in horizontal A5h A7h VMSKF_U 1 bit Upper 1 bit of starting point to mask in vertical VMSKF_L 8 bits Lower 8 bits of starting point to mask in vertical A8h A9h VMSKR_U 1 bit Upper 1 bit of ending point to mask in vertical VMSKR_L 8 bits Lower 8 bits of ending point to mask in vertical 12 LR38266 OUTPUT DATA Output Data Table ADDRESS NAME BIT CONTENTS 00 to 07h IRIS-1-1 to 8 8 bits Average data to control exposure 08 to 0Fh IRIS-2-1 to 8 8 bits Average data to control exposure 10 to 17h IRIS-3-1 to 8 8 bits Average data to control exposure 18 to 1Fh IRIS-4-1 to 8 8 bits Average data to control exposure 20 to 27h IRIS-5-1 to 8 8 bits Average data to control exposure 28 to 2Fh IRIS-6-1 to 8 8 bits Average data to control exposure 30 to 37h IRIS-7-1 to 8 8 bits Average data to control exposure 38 to 3Fh IRIS-8-1 to 8 8 bits Average data to control exposure 40 to 43h AWBI-1-1 to 4 8 bits Average data of I/R – Y axis to control auto white balance 44 to 47h AWBI-2-1 to 4 8 bits 48 to 4Bh AWBI-3-1 to 4 8 bits 4C to 4Fh AWBI-4-1 to 4 8 bits 50 to 53h AWBQ-1-1 to 4 8 bits 54 to 57h AWBQ-2-1 to 4 8 bits 58 to 5Bh AWBQ-3-1 to 4 8 bits 5C to 5Fh AWBQ-4-1 to 4 8 bits 60h Average data of I/R – Y axis to control auto white balance Average data of Q/B – Y axis to control auto white balance Average data of Q/B – Y axis to control auto white balance 61h H_PEAK L_PEAK 8 bits Maximum luminance signal out of 64 blocks 8 bits Minimum luminance signal out of 64 blocks 62h 63h OB_DATA 8 bits Average data of optical pixels C1_OB_R 8 bits Average data of optical pixels for Mg + Ye 64h C3_OB_B 8 bits Average data of optical pixels for Mg + Cy 13 LR38266 Position of Each Output on Image Screen (1) Luminance Signal Data to Control Exposure Left-top Side of Image IRIS-1-1 IRIS-1-2 IRIS-1-3 IRIS-1-4 IRIS-1-5 IRIS-1-6 IRIS-1-7 IRIS-1-8 IRIS-2-1 IRIS-3-1 IRIS-2-2 IRIS-3-2 IRIS-2-3 IRIS-3-3 IRIS-2-4 IRIS-3-4 IRIS-2-5 IRIS-3-5 IRIS-2-6 IRIS-3-6 IRIS-2-7 IRIS-3-7 IRIS-2-8 IRIS-3-8 IRIS-4-1 IRIS-5-1 IRIS-4-2 IRIS-4-3 IRIS-5-2 IRIS-5-3 IRIS-4-4 IRIS-5-4 IRIS-4-5 IRIS-5-5 IRIS-4-6 IRIS-5-6 IRIS-4-7 IRIS-5-7 IRIS-4-8 IRIS-5-8 IRIS-6-1 IRIS-6-2 IRIS-6-3 IRIS-6-4 IRIS-6-5 IRIS-6-6 IRIS-6-7 IRIS-6-8 IRIS-7-1 IRIS-8-1 IRIS-7-2 IRIS-8-2 IRIS-7-3 IRIS-8-3 IRIS-7-4 IRIS-8-4 IRIS-7-5 IRIS-8-5 IRIS-7-6 IRIS-8-6 IRIS-7-7 IRIS-8-7 IRIS-7-8 IRIS-8-8 (2) Color Signal Data to Control Auto White Balance Left-top Side of Image AWBI/AWBQ-1-1 AWBI/AWBQ-1-2 AWBI/AWBQ-1-2 AWBI/AWBQ-1-2 AWBI/AWBQ-2-1 AWBI/AWBQ-3-1 AWBI/AWBQ-2-2 AWBI/AWBQ-3-2 AWBI/AWBQ-2-2 AWBI/AWBQ-3-2 AWBI/AWBQ-2-2 AWBI/AWBQ-3-2 AWBI/AWBQ-4-1 AWBI/AWBQ-4-2 AWBI/AWBQ-4-2 AWBI/AWBQ-4-2 Either I or R – Y is selectable by address 28h. Either Q or B – Y is selectable by address 28h. 14 LR38266 ABSOLUTE MAXIMUM RATINGS PARAMETER Power supply voltage Input voltage Output voltage Storage temperature SYMBOL VDD RATING –0.3 to +4.6 UNIT V VI VO –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 V V TSTG –55 to +150 ˚C RECOMMENDED OPERATING CONDITIONS PARAMETER Power supply voltage SYMBOL VDD MIN. 3.0 TYP. 3.3 MAX. 3.6 UNIT V Operating temperature Input clock frequency TOPR fCK –20 +25 28.6 +70 ˚C MHz ELECTRICAL CHARACTERISTICS PARAMETER Input "Low" voltage Input "High" voltage SYMBOL VIL VIH Input "Low" voltage Input "High" voltage VT– VT+ Hysteresis voltage VT+ – VT– (VDD = 3.3±0.33 V, TOPR = –20 to +70 ˚C) CONDITIONS MIN. TYP. 0.8VDD MAX. UNIT 0.2VDD V V 0.2VDD 0.8VDD V V NOTE 1 2 V 0.2 0.1VDD V V 1.0 0.1VDD µA V Output "Low" voltage Output "High" voltage VOL1 VOH2 IOL = –1.6 mA IOH = 0.8 mA Output leakage current Output "Low" voltage |IOZ| VOL1 High-impedance IOL = –1.6 mA –1.0 Output "High" voltage VOH2 IOH = 0.8 mA 0.9VDD Output leakage current Input "Low" current |IOZ| |IOL1| High-impedance VIN = 0 V –1.0 Input "High" current Output "Low" voltage |IOH2| VOL1 VIN = VDD IOL = –1.6 mA Output "High" voltage Resolution VOH2 RES IOH = 0.8 mA EL VREF = 1.0 V ±3.0 LSB Differential error Full scale current ED |IFS| RREF= 4.8 k$ ROUT = 75 $ ±1.0 13 LSB mA Reference voltage Reference resistance VREF RREF 1.0 4.8 V k$ 9 10 Output load resistance ROUT 75 $ 8 Linearity error 0.9VDD V Applied Applied Applied Applied Applied to to to to to 1.0 µA µA 5 10 6 0.1VDD µA V 0.9VDD V Bit 8 6. 7. 8. 9. 10. inputs (IC, ICD, ICU). input (ICS). output (TO). output (XTO). input (ICU). 15 Applied Applied Applied Applied Applied to to to to to 4 10 NOTES : 1. 2. 3. 4. 5. 3 input (ICD). output (O). outputs (YENCO, CENCO). input (VREF). inputs (IREF1, IREF2). 7 8 LR38266 Data Interface Timing Data is stored in LR38266 SLDI SCK MSB LSB MSB LSB SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 Address D5 D4 Data SCK should be slower than 20 MHz. Data Input ADD [6 : 0] DATA [7 : 0] MAX. 47 ns Data output in 47 ns or more after address input is valid. Data Output 16 D3 D2 D1 D0 LR38266 (3) Black Balance Control Data Output (3 data with 8 bits) Three kinds of outputs below are at DATA output pins. • An average signal of CCD optical black portion consisting of 4 pixels per horizontal line for 128 horizontal lines located in the image center. • An average signal of CCD optical black portion consisting of 2 pixels per horizontal line for 128 horizontal lines located in the image center, which is available to tune the base level of Mg + Ye color signal component. • An average signal of CCD optical black portion consisting of 2 pixels per horizontal line for 128 horizontal lines located in the image center, which is available to tune the base level of Mg + Cy color signal component. DETAIL EXPLANATION CCD CCD type out of 270 k, 320 k, 410 k and 470 k pixels is selected by address 01h. Output Signal Format (1) Analog Video Signal Output Built-in DA converters output luminance (Y) signal without CSYNC and modulated color signal of NTSC or PAL. Standby mode of DA converter makes DA output pins high impedance. (2) Digital Video Signal Output (address 01h) One out of three formats below is selectable by address 01h. High level of pin 74 as DOC makes all digital output pins high impedance. Camera Signal Processing (1) Optical Black Signal Clamping The optical black signal portion is clamped so as to be 64h by using the average level of the input digital signal. The averaging is done for every field. 1. 8-bit Y and 8-bit C 2. 8-bit Y and 8-bit U/V 3. 8-bit U/Y/V/Y Camera Control Data Output (2) Horizontal Period Delay Line There are two horizontal delay lines in this IC for camera signal processing. (1) Exposure Control Data Output (64 data with 8 bits and 2 data with 8 bits) The user-defined image area consists of 64 blocks divided into 8 x 8 blocks. Each average luminance level is output to DATA output pins by setting ADD input pins. In the defined area, the maximum luminance level and the minimum luminance level are output to DATA output pins. (3) Digital Filter for Luminance Signal These are low-pass filters to make a Y signal from the color CCD signal. (4) Gamma Correction for Luminance Signal 10-bit input signal is converted into an 8-bit signal with a gamma curve defined by 10 straight lines. Slope and position of every straight line can be set by address. (2) White Balance Control Data Output (two kinds of 16 data with 8 bits) The user-defined image area consists of 16 blocks divided into 4 x 4 blocks. Average color signal levels of either both I and Q or both R – Y and B – Y are output to DATA output pins by setting ADD input pins. (5) Edge Enhancement of Luminance Signal After gamma correction, the edge of the luminance signal is enhanced in both horizontal and vertical. How to enhance is tunable by address. 17 LR38266 (14) Color Matrix Correction Color rendition can be tuned by address 1Dh and 1Eh under below equation. R – Y = (R – Y) + K1 (B – Y) B – Y = (B – Y) + K2 (R – Y) (6) Set-up Level of Luminance Signal The set-up level is tunable by address. (7) Polarity Option and Level Tuning of Luminance Signal The polarity of the input signal from the AD converter can be inverted before filtering. The DC offset level and the amplitude are tunable by address. (15) Color Level Adjustment The amplitude of R – Y and B – Y can be tuned by address 1Fh and 20h. (16) Color Level Suppression A false color signal at both the transient portion of luminance signal and the high-light portion of luminance signal can be suppressed by address 2Bh, 2Ch, 2Dh, 2Eh, 30h, 31h, 32h, 33h, 34h and 35h. (8) Masking Luminance Signal The restricted area in the whole image can be set by address. The exposure function and the auto white balance function can be used only in the restricted area. (9) Extract of Color Signal Component Color signal components are extracted by following processing calculation. Red = (Mg + Ye) – K1 (G + Cy) Blue = (Mg + Cy) – K2 (G + Ye) YL = ((Mg + Ye) + (G + Cy) + (Mg + Cy) + (G + Ye))/4 K1 and K2 are variable by address. (17) Polarity Option and Level Tuning of Color Signal The polarity of the color component signal can be inverted before gamma correction. The DC offset level and the amplitude are tunable by address 36h, 37h, 38h and 39h. (18) NTSC/PAL Color Signal Encoder R – Y and B – Y color signals are modulated under NTSC or PAL format. Modulated clock frequency and TV format are selected by address 03h, 21h, 22h and 23h. Line-lock system requires the clock generator outside LR38266. (10) Digital Filter of Color Signal Component Red, blue and YL are passed to limit each bandwidth so as to be half of extracted signals by low-pass filters. (11) Black Level Clamping of Color Signal Component The black level of red and blue signals can be tuned by address 15h, 16h, 17h, and 18h. (19) Accumulator to Control Exposure Three kinds of output data below become available by address A0h, 00h to 3Fh, 60h and 61h. • Average signal in either the whole image or restricted area. • Maximum signal in either the whole image or restricted area. • Minimum signal in either the whole image or restricted area. (12) White Balance The amplitude of red and blue signals can be tuned by address 19h, 1Ah, 1Bh, and 1Ch for white balance situation. (13) Color Gamma Correction 10-bit input signal of red, blue and YL signals are converted into an 8-bit signal with gamma curve defined by 10 straight lines. The slope and position of every straight line can be set by address. 18 LR38266 (20) Accumulator to Control White Balance Output data below become available by address 24h, 25h, 26h, 27h, 28h, 29h, 2Ah, A0h and 4Fh to 5Fh. Average signal of I (R – Y) and Q (B – Y) in 16 areas of the whole image. These data can be weighted by both the color zone of I-axis and/or Q-axis and the range of luminance. (21) Accumulator to Control Color Black Balance Average signal of the optical black portion to clamp the black level of color signal is available by address 62h, 63h and 64h. (22) Others • The output timing of synchronous signals are available by address 06h, 07h and 08h. • Functions like standby, muting, etc. are available by address 01h, 03h, 04h and 21h. 19 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE (Unit : mm) 100 LQFP (LQFP100-P-1414) 50 100 26 1 25 14.0±0.2 0.6375 (1.0 ) 16.0±0.3 1.70MAX. 1.4±0.2 0.1±0.1 Package base plane (1.0) (1.0) 14.0±0.2 76 0.125±0.05 20 15.0±0.2 51 0.1 75 M (1.0) 0.08 0.2±0.08 16.0±0.3 0.5TYP. Unit : mm