SHARP LZ2423H

LZ2423H
1/4-type Color CCD Area Sensor
with 320 k Pixels
LZ2423H
DESCRIPTION
PIN CONNECTIONS
The LZ2423H is a 1/4-type (4.5 mm) solid-state
image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With
approximately 320 000 pixels (542 horizontal x 582
vertical), the sensor provides a stable high-resolution
color image.
14-PIN HALF-PITCH WDIP
FEATURES
• Number of effective pixels : 512 (H) x 582 (V)
• Number of optical black pixels
– Horizontal : 2 front and 28 rear
• Pixel pitch : 7.2 µm (H) x 4.7 µm (V)
• Mg, G, Cy, and Ye complementary color filters
• Low fixed-pattern noise and lag
• No burn-in and no image distortion
• Blooming suppression structure
• Built-in output amplifier
• Built-in overflow drain voltage circuit and reset
gate voltage circuit
• Horizontal shift register clock and reset gate clock
voltage : 3.3 V (TYP.)
• Variable electronic shutter (1/50 to 1/10 000 s)
• Compatible with PAL standard
• Package :
14-pin half-pitch WDIP [Plastic]
(WDIP014-P-0400A)
Row space : 10.16 mm
TOP VIEW
OD 1
14 GND
ØRS 2
13 ØV4
NC1 3
12 ØV3
OS 4
11 ØV2
NC2 5
10 ØV1
ØH2 6
9 PW
ØH1 7
8 OFD
(WDIP014-P-0400A)
PRECAUTIONS
• The exit pupil position of lens should be more
than 25 mm from the top surface of the CCD.
• Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LZ2423H
PIN DESCRIPTION
SYMBOL
OD
PIN NAME
Output transistor drain
OS
ØRS
Output signals
ØV1, ØV2, ØV3, ØV4
Vertical shift register clock
ØH1, ØH2
Horizontal shift register clock
Reset transistor clock
OFD
Overflow drain
PW
GND
P-well
Ground
NC1, NC2
No connection
ABSOLUTE MAXIMUM RATINGS
(TA = +25 ˚C)
SYMBOL
VOD
RATING
0 to +18
UNIT
V
NOTE
VOFD
VØRS
Internal output
V
Internal output
V
1
2
Vertical shift register clock voltage
VØV
–10.5 to +17.5
V
Horizontal shift register clock voltage
VØH
V
V
PARAMETER
Output transistor drain voltage
Overflow drain voltage
Reset gate clock voltage
Voltage difference between P-well and vertical clock
VPW-VØV
–0.3 to +12
–28 to 0
Voltage difference between vertical clocks
Storage temperature
VØV-VØV
TSTG
0 to +15
–40 to +85
V
˚C
TOPR
–20 to +70
˚C
Ambient operating temperature
3
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is
applied below 26 Vp-p.
2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 27 V.
2
LZ2423H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Ambient operating temperature
SYMBOL
TOPR
MIN.
TYP.
25.0
MAX.
UNIT
˚C
Output transistor drain voltage
Overflow drain clock p-p level
VOD
14.55
15.0
15.45
V
VØOFD
21.5
Ground
P-well voltage
GND
VPW
LOW level
Vertical shift
VØV1L, VØV2L
VØV3L, VØV4L
INTERMEDIATE level
HIGH level
VØV3I, VØV4I
VØV1H, VØV3H
Horizontal shift
register clock
LOW level
VØH1L, VØH2L
HIGH level
Reset gate clock p-p level
–8.5
VØV1I, VØV2I
register clock
23.5
V
1
VØVL
V
V
2
–7.5
V
0.0
–9.0
–8.0
NOTE
0.0
V
14.55
15.0
15.45
V
VØH1H, VØH2H
–0.05
3.0
0.0
3.3
0.05
5.25
V
V
VØRS
3.3
3.3
5.25
V
Vertical shift register clock frequency
fØV1, fØV2
fØV3, fØV4
15.63
kHz
Horizontal shift register clock frequency
Reset gate clock frequency
fØH1, fØH2
fØRS
9.66
9.66
MHz
MHz
1
NOTES :
• Connect NC1 and NC2 to GND directly or through a capacitor larger than 0.047 µF.
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected
to VL of V driver IC.
* To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
3
LZ2423H
CHARACTERISTICS (Drive method : Field accumulation)
(TA = +25 ˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER
Standard output voltage
SYMBOL
VO
MIN.
TYP.
150
Photo response non-uniformity
Saturation output voltage
PRNU
VSAT
Dark output voltage
VDARK
0.5
Dark signal non-uniformity
Sensitivity
DSNU
R
MAX.
15
NOTE
2
%
3
mV
4
3.0
mV
1, 5
0.5
500
2.0
mV
mV
1, 6
7
–90
–80
1.0
dB
%
8
9
4.0
350
8.0
mA
$
Vector breakup
Line crawling
7.0
3.0
˚, %
%
11
12
Luminance flicker
2.0
%
13
Smear ratio
Image lag
SMR
AI
Blooming suppression ratio
ABL
Output transistor drain current
IOD
Output impedance
RO
650
UNIT
mV
380
1 000
10
NOTES :
• Within the recommended operating conditions of VOD,
VOFD of the internal output satisfies with ABL larger than
1 000 times exposure of the standard exposure conditions,
and VSAT larger than 650 mV.
1. TA = +60 ˚C
2. The average output voltage under uniform illumination.
The standard exposure conditions are defined as when
Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax – Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. VSAT is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions.
5. The average output voltage under non-exposure
conditions.
6. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax –
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
7. The average output voltage when a 1 000 lux light
source with a 90% reflector is imaged by a lens of F4,
f50 mm.
8. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
9. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
10. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
11. Observed with a vector scope when the color bar chart
is imaged under the standard exposure conditions.
12. The difference between the average output voltage of the
(Mg + Ye), (G + Cy) line and that of the (Mg + Cy), (G +
Ye) line under the standard exposure conditions.
13. The difference between the average output voltage of
the odd field and that of the even field under the
standard exposure conditions.
4
LZ2423H
PIXEL STRUCTURE
yyyyyyyyy
,,,,,,,,,
,,,,,,,,,
yyyyyyyyy
,,,,,,,,,
yyyyyyyyy
,,,,,,,,,
yyyyyyyyy
,,,,,,,,,
yyyyyyyyy
,,,,,,,,,
yyyyyyyyy
OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(28 PIXELS)
512 (H) x 582 (V)
1 pin
COLOR FILTER ARRAY
(1, 582)
1st, 3rd
field
(512, 582)
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
(1, 1)
2nd, 4th
field
(512, 1)
5
LZ2423H
TIMING CHART
VERTICAL TRANSFER TIMING
(1st, 3rd FIELD)
623
625 1
6
20
Shutter speed
22 1/2 000 s
HD
VD
ØV1
ØV2
ØV3
ØV4
ØOFD
580 582
+
581
1
+
2
3
+
4
5
+
6
7
+
8
1
2
+
3
4
+
5
6
+
7
OS
(2nd, 4th FIELD)
311
318
332
HD
VD
ØV1
ØV2
ØV3
ØV4
ØOFD
579 581
+
+
580 582
OS
HORIZONTAL TRANSFER TIMING
618, 1
60
HD
ØH1
ØH2
ØRS
OS
…512
OB (2)
OUTPUT (512) 1πππ
OB (28)
29
49
ØV1
39
59
ØV2
54
24
ØV3
34
64
ØV4
62
ØOFD
6
72
LZ2423H
READOUT TIMING
(1st, 3rd FIELD)
HD
1
60
618, 1
242
29 49
ØV1
39 59
ØV2
24
ØV3
29 49
161
54
34
ØV4
290
449
290
180
60
39 59
338
54
34
64
64
(2nd, 4th FIELD)
HD
ØV1
ØV2
ØV3
ØV4
1
60
618, 1
242
29 49
39 59
24 54
34
60
290
161
59
290
180
338
54
450
64
7
64
V4
V3B
V3A
V1B
VMa
V1A
VH
8
13 14 15 16 17 18 19 20 21 22 23 24
1
V1X
VH1AX
V3X
VDD
GND
+
VH3AX
V4X
VH1BX
(*1) ØRS, OFD :
Use the circuit parameter indicated in
this circuit example, and do not connect
to DC voltage directly.
100 $
+
0.1 µF
6
5
4
3
2
(*1)
1
9
8
10 11 12 13 14
LZ2423H
(*1)
7
OFD
+5 V
V3X
VH1AX
V1X
V2X
OFDX
NC
PW
VH3AX
V2
LR36685
VL
2
VMb
3
POFD
4
ØH1
5
ØH2
6
OS
7
NC2
8
NC1
9
OD
12 11 10
0.01 µF
ØRS
V4X
VH
VL (VPW)
VOD
ØRS
ØH2
ØH1
1 M$
ØV4
ØV1
+
+
270 pF
CCD
OUT
1 M$
LZ2423H
SYSTEM CONFIGURATION EXAMPLE
GND
ØV3
ØV2
VOFDH
VH3BX
OFDX
V2X
PACKAGES FOR CCD AND CMOS DEVICES
PACKAGE
(Unit : mm)
14 WDIP (WDIP014-P-0400A)
0.03
9.00±0.10 (◊)
(◊ : Lid's size)
0.50±0.50
CCD
1
0.50±0.50
Glass Lid
CCD
Package
0.03
Cross section A-A'
7
MAX.
Rotation error of die : ¬= 1.0˚
0.80±0.05 (◊)
5.00±0.075
¬
1.27±0.25
A
5.02MAX.
2.55±0.10
5.00±0.075
3.50±0.30 3.35±0.10
10.00±0.10
8
1.39±0.05
9.00±0.10 (◊)
14
Center of effective imaging area
and center of package
1.96±0.05
10.00±0.10
A'
0.30TYP.
0.46TYP.
0.25
0.25±0.10
P-1.27TYP.
+0.5
10.16–0
M
9
PRECAUTIONS FOR CCD AREA SENSORS
PRECAUTIONS FOR CCD AREA SENSORS
(In the case of plastic packages)
– The leads of the package are fixed with
package body (plastic), so stress added to a
lead could cause a crack in the package
body (plastic) in the jointed part of the lead.
1. Package Breakage
In order to prevent the package from being broken,
observe the following instructions :
1) The CCD is a precise optical component and
the package material is ceramic or plastic.
Therefore,
ø Take care not to drop the device when
mounting, handling, or transporting.
ø Avoid giving a shock to the package.
Especially when leads are fixed to the socket
or the circuit board, small shock could break
the package more easily than when the
package isn’t fixed.
2) When applying force for mounting the device or
any other purposes, fix the leads between a
joint and a stand-off, so that no stress will be
given to the jointed part of the lead. In addition,
when applying force, do it at a point below the
stand-off part.
Glass cap
Package
Lead
Fixed
Stand-off
3) When mounting the package on the housing,
be sure that the package is not bent.
– If a bent package is forced into place
between a hard plate or the like, the package may be broken.
4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could
deteriorate.
Therefore,
ø Do not hit the glass cap.
ø Do not give a shock large enough to cause
distortion.
ø Do not scrub or scratch the glass surface.
– Even a soft cloth or applicator, if dry, could
cause dust to scratch the glass.
(In the case of ceramic packages)
– The leads of the package are fixed with low
melting point glass, so stress added to a
lead could cause a crack in the low melting
point glass in the jointed part of the lead.
Low melting point glass
Lead
2. Electrostatic Damage
As compared with general MOS-LSI, CCD has
lower ESD. Therefore, take the following anti-static
measures when handling the CCD :
1) Always discharge static electricity by grounding
the human body and the instrument to be used.
To ground the human body, provide resistance
of about 1 M$ between the human body and
the ground to be on the safe side.
2) When directly handling the device with the
fingers, hold the part without leads and do not
touch any lead.
Fixed
Stand-off
10
PRECAUTIONS FOR CCD AREA SENSORS
ø The contamination on the glass surface
should be wiped off with a clean applicator
soaked in Isopropyl alcohol. Wipe slowly and
gently in one direction only.
– Frequently replace the applicator and do not
use the same applicator to clean more than
one device.
◊ Note : In most cases, dust and contamination
are unavoidable, even before the device
is first used. It is, therefore, recommended
that the above procedures should be
taken to wipe out dust and contamination
before using the device.
3) To avoid generating static electricity,
a. do not scrub the glass surface with cloth or
plastic.
b. do not attach any tape or labels.
c. do not clean the glass surface with dustcleaning tape.
4) When storing or transporting the device, put it in
a container of conductive material.
3. Dust and Contamination
Dust or contamination on the glass surface could
deteriorate the output characteristics or cause a
scar. In order to minimize dust or contamination on
the glass surface, take the following precautions :
1) Handle the CCD in a clean environment such
as a cleaned booth. (The cleanliness level
should be, if possible, class 1 000 at least.)
2) Do not touch the glass surface with the fingers.
If dust or contamination gets on the glass
surface, the following cleaning method is
recommended :
ø Dust from static electricity should be blown
off with an ionized air blower. For antielectrostatic measures, however, ground all
the leads on the device before blowing off
the dust.
4. Other
1) Soldering should be manually performed within
5 seconds at 350 °C maximum at soldering iron.
2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise
optical component. Do not give a mechanical
shock to the CCD.
3) Do not expose the device to strong light. For
the color device, long exposure to strong light
will fade the color of the color filters.
11