LZ2426J LZ2426J Dual-power-supply (5 V/12 V) Operation 1/4-type B/W CCD Area Sensor with 320 k Pixels DESCRIPTION PIN CONNECTIONS The LZ2426J is a 1/4-type (4.5 mm) solid-state image sensor that consists of PN photo-diodes and CCDs (charge-coupled devices) driven by dualpower-supply. With approximately 320 000 pixels (542 horizontal x 582 vertical), the sensor provides a stable high-resolution B/W normal or mirror image. 14-PIN HALF-PITCH WDIP TOP VIEW ØRS 1 FEATURES • Number of effective pixels : 512 (H) x 582 (V) • Number of optical black pixels – Horizontal : 2 front and 28 rear • Pixel pitch : 7.2 µm (H) x 4.7 µm (V) • Low fixed-pattern noise and lag • No burn-in and no image distortion • Blooming suppression structure • Built-in output amplifier • Built-in pulse mix circuit • Variable electronic shutter (1/50 to 1/10 000 s) • Normal or mirror image output available from common output pin • Compatible with CCIR standard • Package : 14-pin half-pitch WDIP [Plastic] (WDIP014-P-0400A) Row space : 10.16 mm 14 OFD GND 2 13 ØTG OS 3 12 ØV2 OD 4 11 ØV1 ØH2B 5 10 ØV4 ØH2 6 9 ØV3 ØH1B 7 8 ØH1 (WDIP014-P-0400A) PRECAUTIONS • The exit pupil position of lens should be more than 20 mm from the top surface of the CCD. • Refer to "PRECAUTIONS FOR CCD AREA SENSORS" for details. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LZ2426J PIN DESCRIPTION SYMBOL OD PIN NAME Output transistor drain OS ØRS Output signals ØV1, ØV2, ØV3, ØV4 Vertical shift register clock ØH1, ØH2, ØH1B, ØH2B Horizontal shift register clock NOTE Reset transistor clock ØTG Transfer gate clock OFD GND Overflow drain Ground 1 NOTE : 1. ØV1-ØV4 : Input the clock through a 0.1 µF capacitor. ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C) PARAMETER Output transistor drain voltage SYMBOL VOD RATING 0 to +15 UNIT V Overflow drain voltage VOFD 0 to +30 V Reset gate clock voltage VØRS –0.3 to +15 0 to +7.5 V V –0.3 to +7.5 –0.3 to +15 V V –40 to +85 –20 to +70 ˚C ˚C Vertical shift register clock voltage VØV Horizontal shift register clock voltage VØH Transfer gate clock voltage VØTG Storage temperature TSTG Ambient operating temperature TOPR 2 LZ2426J RECOMMENDED OPERATING CONDITIONS PARAMETER Ambient operating temperature SYMBOL TOPR MIN. TYP. 25.0 MAX. UNIT ˚C Output transistor drain voltage VOD 12.0 12.5 13.0 V 12.0 V 1 12.5 0.0 13.0 V V 2 Overflow drain When DC is applied VOFD 2.7 voltage Ground When pulse is applied p-p level VØOFD GND 12.0 Transfer gate clock LOW level HIGH level VØTGL –0.05 0.0 0.05 V VØTGH 12.0 12.5 13.0 V 4.7 5.0 5.5 V –0.05 0.0 0.05 V 4.7 5.0 5.5 V VOD – 9.0 9.5 V V Vertical shift register clock Horizontal shift register clock Reset gate clock VØV1, VØV2 p-p level VØV3, VØV4 VØH1L, VØH2L LOW level VØH1BL, VØH2BL VØH1H, VØH2H HIGH level VØH1BH, VØH2BH LOW level HIGH level VØRSL VØRSH 0.0 VOD – 4.5 fØV1, fØV2 fØV3, fØV4 Vertical shift register clock frequency Horizontal shift register clock frequency fØH1, fØH2 fØH1B, fØH2B Reset gate clock frequency tw1, tw2 kHz 9.66 MHz 9.66 fØRS Horizontal shift register clock phase 15.63 8.0 13.0 NOTE MHz 18.0 ns 3 NOTES : 1. When DC voltage is applied, shutter speed is 1/50-second. 2. When pulse is applied, shutter speed is less than 1/50-second. 3. ØH1, ØH2 ØH1B, ØH2B : Normal image output mode ØH1B, ØH2B : Mirror image output mode tw1 tw2 * To apply power, first connect GND and then turn on VOD and then turn on other powers and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied. 3 LZ2426J CHARACTERISTICS (Drive method : Field accumulation) (TA = +25 ˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS". Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.) PARAMETER Standard output voltage SYMBOL VO Photo response non-uniformity Saturation output voltage PRNU VSAT Dark output voltage VDARK Dark signal non-uniformity Sensitivity MIN. TYP. 150 MAX. 15 450 UNIT mV NOTE 2 % 3 mV 4 0.5 mV 1, 5 DSNU R 0.5 400 mV mV 1, 6 7 Smear ratio Image lag SMR AI –84 dB % 8 9 Blooming suppression ratio ABL Output transistor drain current IOD Output impedance RO 1.0 1 000 10 4.0 400 8.0 mA $ NOTES : • VOFD should be adjusted to the minimum voltage such that ABL satisfy the specification, or to the value displayed on the device. 1. TA = +60 ˚C 2. The average output voltage under uniform illumination. The standard exposure conditions are defined as when Vo is 150 mV. 3. The image area is divided into 10 x 10 segments under the standard exposure conditions. Each segment's voltage is the average output voltage of all pixels within the segment. PRNU is defined by (Vmax – Vmin)/Vo, where Vmax and Vmin are the maximum and minimum values of each segment's voltage respectively. 4. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. 5. The average output voltage under non-exposure conditions. 6. The image area is divided into 10 x 10 segments under non-exposure conditions. DSNU is defined by (Vdmax – Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each segment's voltage respectively. 7. The average output voltage when a 1 000 lux light source with a 90% reflector is imaged by a lens of F4, f50 mm. 8. The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the V/10 square. 9. The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 10. The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. 4 LZ2426J PIXEL STRUCTURE OPTICAL BLACK (2 PIXELS) OPTICAL BLACK (28 PIXELS) 512 (H) x 582(V) 1 pin TIMING CHART VERTICAL TRANSFER TIMING <NORMAL OUTPUT> (1st, 3rd FIELD) 623 625 1 6 20 22 HD VD ØV1 ØV2 ØV3 ØV4 ØTG 580 582 + 581 1 + 2 3 + 4 5 + 6 7 + 8 1 2 + 3 4 + 5 6 + 7 OS (2nd, 4th FIELD) 311 318 332 HD VD ØV1 ØV2 ØV3 ØV4 ØTG 579 581 + + 580 582 OS 5 LZ2426J HORIZONTAL TRANSFER TIMING <NORMAL OUTPUT> 618, 1 HD 60 24 ØH1 84.5 ØH2 ØRS OS ... 512 PRE SCAN (4) OB (2) OUTPUT (512) 1ππππππππππ OB (28) 29 49 ØV1 59 39 ØV2 24 54 ØV3 34 64 ØV4 62 72 ØOFD READOUT TIMING <NORMAL OUTPUT> (1st, 3rd FIELD) HD 1 60 618, 1 60 29 49 ØV1 39 59 ØV2 24 ØV3 54 34 ØV4 242 ØTG 25.07 µs (242 bits) 64 338 9.95 µs (96 bits) 64.00 µs (618 bits) (2nd, 4th FIELD) HD 1 618, 1 60 60 29 49 ØV1 39 59 ØV2 24 54 ØV3 34 64 ØV4 242 338 ØTG 25.07 µs (242 bits) 9.95 µs (96 bits) 64.00 µs (618 bits) 6 LZ2426J VERTICAL TRANSFER TIMING <MIRROR OUTPUT> (1st, 3rd FIELD) 623 625 1 6 20 22 HD VD ØV1 ØV2 ØV3 ØV4 ØTG 578 580 582 + + 579 581 1 + 2 3 + 4 5 + 6 1 2 + 3 4 + 5 OS (2nd, 4th FIELD) 311 318 332 HD VD ØV1 ØV2 ØV3 ØV4 ØTG 577 579 581 + + + 578 580 582 OS HORIZONTAL TRANSFER TIMING <MIRROR OUTPUT> 618, 1 60 HD 4 ØH1 58.5 ØH2 ØRS OS PRE SCAN (4) OB (2) ππππ1 9 29 ØV1 19 39 ØV2 4 34 ØV3 14 44 ØV4 42 ØOFD 7 52 OB (28) OUTPUT (512) 512ππππππππππ LZ2426J READOUT TIMING <MIRROR OUTPUT> (1st, 3rd FIELD) HD 1 60 618, 1 60 9 29 ØV1 19 39 ØV2 ØV3 4 34 24 44 ØV4 222 ØTG 23.00 µs (222 bits) 318 9.95 µs (96 bits) 64.00 µs (618 bits) (2nd, 4th FIELD) HD 1 60 618, 1 60 9 29 ØV1 19 39 ØV2 4 34 ØV3 14 44 ØV4 222 318 ØTG 23.00 µs (222 bits) 9.95 µs (96 bits) 64.00 µs (618 bits) 8 • Example of drive circuit with LR38580 driver IC. 9 ØRS ØRS GND VOD 3 OS 1 k$ 4 OD ØH1 ØH1B ØH2 ØH2B ØV4 ØV3 ØV2 ØV1 (*1) ØV1-ØV4 : Input the clock through a 0.1 µF capacitor. 2SC4627 7 6 5 ØH2B 2 8 ØH2 1 LZ2426J (*1) 9 ØH1B CCD OUT 0.1 µF OFD OFD 10 $ ØTG 22 k$ ØV2 2.2 k$ ØV1 20 k$ ØV4 14 13 12 11 10 1 000 pF ØV3 2SC4716 1 M$ 390 $ 68 $ ØH1 VCC TGX 0.1 µF 0.1 µF 0.1 µF 0.1 µF LZ2426J SYSTEM CONFIGURATION EXAMPLE PACKAGES FOR CCD AND CMOS DEVICES PACKAGE (Unit : mm) 14 WDIP (WDIP014-P-0400A) 0.03 9.00±0.10 (◊) (◊ : Lid's size) 0.50±0.50 CCD 1 0.50±0.50 Glass Lid CCD Package 0.03 Cross section A-A' 7 MAX. Rotation error of die : ¬= 1.0˚ 0.80±0.05 (◊) 5.00±0.075 ¬ 1.27±0.25 A 5.02MAX. 2.55±0.10 5.00±0.075 3.50±0.30 3.35±0.10 10.00±0.10 8 1.39±0.05 9.00±0.10 (◊) 14 Center of effective imaging area and center of package 1.96±0.05 10.00±0.10 A' 0.30TYP. 0.46TYP. 0.25 0.25±0.10 P-1.27TYP. +0.5 10.16–0 M 10 PRECAUTIONS FOR CCD AREA SENSORS PRECAUTIONS FOR CCD AREA SENSORS (In the case of plastic packages) – The leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. 1. Package Breakage In order to prevent the package from being broken, observe the following instructions : 1) The CCD is a precise optical component and the package material is ceramic or plastic. Therefore, ø Take care not to drop the device when mounting, handling, or transporting. ø Avoid giving a shock to the package. Especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn’t fixed. 2) When applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. In addition, when applying force, do it at a point below the stand-off part. Glass cap Package Lead Fixed Stand-off 3) When mounting the package on the housing, be sure that the package is not bent. – If a bent package is forced into place between a hard plate or the like, the package may be broken. 4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could deteriorate. Therefore, ø Do not hit the glass cap. ø Do not give a shock large enough to cause distortion. ø Do not scrub or scratch the glass surface. – Even a soft cloth or applicator, if dry, could cause dust to scratch the glass. (In the case of ceramic packages) – The leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. Low melting point glass Lead 2. Electrostatic Damage As compared with general MOS-LSI, CCD has lower ESD. Therefore, take the following anti-static measures when handling the CCD : 1) Always discharge static electricity by grounding the human body and the instrument to be used. To ground the human body, provide resistance of about 1 M$ between the human body and the ground to be on the safe side. 2) When directly handling the device with the fingers, hold the part without leads and do not touch any lead. Fixed Stand-off 11 PRECAUTIONS FOR CCD AREA SENSORS ø The contamination on the glass surface should be wiped off with a clean applicator soaked in Isopropyl alcohol. Wipe slowly and gently in one direction only. – Frequently replace the applicator and do not use the same applicator to clean more than one device. ◊ Note : In most cases, dust and contamination are unavoidable, even before the device is first used. It is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. 3) To avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dustcleaning tape. 4) When storing or transporting the device, put it in a container of conductive material. 3. Dust and Contamination Dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. In order to minimize dust or contamination on the glass surface, take the following precautions : 1) Handle the CCD in a clean environment such as a cleaned booth. (The cleanliness level should be, if possible, class 1 000 at least.) 2) Do not touch the glass surface with the fingers. If dust or contamination gets on the glass surface, the following cleaning method is recommended : ø Dust from static electricity should be blown off with an ionized air blower. For antielectrostatic measures, however, ground all the leads on the device before blowing off the dust. 4. Other 1) Soldering should be manually performed within 5 seconds at 350 °C maximum at soldering iron. 2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise optical component. Do not give a mechanical shock to the CCD. 3) Do not expose the device to strong light. For the color device, long exposure to strong light will fade the color of the color filters. 12