LZ93N61 LZ93N61 Timing Pulse Generator LSI for CCD DESCRIPTION PIN CONNECTIONS The LZ93N61 is a CMOS timing generator LSI which provides timing pulses used to drive a CCD area sensor, in combination with the SSG LSI (LZ93NI 9, LZ93B53). FEATURES ● Switchable between 270000 pixels CCD and ● ● c ● 320000 pixels CCD Switchable between NTSC (EIA) and PAL (CCIR) systems Internal electronic shutter : Shutter speed is selectable from 1/W, 1/125, 1/250, 1/500, 1/1 000, 1/2 000, 1/4 000 and 1/10 000 s, in addition to this, 1/100 s (PAL : 1/120 s) in Flicker-less mode using parallel or serial code. Shutter speed can also be controlled in 1 H period using an external trigger to the EXST input. Single +5 V power supply Package : 48-pin QFP(QFP048-P-I 01 O) 48-PIN QFP TOP VIEW I 1 Vlx 37 24 R12 V2X 3a 23 R12 39 22 C12 V3X 21 CI1 V4X 40 20 FCDS OFDX 41 FR 42 19 S12 GND 43 18 SI1 FH2 44 17 FS FHI 45 16 SP12 CKI 46 15 SPII 14 SP2 CKO 47 TSTI W o 13 SPI “In tie abeence of conf[mtlon by device acecification ehwf?, WARP fakee no reswns!blhty b anY defects hat recur In qutpment USIW any of WARPS davIces, show In Cahlws, I deta bwks, etc hn~ct WARP !n mder to obtain tie Iateat vefilon of he device swIkaiim shw~ ktie USIW any 8HARPs dewce.” 287 LZ93N61 DOUT TST I HDI GND GND SESL SINV CKI FH I CKO FH2 TVMD MCK I MCK2 MCK3 VDI MCK. Vcc Vlx GMD V2X V3X V4X VHIX FLMD VH3X PSMD OFDX EXMD SE Do DI SPI 1 D, SPI 2 EXST SP 1 Cll C12 SP2 F C D S S1, 288 S12 FS RI I R12 FR FRS LZ93N61 ABSOLUTE MAXIMUM RATINGS PARAM=ER Supply voltage Input voltage RATING SYMBOL Vcc UNIT – 0.3 to + 7.0 v VI –0.3 to Vcc + 0.3 v Vo – 0.3 to Vcc + 0.3 v Operating temperature Topr – 2 0 t o +70 “c Storage temperature Tstg –55 to +150 ‘c Output voltage DC CHARACTERISTICS PARAMHER (VCC=5 V~l OYO. T a = – 1 0 ~ SYMBOL [I CONDITIONS 1 MIN. ] TYP. I MAX. Input Low voltage VIL Input High voltage vlH 3.5 Input High threshold voltage vT + 2.2 3,8 v lnDut Low threshold voltage vT - 1,0 2.4 v vT+ –VT- 0.4 Hysteresis voltage 1.5 4 mA Output Low voltage VOLI IOL = Output High voltage vOH 1 IoH=–P mA Output Low voltage vOL2 IOL =8 mA Output High voltage vOH2 IoH=–4 mA Output Low voltage vOL3 IoL=16 mA Output High voltage v0H3 IoH=–10 mA I IIL1 I Vl=o v I IIL2 I Vl=o v Input Low current Input High current NOTES : 1. Applled 2. Applied 3. Applied 4. Applied 5, Applied 6. Applied 7. Applied 8. Applied 9. Applied to to to to to to to to to 1tlHl I VI= Vcc I IIH2 I VI= Vcc 1 2 v 0.4 v v 0.4 4.0 0.4 3 v v 4.0 8.0 v v 4.0 8.0 t o +70”C) UNIT I NOTE 4 v v 5 1.0 PA 6 60 \ AA 7 1.0 PA 8 60 PA 9 all inputs except for VDI, CKI. input (VDI). all outputs except for CKO. outputs (FR, MCK I, MCK2, MCK3, MCK4). outputs (FH 1, FH2). all inputs except for PSMD, FRS, FLMD, Do, DI, D2, EXST, SESL, SINV Inputs (PSMD, FRS, FLMD, Do, D!, D2, EXST, SESL, StNV). all inputs except for EXMD, TVMD, TST 1. inputs (EXMD, TVMD, TST I). 289 LZ93N61 ~:. SYMBOL 1/0 1 HDI 2 3 4 POLARITY PfN NAME FUNCTION Ic MM Horizontal drive pulse Ths HDI pin is used to input the horizontal reference signal from SSG. It is connected to the HD (pin 31) of the I-Z93N 19. VDI Ics n Vertical drive pulse The VDI pin is used to input the vertical reference signal from SG. It is connected to the VD (pin 34) of the U93NI 9, DOUT o nn Delay-Line clock The DOUT pin output 1/2 dividing clock input to the CKI (pin 46). It is connected to the CLKI (pin 27) of the ~93Nl 9. Shutter mode select input The PSMD pin is used to switch the Shutter Speed %tting mode. High level : Parallel Setting mode Low level : Serial Setting mode (Refer to “SHU~ER MODE TABLE”. ) PSMD Icu – 5 FRS Icu – FR control input The FRS pin is used to selects the ~larity of the FR (pin 42). High level : negative ~larity Low level : positive polarity 6 FLMD Icu – Flicker-less mode select The FLMD pin is used to prevent the flicker. (Refer to “SHU~ER MODE TABLE ”.) 7 GND — — Ground The GND is a ground pin. 6 Do Icu — Shutter speed switching input O The Do pin is used to control the shutter speed. (Refer to “SHLflTER MODE TABLE”. ) 9 DI Icu — Shutter speed switching input 1 The DI pin is used to control the shutter speed. (Refer to “SH~ER MODE TABLE ”.) 10 D2 Icu — Shutter speed switching input 2 The D2 pin is used to control the shutter speed. (Refer to “SHUITER MODE TABLE ”.) 11 EXST Icu — Shutter speed control 1 The EXST pin used to control the shutter speed 1 H by 1 H. (Refer to “SHU~ER MODE TABLE ”,) 12 EXMD Icu — Shutter speed control 2 When the EXMD input pin is Low level, the EXST (pin 11) is prohibited. (Refer to “SHUTTER MODE TABLE” .) 13 SP1 o L Color sampling pulse 1 The SPI pin output the sampling pulse for color d~ modulation ba~ upon the output signal of ~D, It outputs at High level of the SE (pin 29). 14 SP2 o L @lor sampling pulse 2 The SP2 pin output the sampling pulse for COIW de mdulation based upon the output signal of CCD, It outputs at Low level of the SE (pin 29). 290 U93N61 PrN .- Uo. 1 CVMR~ -------- I/n -$- I MLAR~ .- —..... I PIN NAME FUNCTON 15 SPI 1 IC m SPI and SP2 phase control input 1 The SPII pin sets the falling edge of COICS sampling pulses SP1 (pin 13) and SP2 (pin 14). 16 SP12 Ic N SP1 and SPZ phase control input 2 The SP12 pin sets the rising edge of color sampling pulses SPI (pin 13) and SP2 (pin 14). 17 FS o n CDS pulse 2 The FS pin outputs the pulses for sampling output signals of CCD. 18 SI 1 Ic m FS phase control input 1 The SII pin sets the phase of the FS (pin 17). 19 S12 Ic nn FS phase control input 2 The SIZ pin sets the width of the FS (pin 17). 20 FCDS o n FCDS pulse 1 The FCDS pin outputs the pulse to clamp the output signals of CCD. 21 c11 Ic m FCDS phase control input 1 The Cl 1 pin sets the phase of the FCDS (pin 20). 22 C12 Ic N FCDS phase control input 2 The CIZ pin sets the width of the FCDS (pin 20). 23 RI j Ic nn FR phase control input 1 The RI I pin sets the pahse of the FR (pin 42). 24 R12 Ic nn FR phase control input 2 The R12 pin sets the width of the FR (pin 42). 25 MCKI o nn Clock output 1 The MCKI pin outputs 1/2 dividing pulse of CKI (pin 46). It is the same phase with the FH i (pin 45). 26 MCK2 o nn Clink output 2 The MCK2 pin outputs 1/2 dividi~ pulse of CKI (pin 46). It is delayad by approximately 90° in phase with respect to FH1 (pin 45). 27 MCK3 o nrl Clwk output 3 Tk MCK3 pin outputs 1/2 dividing pulse of CKI (pin 46). It is the same phase with the FHz (pin 44). 28 MCK4 o m Clock output 4 The MCK4 pin outputs 1/2 dividing pulse of CKI (pin 46). It is delayed by approximately 90” in phase witi respect to FH2 (pin 44). 29 SE o rL Color demodulation pulw The SE pin outputs the demodulation carrier of output signals of CCD, and input the switching signal of color sampling pulses SP1 (pin 13) and SPZ (pin 14). It outputs 1/4 dividing pulse of the CKI input (pin 46), and selects the phase in mmbination with the SESL (pin 32) and the SINV (pin 34). 30 Vcc – — Power supply The Vcc is a + 5 V power supply pin. 31 GND – – Ground The GND is a ground pin. 291 I-Z93N61 :: SYMBOL 1/0 POLARITY PIN NAME FUNCTION The SESL input pin selects the phase of color demodulation carrier output SE (pin 29). 32 SESL Icu — Low level : synchronized with the rising edge SF control input of FHI (pin 45). High level : synchronized with the rising edge of FH2 (pin 44). The TVMD input pin selects the TV system. 33 TVMD ICD – TV mode input Low level : NTSC system Hige level : PAL system 34 SINV Icu — tiior line input The SINV input pin is used to invert the color demodulation carrier output SE (pin 29) at 1 H rate. The 35 VH3X 0 r Read out pulse 3 VH3X is a pulse output pin to transfer the photc- diode charge of CCD to the vertical shift register. It is connected to the 3BX (pin 11) of the LR366B3N vertical driver LSI. The VHIX is a pulse output pin to transfer the photc- 36 V HIX 0 lr Read out pulse 1 diode charge of CCD to the vertical shifi register. It is connected to the 1 BX (pin 8) of the LR-N vertical driver LSI. 37 VI x o L Vertical transfer pulse 1 38 V2X o n Vertical transfer pulse 2 39 V3X o u Vertical transfer pulse 3 40 V4X o u Vertical transfer pulse 4 41 OFDX o lr OFD pulse output 42 FR 02 T Reset pulse L 43 GND – – 44 FH2 05 Uu 45 FH I 05 nn The VI x, V2X, V3X and V4X are transfer pulse output pins for CCD vertical shift register, The OFDX pin is used to output for controlling OFD voltage during electronic shutter operation. The FR pin outputs the reset pulse of CCD. It is connected to the ~ R through the offset circuit. Ground The GND is a ground pin. Horizontal transfer The FH2 pin outputs the horizontal transfer pulse of pulse 2 CCD shift register. It is connected to the ~ Hz. Horizontal transfer The FHI pin outputs the horizontal transfer pulse of pulse 1 CCD shift register, It is connected to the #HI, The CKI is a reference clock input pin of horizontal and vertical pulses, Frequency for NTSC (TVMD = L) 46 CKI ICK nlllul Clock input 1212 fH : CCD of 542 horizontal pixels. Frequency for PAL (TVMD = H) 1236 fH : CCD of 542 horizontal pixels. (fH = Horizontal frequency) 292 LZ93N61 ::. SYMBOL I I CKO 47 I Ic 48 I TSTI I I : Input pln Icu : Input pin 0 : 02 : 05 : Output pin. 1/0 ] POLARITY ] OCK I Uuuv I ICD I - I Test PIN NAME The CKO pin outputs clocks at the reverse of the Clock output terminal FUNCTION I CKI (pin 46). 1 I The TSTI input pin is normally kept Low or open. (CMOS level). (CMOS level with buflt-in pull-up resistor). ICD : Input pin (CMOS level with built-in pull-down resistor). Ics : Input pin (CMOS level schmitt). ICK : Input pin for oscillation. OCK : Output pin for oscillation. Output pin. Output pin. 293 LZ93N61 SUPPLEMENTARY EXPLANATION SH~ER MODE TABLE I I SHUITER SPEED (S]) FL MD Tv MD EX MD EX ST ‘2 “ m 4 6 33 12 11 10 9 8 H H L L L L NORMAL H H L L L H 1 /125 P s MD PIN ( REGISTER IN LSl INPUT PIN 1 1 1 1 D, I D6 I D5 1 D4 1 D3 D2 1 I DI Do 1 I I H H L L H L 1 /250 J u J H H L L H H 1 /500 L H L L 1/1 000 ~ n. : H : H L H L H 1/2 000 L H H L 1/4 000 H H Iui, n L L iii, L L H H H 1,.. /10000 I t < E & H 1 I 1 1 1 1 1 1 I I 1 I H L L H L L H H L L L NORMAL L H L H H L L H 1/125 L H L H H L H L 1 /250 L H L H H L H H 1 /500 L H L H H H L L 1/1 000 L H L H H H L H 1/2 000 L L H H L H H H H L 1/4 000 L H H H H H 1/10000 L H H L H L H H L L H L L L H L L H L H L L L L L L L L H L 1 1 1 t H NOTES : 1. NTSC=l/W S, PAL=l/50 I I I 1/120 H L 1/100 H L L 1/120 H H L 1/100 L L 1 1/120 OFDX = H 1/100 1/120 1 1 S. The data of shutter speed was decided by the control pulse EXST (pin 11), is deleted. 3. The shutter s@ed is decided by the falling edge of control pulse EXST (pin 11). 4. The data of shutter s-d was decided by the control pulse EXST (pin 11), hold as it is 2. lNmAL STATUS IN SERIAL MODE AND EXTERNAL TRIGGER MODE When power is turned on in Serial mode (PSMD = L) or External Trigger mode (EXMD = H), the mode is not established until data is input from serial code or EXST, 294 1 . /.nfi 1/ Iuu J 1 I H NOTE OFDX = H 2 EXST 3 LZ93N61 SERIAL DATA FORMAT D I (pin 9) D2 (pin 10) Do DI D2 D3 D. D, De D7 n Do (pin 8) NOTE : D&D7 are latched by the rising edge of pulse D, (pin 9). By the falling edge of pulse Do (pin 8), the shutter DESCRIPTION OF EXTERNAL SYNCHRONOUS SHUTTER MODE 1. When EXMD = H, this mode is given priority over other modes. On applying falling edge of trigger input to EXST (pin 11), the IC reads at the rising edge of HDI and latches the V period counter value, and controls final output of the OFDX pulse during this H period. (The pulse must lasts until HDI goes high.) 2. Once latched, the value of V period counter is retained until the next trigger is input as long as EXMD = H, even trigger input is for odd (ODD) w even (EVEN) field, the storage time of another field becomes the same as the field with trigger input automatically. NTSC 17/279 H PAL 19/331 H HOI EXST (PATTERN) 19/281 H 21/W H n n Note that when changing in high speed shutter direction, the internally stored data is used first, This caue-es the delay to control by one field. [Trigger input disabled range] To match ODD storage time with EVEN stomge time, the pulse start position is set at 20/283 H for NTSC and 22/335 H for PAL. This means that inputting the trigger at 18/280, 281 H in NTSC mode and 20/332, 333 H in PAL mode is made disabled. 20/282 H 22/=4 H I - 1 21/2S3 H 23/=5 H 22/2W H 241W H n ~~~~ ~ b (INVALID) C (EVEN IWALIO) a d[ e OFDX [ (PATTERN) 18/280 H 20/W2 H speed is decided. 000/lst, 3rd FIELD ~ WEN/2nd, 4th FIELD ~ a END w b-u , c d e 000 START EVEN START 295 LZ93N61 TIMING DAIGRAM VERTICAL PULSE TIMING < NTSC > Shutter speed 1/10000 s FIELD) (ODD 525 1 CBLK HDI VDI VI x V2X V3X V4X VHIX VH3X OFDX n H n 21 10 [ 1 n n n n n n n n n n n n n n n n n n n ~------JUUUUUUUUL --~ . n n n n n n n n n n n n n n n n n n 1 482 .M ap 4y 4P 4W n n n n n 5 9 1 1 ;:+: 24681: + + M 465 487 4= 491 -n. - n n - n - u u u I n n n - - n 1 3 1 5 + + 1+2?416 n n - n - - u u u n n n n - ~uuuuuuu uu~uuuu Uuuuuu II u u u u u u u u u H u Vul ~ 481 4P 465 a7 n n n n n n n n VI. n@2n4wn4ffiflwn4mn4’2fl n n n n V2X V3X u u u u u u u u n n n] u u u u u u u u u n n L n n n n n n n 0 n n n n n n n n n n n n n U u u u u u u u u IJu u u (EVEN FIELD) 272 263 CBLK HDI ..-. n + + m 4~1 + + 283 n 12468 + + 3 5 + 7 n u n 11 u u u u u 9 u 10 + 1 1 n u n u VHIX VH3X OFDX ~ u u u IJ u 1+4 1 5 n u n u u u “ u u u u u u u u u u u u VERTICAL PULSE TIMING < PAL > Shutter speed 1/10000 s (l St, 3rd FIELD) 10 625 1 623 U— 16 21 23 n n n n n n n V2X V3X V4X n n n u u n u . . n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n u u n u n u u — u u u u u n n 3 :7 i+i 2 4 6 5:6 5;8 ~ 5= n’mn’’’nn’n . UUUL n J VIX VHIX VH3X OFDX 3 u V4X C B L K HDI VDI 1+2 + 1 n u n H n u n u u 11 H u u lJ u u u u u 11 11 u u u u u Uu n n u u u u u u u u u u u u u u u u u u u u u u (2nd, 4th flELD) 318 310 332 336 CBLK HDI I n VDI n n n n n n n n n n n n n n n n n n n n n n n n n 1 5:6 518 5P 5~ 4 6 t++ 3 5 7 VIx n577f1579n58’J=’n n n n n n n n n n 1 n n n n n n n n n n n n V2X V3X V4X u u u 11 u u u u u u u u u 11 u u u u u u u u u llu u u u n u n u u u u u o u I u u u u u u u u u u u u u u u u u u u u VHIX VH3X OFDX 296 n u LZ93N61 CHARGE READ TIMING < NTSC > (ODD FIELD) 19 H 121 2(01 18 H HD VI x }~.r+. 1! 98 5~ -, 120 5~ w ~——.—~ 78 V2X 118 3;2; 898 I 78 118 V3X v.. VHIX ———?z,?”~ I I VH3X II OFDX (EVEN FIELD) HD 28Il H 281 H 121 2(o) =..———~ 120 v!. V2X V3X V4X I I 6a —, 1 2 L-— 8 128 +~ VHIX VH3X OFDX CHARGE READ TIMING < PAL > (Ist, 3rd FIELD) HD VIX V2X V3X V4X V HI X ,4 812 7M -1 — ——— VH3X OFDX (2nd, 4th FIELD) HD VI x V2X V3X V4X VHIX VH3X OFDX 332 H o 333 H 12WOI 120 _—— lm — ~ _—— — ?~ 118 322 ———— I 1 I 118 I —~—Y___ ~ 128 m i 28 —— I __— .——, I L ——wY— I LZ93N61 HORIZONTAL PULSE TIMING o (. )= PAL 120 HDI DOUT ,! 48 169 (193) FH T FH2 MCKI MCK, T SINV SESL SE L L ,’ L H W:h [~ 58 98 VI x 78 118 V2X 48 V3X V4X OFDX 298 108 6s 128 140 15s