TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Dual VCO/PLL Synthesizer With IF Up-Converter • • • • • • • • • S-Band LO Frequency Range: – TRF1121: 1500 to 2500 MHz – TRF1221: 1700 to 3600 MHz UHF LO Frequency Range: 250 to 350 MHz Input Frequency Range: 10 MHz to 70 MHz S-Band LO Phase Noise Typical 0.5 rms (100 Hz to 1 MHz) Output Power Range From –32 dBm to 0 dBm in 1 dB Steps (500-mVpp Diff Input) Minimum UHF LO Step Size of 50 kHz For TRF1121 and 62.5 kHz for TRF1221 Image Rejection: –50 dBc, Typical (20–40 MHz Tx IF Input) LO Leakage: –36 dBm, Typical 3rd Order IMD: < –60 dBc In Max Gain DESCRIPTION The TRF1121/TRF1221 are VHF-UHF upconverters with integrated UHF and S-band frequency synthesizers for radio applications in the 2GHz to 4 GHz range. The IC performs the first up-conversion and generates the local oscillator (LO) for the second up-conversion. The device uniquely integrates an image reject mixer, IF gain blocks, 5-bit gain control, and two complete phase locked loop (PLL) circuits including: VCOs, resonator circuit, varactors, dividers, and phase detectors. LPCC−48 PACKAGE (TOP VIEW) LO2ABPB LO2ATUN LO2ABPA LO2BBPB LO2BTUN LO2BBPA GND LO2OP LO2ON GND VCCLO2 GND SPECIFICATIONS 48 47 46 45 44 43 42 41 40 39 38 37 • • The TRF1121/TRF1221 are designed to function as part of complete 2.5-GHz and 3.5-GHz radio chipsets, respectively. In the chipset, the transmit chain operates as a double up converter from an IF frequency input (typically from a baseband modem's DAC) to an RF output frequency. The TRF1121/ TRF1221 performs the first up conversion from IF signals in the range of 10 MHz to 60 MHz to a second IF frequency in the range of 300 MHz to 360 MHz. The radio chipset features sufficient linearity, phase noise, and dynamic range to work in either single carrier or multi-carrier, line-of-sight or non-line-of-sight, standard (IEEE 802.16), or proprietary systems. Due to the modular nature of the chipset, it is ideal for use in systems that employ transmit or receive diversity. CP2O LD2 LF2 DATA CLK VCCD2 FR VCCD1 FRBP EN LF1 LD1 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 EXTLO2IP EXTLO2IN TXON IFOP VCCIF IFON GND GND GAIN[4] GAIN[3] GAIN[2] GAIN[1] 13 14 15 16 17 18 19 20 21 22 23 24 • Low Phase Noise Image Reject Upconverter Dual VCO/PLL For Double Up Conversion Architecture On-Chip VCO, Resonator and PLL Only Requires Off-Chip Loop Filter External S-Band VCO Option 5-Bit Transmit Level Control, 32 dB in 1 dB Steps CP1O LO1BPA LO1TUN LO1BPB VCCLO1 GND GND GND BBIN BBIP VCCUPC GAIN[0] FEATURES • • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BLOCK DIAGRAM The detailed block diagram and the pin-out of the ASIC are shown in Figure 1 and Table 1. VCCD1 VCCD2 GND Power Supply VCCIF Upconverter VCCUPC VarAtten IFOP IF2 BBIP 90o IFON BBIN TXON 90o GAIN[4] GAIN[3] GAIN[2] GAIN[1] Amplitude Select VCCLO1 N GAIN[0] LO1BPA LO1BPB CLK DATA EN Serial Interface Synth #1 Divider PFD/CP VCO#1 Synth #2 Divider − + + Synthesizer #1 N LO2OP VCO2A LO2ON PFD/CP VCO2B − + + Synthesizer #2 FR FRBP LD1 LF1 CP1O LO1TUN LF2 LD2 CP2O LO2ATUN LO2BTUN EXTLO2IP EXTLO2IN VCCLO2 LO2ABPB LO2ABPA LO2BBPA LO2BBPB 2 IF1 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 TERMINAL FUNCTIONS TERMINAL NO. NAME I/O TYPE Analog Synthesizer 2 charge pump output 1 CP2O O 2 LD2 O Digital 3 LF2 O Analog Lock detect filter capacitor for LO2, 0.01 µF typical 100 kΩ pull-up (1) 4 DATA I Digital Serial interface data input 5 CLK I Digital Serial interface clock input 6 VCCD2 I Power +5 V power for digital 7 FR I Analog 18-MHz reference clock input, HCMOS input. (DC level = 2.5 V) 8 VCCD1 I Power 9 FRBP O Analog Reference frequency bypass. Internally biased to 2.5 V. 10 EN I Digital 11 LF1 O Analog Lock detect filter capacitor for LO1, 0.01 µF typical 100 kΩ (1) 12 LD1 O Digital 13 CP1O O Analog Synthesizer 1 charge pump output 14 LO1BPA O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. 15 LO1TUN I Analog VCO synthesizer 1 tuning port 16 LO1BPB O Analog Bypass capacitor for LO1 0.1 µF (min) DCV =1.0 V 17 VCCLO1 I Power VCC for LO1 Power Ground 18, 19, 20, 29, GND 30, 37, 39, 42 Synthesizer 2 lock detect output, High is locked. +5 V power for digital Serial interface load enable (active high) Synthesizer 1 lock detect output, High is locked. 21 BBIN I Analog Baseband IF input (2 kΩ diff) negative, dc-coupled, Internal voltage is 4 V DC 22 BBIP I Analog Baseband IF input (2 kΩ diff) positive, dc-coupled, Internal voltage is 4 V DC 23 VCCUPC I Power +5V power Analog 24 GAIN[0] I Digital Gain control bit 0 (LSB) – Logic low induces 1-dB attenuation 25 GAIN[1] I Digital Gain control bit 1 – Logic low induces 2-dB attenuation 26 GAIN[2] I Digital Gain control bit 2 – Logic low induces 4-dB attenuation 27 GAIN[3] I Digital Gain control bit 3 – Logic low induces 8-dB attenuation 28 GAIN[4] I Digital Gain control bit 4 (MSB) – Logic low induces 16-dB attenuation 31 IFON O Analog IF analog output (100 Ω diff ) negative, dc-coupled, Internal voltage is 2.1 V DC 32 VCCIF I Power 33 IFOP O Analog IF analog output (100 Ω diff ) positive, dc-coupled, Internal voltage is 2.1 V DC 34 TXON I Digital 35 EXTLO2IN I Analog External input for LO2 (differential) negative and logic level for VCO select. 36 EXTLO2IP I Analog External input for LO2 (differential) positive and logic level for VCO select. 38 VCCLO2 I Power 40 LO2ON O Analog LO2 output (differential) Negative and positive VCC bias (+5 V) for LO buffer amp. 41 LO2OP O Analog LO2 output (differential) Positive and positive VCC bias (+5 V) for LO buffer amp. 43 LO2BBPA O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. 44 LO2BTUN I Analog LO2B Tune Port 45 LO2BBPB O Analog Bypass cap. for LO2B 0.1 µF (min) DCV = 1 V 46 LO2ABPA O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. 47 LO2ATUN I Analog LO2A tune port 48 LO2ABPB O Analog Bypass capacitor for LO2A 0.1 µF (min ) DCV = 1 V Back (1) DESCRIPTION +5 V power Analog IF amplifier enable active high VCC for LO2 A and B Back side of package has metal base that must be grounded for thermal and RF performance Current leakage on the order of 10µA through the capacitor or by any other means from either LF pin can cause false loss of lock signals. The two pullup resistors (R16 and R17) in Figure 23 reduce this sensitivity. 3 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE UNIT VCC DC supply voltage 0 to 5.5 V ICC DC supply current 270 mA Pin RF input power 20 dBm TJ Junction temperature 150 °C Pdiss Power dissipation 1.5 W Digital input voltage –0.3 to VCC+0.3 V Analog input voltage VCC V 25 °C/W θJC Thermal resistance junction-to-ambien (1) Tstg Storage temperature –40 to 105 °C Top Operating temperature –40 to 85 °C 260 °C Lead temperature, 40 Sec Max (1) Thermal resistance is junction-to-ambient assuming thermal pad with nine thermal vias under package metal base. See the recommended PCB layout. ELECTRICAL CHARACTERISTICS The characteristics listed in the following tables are at VCC = 5 V, TA = 25°C(unless otherwise noted) DC CHARACTERISTICS PARAMETER VCC ICC_TxON ICC_TxOFF DC supply voltage Supply current TEST CONDITIONS TA = 25°C MIN TYP 4.8 MAX 5.2 TA = 25°C, TXON enabled 180 TA = 25°C, TXON disabled 130 UNIT V mA UPCONVERTER CHARACTERISTICS Input signal 500 mVpp, VCC = 5 V, 25°C, IF1 = 26 MHz, IF2 = 325 MHz unless otherwise stated PARAMETER TEST CONDITIONS MIN MAX FIF2 Output frequency range VBB Input signal level Peak-to-peak differential ZIF1 Input IF1 differential impedance See Application Note TDB 2 kW Output power (maximum gain) Measured at IF2 (IF2OP,IF2ON) With 500-mVpp differential input to IF1(BBIP,BBIN) and GAIN[4:0] = 11111 0 dBm Output power (minimum gain) Measured at IF2 (IF2OP,IF2ON) With 500-mVpp differential input to IF1(BBIP,BBIN), GAIN[4:0] = 00000 –32 dBm ∆Gmax Gain flatness 300 MHz < IF2 < 330 MHz ∆PSTEP Gain step size OP1dB Output power a 1-dB gain compression GAIN[4:0] = 11111 12 OIP3 Output third order intercept For any gain setting 24 IR Image rejection IF1 = 15 to 45 MHz PLO1 LO1 leakage At GAIN[4:0] = 11111 decreases dB for dB as gain state is changed NF Input noise figure At max gain (GAIN[4:0]=11111), no worse then 1-dB degradation per 1 dB of attenuation ZIF2 Output RF impedance Differential 4 26 UNIT Input center frequency Pout See Figure 3 TYP FIF1 270 500 MHz 400 MHz 1000 mV ±0.3 0.7 1 dB 1.3 dB dBm dBm –30 dBc –36 dBm 27 dB 100 Ω TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 SYNTHESIZER #1 (UHF-BAND PLL) CHARACTERISTICS PARAMETER TEST CONDITIONS fRef Reference frequency See Table 7 fVCO1 Frequency TRF1121 and TRF1221 MIN TYP MAX 18 250 UNIT MHz 350 MHz £FRVCO1 Free running VO1 SSB phase noise at 100 kHz –115 dBc/Hz £LD LO1 Locked synthesizer 1 SSB phase noise at 10 kHz –115 dBc/Hz £LD LO1 Locked synthesizer 1 SSB phase noise at 100 kHz –115 fLD LO1 MSLO1 Locked synthesizer 1 integrated RMS phase noise 100 Hz to 1 MHz Tuning sensitivity For VLO1TUN > 2 V 30 TRF1121, 18-MHz reference input 50 TRF1221, 18-MHz reference input 62.5 ∆fLO1 Step Size RRS LO1 Reference spur rejection RFS LO1 Fractional spurs rejection dBc/Hz 0.2 deg 60 MHz/V kHz –70 dBc -60 dBc SYNTHESIZER #2 (S-BAND PLL) CHARACTERISTICS PARAMETER fRef Reference frequency TEST CONDITIONS MIN See Table 7 TYP 18 1500 2100 TRF1221 1700 2450 TRF1121 1700 2500 TRF1221 2400 3600 TRF1121 For VLO1TUN >2 V 150 350 TRF1221 For VLO1TUN >2 V 200 400 TRF1121 For VLO1TUN >2 V 200 400 TRF1221 For VLO1TUN >2 V 350 550 Output frequency, VCO#2A fLO2B Output frequency, VCO#2B MSLO2A Tuning sensitivity, VCO#2A MSLO2B Tuning sensitivity, VCO#2B ∆fLO2 Step size For 18-MHz ref input PLO2 Output power level Measured into a 100-Ω differential load at the LO1OP/N port -3 £FR Free running SSB phase noise at 100 kHz Measured into a 100-Ω differential load at the LO1OP/N port –100 Locked synthesizer SSB phase noise at 10 kHz £LD LO2 φLD LO2 RRS RFS Locked synthesizer SSB phase noise at 100 kHz 1 Measured into a 100-Ω differential load at the LO2OP/N port with loop filter set to 400 kHz nominal MHz MHz MHz/V MHz/V MHz dBm dBc/Hz – 102 –97 –100 –95 dBc/Hz Integrated RMS phase noise Locked, 100 Hz to 1 MHz 0.5 1 Deg LO2 Reference sideband suppression Measured into a 100-Ω differential load at the LO1OP/N port. PLL loop bandwidth ~ 400 kHz –65 –60 dBc At 1 MHz offset (Loop BW ~400 kHz) –50 –45 LO2 Fractional spur suppression At 2 MHz offset (Loop BW ~400 kHz) –65 –60 All others –70 –70 Harmonics suppression Measured into a 100-Ω differential load at the LO1OP/N port RLLO2 Output return loss Measured into a 100-Ω differential load at the LO1OP/N port –11 PextVCO Ext VCO input power RLextVCO Ext VCO port input ret. loss Differential mode –10 RH UNIT MHz TRF1121 fLO2A VCO2 MAX LO2 Zin extVCO Ext VCO port input impedance Differential mode –20 dBc dBc –16 dB –13 dBm –15 dB 100 Ω 5 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 INPUT REFERENCE REQUIREMENTS Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19 PARAMETER fRef TEST CONDITIONS TYP MAX 18 Temperature stability Customer requirements VFR Ref. source input voltage (1) HCMOS Output DCfref Reference Input Symmetry Waveform Duty Cycle tFR Reference source pulse rise time 10% to 90% of maximum voltage transition fFR Reference Phase Noise at 10 kΩ offset (1) MIN Reference frequency UNIT MHz PPM 4 4.5 40% 5 Vpp 60% 1 4 –153 –150 nsec dBc/Hz Note that for source peak-to-peak voltages of less than 4 V and dc-component other than 2.5-V degradation of the close-in phase noise may occur. For oscillators with no dc-component, a dc-voltage may be applied using a voltage divider (see the schematic) . AC TIMING, SERIAL BUS INTERFACE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CDI Clock to data invalid See Figure 7 10 ns DVC Data valid to clock See Figure 7 10 ns CPWH Clock pulse width high See Figure 7 50 ns CPWL Clock pulse width low See Figure 7 50 ns CEL Clock to enable low See Figure 7 10 ns ELC Enable low to clock See Figure 7 10 ns EPWH Enable pulse width See Figure 7 10 ns DIGITAL INTERFACE CHARACTERISTICS Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19 PARAMETER VIH Input high voltage VIL TEST CONDITIONS MIN TYP MAX UNIT 2.1 5 V Input low voltage 0 0.8 V IIH Input high current 0 50 µA IIL Input low current 0 –50 µA CI Input capacitance VOH Output logic 1 voltage ROH Output logic 1 impedance VOL Output low voltage 3 0 to 100-µA load 2.4 pF 3.6 18 0 to –100-µA load 0 V kΩ 0.4 V AUXILIARY AND CONTROL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V VCOenb External VCO enable voltage CMOS compatible Input. See Table 9 V VLD1 Lock detect voltage (PLL1) CMOS compatible output (active high). See Table 9 V VLD2 Lock Detect Voltage (PLL2) CMOS compatible output (active high). See Table 9 TXON EXTLO2IP EXTLO2IN EXTLO2IP EXTLO2IN EXTLO2IP EXTLO2IN 6 IF Amp Enable On-chip VCO2A selection On-chip VCO2B selection On-chip VCO2 selection IF Output On IF Output Off V High Low High Logic level applied to EXTLOIP and EXTLOIN pins to select either on chip VCO 2A or 2B. Pullup resistor = 200 Ω and pulldown resistor = 1 kΩ. Low Low High Logic Level applied to EXTLOIP and EXTLOIN pins to select the external VCO2 input Low Low TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 FREQUENCY PLAN The TRF1121/TRF1221 allow a variety of frequency plans. Figure 1 illustrates the allowable combinations of first and second IFs. However, due to the fact that the chip features image reject mixers, significant changes in the frequency plan can result in degradation of the image rejection as shown in Figure 2. LO leakage vs LO1 frequency is shown in Figure 3. In order to maintain maximum image rejection and LO suppression, a recommended frequency plan is TxIF1 = 26 MHz, TxIF2 = 325 MHz. 385 375 365 355 IF2 (MHz) 345 335 325 26 / 325 315 26 / 315 305 295 285 275 0 10 20 30 40 50 60 70 80 IF1 (MHz) Figure 1. Potential IF Combinations (TRF1121/1221) 7 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 0 Vin=500mVpp diff Max. Gain, T=25oC −10 Image Rejectin (dBc) −20 −30 −40 −50 LO2=270 MHz −60 LO2=299MHz LO2=320 MHz −70 5 15 25 35 45 55 65 75 Input Tx IF1 (MHz) RC1x21 IR Figure 2. . Image Rejection vs IF1, Transmit Chain 0 Vin=500mVpp diff T=25oC LO1 Leakage (dBm) −10 −20 −30 −40 −50 250 260 270 280 290 300 310 320 LO1 Frequency (MHz) Figure 3. LO1 Leakage at IF2 Port, Maximum Gain 8 330 340 350 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 TRANSMIT LEVEL CONTROL The TRF1121 / TRF1221 offer 32 dB of gain control through a five wire parallel bus. When driven with a 500-mVpp differential baseband IF signal, the transmit level can be programmed between –32 dBm and 0 dBm in 1 dB steps. 0 1 Vin=500mVpp diff T=25oC Pout −20 0 Gain Deviation from ideal −30 −40 −1 −50 LO1 Leakage at IF2 port −60 −2 IMD Level with two input tones at 250 mVpp diff. each Gain Deviation from Ideal (dB) Pout, LO Leakage (dBm) IMD Level (dBc) −10 −70 −80 −3 30 28 26 24 22 20 18 RC1x21 Po, PLO, IM3 (G) 16 14 12 Gain State 10 8 6 4 2 0 Figure 4. Output Power, LO Leakage and IMD Level vs Gain State −10 2 −20 1 Pout with Vin =500mVppdiff −30 −40 0 −1 LO1 Leakage at IF2 port −50 −60 −70 −40 −2 IMD Level with two input tones at 250mVppdiff each Pout (dBm) Pout, LO leakage (dBm), IMD Level (dBc) All measurements are made at Max. Gain −3 −4 −30 −20 −10 0 10 20 30 40 Temperature ( oC) 50 60 70 80 90 Figure 5. Power Level, IMD and LO1 Leakage Variation vs Temperature at Maximum Gain Setting 9 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 4 shows the output power, two-tone imtermodulation level, LO leakage and gain deviation from ideal vs gain state while Figure 5 shows the upconverter gain variation vs temperature. RC1x21 Output Power vs Input Voltage 14.00 12.00 Output Power (dBm) 10.00 8.00 Input at 26 MHz Output at 325 MHz T=25 degrees Input Impedance <800 ohms Input is sinusoidal Measured at max gain 6.00 4.00 2.00 0.00 −2.00 −4.00 −6.00 100 1000 10000 Differential Input Voltage (mVppd) NOTE: If left unconnected, the GAIN[0], GAIN[1], GAIN[2], GAIN[3], GAIN[4], and TXEN pins rest on logic Low. Figure 6. Output Power vs Input Voltage INTEGRATED SYNTHESIZERS PLL Programming Synthesizer #1 (UHF) and synthesizer #2 (S-band) are both integrated in the TRF1121/TRF1221. These two PLLs can be programmed via a 3-wire serial bus (CLK, DATA, and EN) from the baseband processor. The timing specs are given in the AC Timing table. Synthesizer #2 has a step size of 1 MHz, while Synthesizer #1 offers a step size of 50 kHz, both assuming an 18-MHz reference frequency. Different reference frequencies yield different step sizes, many of which may be non-integer. NOTE: If left unconnected, the DATA, CLK and EN pins rest on logic High. EN is level sensitive. 10 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 CDI Data DVC A[7]=MSB A[6] CEL A[4] A[5] D[0] LSB D[1] Clock EN ELC CPWH CPWL EPWH Figure 7. Serial Interface Timing Diagram Data is written to the PLLs according to the format in Figure 8. MSB Byte 1 LSB MSB Byte 2 LSB Address MSB Byte 3 LSB Data A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[15] D[14] 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 D[13] D[12] D[11] D[10] D[9] D[8] Synth #1 N divider Synth #2 N divider 0 0 0 0 D[7] D[6] D[5] D[4] Synth #1 S counter Synth #2 S counter 0 PS 0 0 0 D[3] D[2] D[1] D[0] Synth #1 F counter Synth #2 F counter 0 0 0 0 0 all other addresses reserved for future expansion Figure 8. Serial Interface Data Format The first eight bits are the appropriate address for the instruction set and the remaining 16 bits are the instructions. The data is 24 bits long (3 bytes). Byte 1 is the address with A[7] being the MSB and A[0] being the LSB. Byte 2 and 3 program the IC with synthesizer information and PS (Polarity Select Bit) information. D[15] is the MSB and D[8] the LSB. The PS bit selects which edge of the reference is used for frequency comparison. Improved spurious and phase noise is achieved by selecting the edge with the fastest rise or fall time. If PS = 1 the rising edge is used as the reference. If PS = 0, the falling edge is used. Figure 7 needs to be sent to the TRF1121 / TRF1221 to fully program the Synthesizers #1 and #2 and the PS bit. Once the synthesizers and the PS bit are fully programmed, the clock signal should be turned off to eliminate any clock-related spurious signals. The LO1 (UHF oscillator) frequency of oscillation is set by Equation 1: Fout REFIN 8 (N 3) S F [2 M] 18 (1) where M = 10 for TRF1121 and 8 for 1221 The TRF1121/TRF1221 contains two independent S-band VCOs and resonator circuits to provide additional frequency range from one IC, however only one VCO can be enabled at a time. These two VCOs are referred to as VCO2A and VCO2B (see the block diagram). The S-band PLL (LO2A or LO2B) frequency of oscillation is set by the following equation: Fout REFIN 8 (N 3) S F 18 (2) where F has a range of 0 to 17. Both N and S have ranges that are limited more by the LO range than by their digital count. 11 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Both synthesizers have a fractional architecture, which allows a high comparison frequency relative to the step size. The S-band PLL operates at a reference frequency of 18 MHz with a minimum phase accumulator frequency of 1 MHz. The UHF PLL operates at a 9-MHz reference with a minimum phase accumulator frequency of 0.5 MHz. The S-band PLL has a step size of 1 MHz and the UHF PLL has a step size of 50 kHz (TRF1121) or 62.5 kHz (TRF1221), when using an 18-MHz reference frequency. Different reference frequencies yield different step sizes, many of which are non-integer. If a different reference frequency is chosen, the step size is linearly related to the step size for 18 MHz. Step size = step size 18 MHz x [REF FREQ / 18 MHz] In addition to the normal reference spurious signals at the comparison frequency, fractional synthesizers have fractional spurs. The fractional spurs occur at an offset from the LO signal that is dependent on the difference between the LO frequency and integer multiples of the reference frequency. They occur on both sides of the LO carrier. The spur locations can be found by the following process: divide the LO frequency by the reference frequency, take the remainder (fraction to the right of the whole number) and multiply it by the reference frequency. This frequency is the difference between the actual LO frequency and an integer-multiple of the reference frequency. Fractional spurs occur at this frequency and the reference frequency minus this frequency. The following example best explains the process: if LO2 is set to 2206 MHz and we are using an 18 MHz reference frequency, then 2206/18 is 122.55556. The difference between the LO and 122 x 18 MHz is: 0.55556 x 18 MHz = 10 MHz The fractional spurs occur at this frequency offset (10 MHz) from LO2 and: 18–10 MHz or 8 MHz offset from LO2. The fractional spurious level varies with the offset from the LO since the spurs are attenuated by the loop filter response. The larger the offset from the LO, the lower the spur level. In general, spurs at offsets greater than 3 MHz or 4 MHz are below -75 dBc and are not a concern. The worst fractional spur levels occur when they are located at 1 MHz offsets from the LO2. (Note: the fractional spurs are offset from the LO2 by 1 MHz when the difference between the LO2 and an integer multiple of the reference frequency is 1 MHz or 17 MHz). Although both synthesizers have fractional spurs, for most applications the spurious signals from the UHF synthesizer can be ignored because the LO1 spurs are filtered by the IF2 filter and attenuated by frequency dividers that are located after the LO1 generation. In some frequency plans it is possible to offset LO1 and LO2 to avoid worst case fractional spurs (at 1-MHz offsets) on LO2. 12 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 VCO Tuning Characteristics The TRF1121 / TRF1221 have internal VCOs with the following frequency vs tuning voltage characteristics. 2500 700 2250 600 500 Frequency 1750 400 1500 300 Mod Sense (MHz/V) Frequency (MHz) 2000 Mod Sense 1250 200 −40 ºC +25 ºC +85 ºC 1000 100 1 1.5 2 2.5 3 3.5 Tuning Voltage (V) 4 4.5 5 Figure 9. TRF1121 LO2A Frequency LO2ATUN Voltage 2750 700 −40 ºC +25 ºC +85 ºC 2500 600 500 Frequency 2000 400 1750 300 Mod Sense 1500 Mod Sense (MHz/V) Frequency (MHz) 2250 200 1250 100 1 1.5 2 2.5 3 3.5 4 4.5 5 Tuning Voltage (V) Figure 10. TRF1121 LO2B Frequency vs LO2BTUN Voltage 13 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 400 110 −40 ºC +25 ºC +85 ºC 350 90 70 250 50 Mod Sense 200 30 150 Mod Sense (MHz/V) Frequency (MHz) Frequency 300 10 1 1.5 2 2.5 3 Tuning Voltage (V) 3.5 4 4.5 5 Figure 11. TRF1121 LO1 Frequency vs LO1TUN Voltage 2750 700 −40 ºC +25 ºC +85 ºC 2500 600 500 Frequency 2000 400 1750 300 Mod Sense 1500 200 1250 100 1 1.5 2 2.5 3 3.5 4 4.5 Tuning Voltage (V) Figure 12. TRF1221 LO2A Frequency vs LO2ATUN Voltage 14 5 Mod Sense (MHz/V) Frequency (MHz) 2250 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 4000 900 −40 ºC +25 ºC +85 ºC 3750 800 700 Frequency 3250 600 3000 500 2750 400 Mod Sense 2500 300 2250 200 2000 Mod Sense (MHz/V) Frequency (MHz) 3500 100 1 1.5 2 2.5 3 3.5 4 4.5 5 Tuning Voltage (V) Figure 13. TRF1221 LO2B Frequency vs LO2BTUN Voltage 400 110 350 90 70 250 50 Mod Sense − MHz/V Frequency − MHz Frequency 300 Mod Sense 200 30 −40C 25C 85C 150 10 1 1.5 2 2.5 3 3.5 4 4.5 5 Tuning Voltage − V Figure 14. TRF1221 LO1 Frequency vs LO1TUN Voltage 15 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Phase Noise The TRF1121 / TRF1221 achieve superior phase noise performance with on-chip resonators and varactors. It is designed to meet the phase noise requirements of both single-carrier and multi-carrier systems. Due to the chip architecture, the phase noise and spurious performance of the LO1 PLL is about 15 dB better than the LO2 PLL. The typical phase noise of the TRF1121 and TRF1221 S-band PLL (LO2) with the PLL locked is shown in Figure 15 and Figure 16 respectively. The phase noise plots of the TRF1221 S-band PLL at the min and max range are shown in Figure 20 and Figure 21 respectively. These plots were taken at room temperature and typical voltage conditions. Figure 15. TRF1121 Typical Integrated LO1 (S-band) Phase Noise is 0.35 rms (100 Hz to 1 MHz) When designing full duplex radios that employ narrow T to R spacing, one must consider impact of wide-band phase noise since it can degrade Rx sensitivity. (See Application Note TDB). Figure 17 shows typical wide-band composite phase noise performance of the combination of the two integrated PLLs. At 50-MHz offset typical performance is –145 dBc/Hz. 16 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 16. TRF1221 Typical Integrated LO2 (S-band) Phase Noise is 0.65 rms (100 Hz to 1 MHz) −60 −70 Phase Noise (dBc/Hz) −80 −90 −100 −110 −120 −130 −140 −150 −160 1.0E+02 RC1121 cmpPhsNs 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency Offset (Hz) Figure 17. TRF1121 Typical Wide-Band Composite PLL Phase Noise Profile 17 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 18 shows reference spurs of the S-band (LO2) locked synthesizer and Figure 19 shows the fractional spurs of the same LO at 2-MHz offset from the carrier Figure 18. TRF1121 Reference Spurs on LO2 Output Figure 19. TRF1121 Fractional Spurs on LO2 (2-MHz Offset) 18 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 20. Phase Noise - 2750 MHz 19 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 21. Phase Noise - 3600 MHz For systems that demand tighter phase noise performance than that offered by Texas Instruments internal VCOs, a provision exists for connection of an external VCO. Texas Instruments PLL still locks the VCO to the reference frequency and the ASIC provides an external tuning voltage that drives the VCO. 20 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 APPLICATION INFORMATION A typical application schematic is shown in Figure 23, while a mechanical drawing of the package outline (LPCC Quad 7 mm × 7 mm, 48 pin) is presented in Figure 24. The recommended PCB layout mask is shown in Figure 25. PCB material recommendations are shown in , Table 1and Figure 22. Table 1. PCB Recommendations Board material Board material core thickness FR4 10 mil Copper thickness (starting) 1 oz Prepreg thickness 8 mil Recommended number of layers Via plating thickness Final plate Final board thickness 4 0.5 oz White immersion tin 33–37 mil Figure 22. PCB Construction and Via Cross Section 21 TRF1121 TRF1221 www.ti.com U1 TRF1121/1221 SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 23. Typical Application Schematic 22 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 Figure 24. ASIC Package Outline 23 TRF1121 TRF1221 www.ti.com SLWS170A – APRIL 2005 – REVISED DECEMBER 2005 5.50 0.50 TYP 0.60 TYP 0.45 TYP PIN 1 1.27 TYP 5.50 1.27 TYP 5.30 DIA 0.38 TYP 0.25 TYP 5.30 SOLDER MASK: NO SOLDERMASK UNDER CHIP, ON LEAD PADS OR ON GROUND CONNECTIONS. 16 VIA HOLES, EACH 0.38 mm. DIMENSIONS in mm Figure 25. PCB Layout Mask for TRF1121/TRF1221 24 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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