SP7653 ® Preliminary PowerBlox Blox Wide Input Voltage Range, 1.3MHz, Buck Regulator TM FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SP7653 DFN PACKAGE 7mm x 4mm 2.5V to 20V Step Down Achieved Using Dual Input Output Voltage down to 0.8V 3A Output Capability Built in Low RDSON Power Switches (40 mΩ typical) Highly Integrated Design, Minimal Components 1.3MHz Fixed Frequency Operation UVLO Detects Both VCC and VIN Over Temperature Protection Short Circuit Protection with Auto-Restart Wide BW Amp Allows Type II or III Compensation Programmable Soft Start Fast Transient Response High Efficiency: Greater than 95% Possible Asynchronous Start-Up into a Pre-Charged Output Small 7mm x 4mm DFN Package PGND 1 26 LX TOP VIEW PGND 2 Heatsink Pad 1 Connect to Lx PGND 3 25 LX 24 LX GND 4 23 LX VFB 5 2 2 VCC COMP 6 21 GND Heatsink pad 2 Connect to GND UVIN 7 20 GND GND 8 19 GND SS 9 18 BST VIN 10 17 NC Heatsink pad 3 Connect to VIN VIN 11 16 LX VIN 12 15 LX VIN 13 14 LX Now Available in Lead Free Packaging DESCRIPTION The SP7653 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be especially attractive for dual supply, 12V to 20V distributed power systems stepped down with 5V used to power the controller. This lower VCC voltage minimizes power dissipation in the part and is used to drive the top switch. The SP7653 is designed to provide a fully integrated buck regulator solution using a fixed 1.3MHz frequency, PWM voltage mode architecture. Protection features include Under Voltage Lock Out (UVLO), thermal shutdown and output short circuit protection. The SP7653 is available in the space saving DFN package. TYPICAL APPLICATION CIRCUIT L1: IHLP2525CZER2R2M01 2.2uH, Irate =8A U1 SP7653 1 2 RZ2 CZ2 3 1.5nF 38.3k, 1% 4 C P1 5 3.3pF 6 7 CF1 100pF 8 9 10 CSS 22nF 11 12 13 VIN 12V C1,C5 CERAMIC X5R GND Date: 03/25/05 LX P GND LX P GND LX GND LX V FB VCC COMP GND UV IN GND GND GND SS BST V IN NC V IN LX V IN LX V IN LX fs=1.3MHz R3 200k,1% C1 22uF 16V P GND 1 C5 2 22uF 16V 3 R4 100k,1% 26 25 24 23 DCR=18mOhm C3 CERAMIC X5R 22 21 20 VOUT C VCC 2.2uF 17 16 15 14 EN BYP CZ3 820pF VOUT 3.30V 0-3A R1 68.1k,1% R2 21.5k,1% R BST 5.11, 1% C BST 1uF D BST SD101AWS Notes: 5 4 U1 Bottom-Side Layout should have three Contacts which are isolated from one another: QT Contact, QB Drain Contact, and Controller GND Contact. ALL RESISTORS & CAPACITORS SIZE 0603 UNLESS OTHERWISE SPECIFIED. SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 1 RZ3 158,1% GND2 18 GND C2 0.1uF 47uF 6.3 V 19 U2 SPX5205 VIN C3 © Copyright 2005 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. GH ....................................................................... -0.3V to Boost+0.3V GH-SWN ......................................................................................... 7V All other pins .......................................................... -0.3V to VCC+0.3V VCC .................................................................................................. 7V VIN ........................................................................................................................................... 20V ILX ............................................................................................................................................... 5A Boost ............................................................................................. 27V Boost-SWN ....................................................................... -0.3V to 7V SWN ................................................................................... -1V to 20V Storage Temperature .................................................. -65°C to 150°C Power Dissipation ...................................... Internally Limited via OTP ESD Rating .......................................................................... 2kV HBM Thermal Resistance ϑJC .................................................................................... 5°C/W ELECTRICAL SPECIFICATIONS Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, Boost=LX + 5V, LX = GND = 0Volts, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V. The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS 1.5 3 mA CONDITIONS QUIESCENT CURRENT VCC Supply Current (No switching) VCC Supply Current (switching) 8 BST Supply Current (No switching) 0.2 BST Supply Current (switching) 4.0 mA 0.4 VFB =0.9V ♦ VFB =0.9V mA mA ♦ PROTECTION: UVLO VCC UVLO Start Threshold 4.00 4.25 4.5 V VCC UVLO Hysteresis 100 200 300 mV UVIN Start Threshold 2.3 2.5 2.65 V UVIN Hysteresis 200 300 400 mV 1 µA UVIN Input Current ♦ UVIN= 3.0V ERROR AMPLIFIER REFERENCE Error Amplifier Reference 0.792 0.800 0.808 V Error Amplifier Reference Over Line and Temperature 0.788 0.800 0.812 V 2X Gain Config., Measure VFB; VCC =5 V, T=25ºC ♦ Error Amplifier Transconductance 6 mA/V Error Amplifier Gain 60 dB No Load COMP Sink Current 150 µA VFB =0.9V, COMP= 0.9V COMP Source Current 150 µA VFB =0.7V, COMP= 2.2V VFB Input Bias Current 50 nA VFB = 0.8V Internal Pole 4 MHz COMP Clamp 2.5 V COMP Clamp Temp. Coefficient -2 mV/ºC Date: 03/25/05 200 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 2 VFB =0.7V, TA=25ºC © Copyright 2005 Sipex Corporation ELECTRICAL SPECIFICATIONS Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, Boost=LX + 5V, LX = GND = 0Volts, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V. The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH Ramp Amplitude 0.92 1.1 1.28 V RAMP Offset 1.1 V RAMP offset Temp. Coefficient -2 mV/ºC GH Minimum Pulse Width 90 Maximum Controllable Duty Ratio 92 Maximum Duty Ratio 100 Internal Oscillator Ratio 1.1 180 97 1.3 1.5 ns TA = 25ºC, RAMP COMP until GH starts Switching ♦ % Maximum Duty Ratio Measured just before pulsing begins % Valid for 20 cycles MHz ♦ TIMERS: SOFTSTART SS Charge Current: 10 SS Discharge Current: µA 1 mA ♦ Fault Present, SS = 0.2V V ♦ Measured VREF (0.8V) VFB PROTECTION: Short Circuit & Thermal Short Circuit Threshold Voltage 0.2 0.25 0.3 Hiccup Timeout 200 ms VFB = 0.5V Number of Allowable Clock Cycles at 100% Duty Cycle 20 Cycles Minimum GL Pulse After 20 Cycles 0.5 Cycles VFB = 0.7V Thermal Shutdown Temperature 145 ºC VFB = 0.7V Thermal Recovery Temperature 135 ºC Thermal Hysteresis 10 ºC High Side Switch RDSON 40 mΩ VCC = 5V ; IOUT = 3A TAMB = 25ºC Synchronous Lowside Switch RDSON 40 mΩ VCC = 5V ; IOUT = 3A TAMB = 25ºC OUTPUT: POWER STAGE Maximum Output Current Date: 03/25/05 3 A SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 3 © Copyright 2005 Sipex Corporation PIN DESCRIPTION Pin # Pin Name Description 1-3 PGND Ground connection for the synchronous rectifier 4,8,19-21 GND Ground Pin. The control circuitry of the IC and lower power driver are referenced to this pin. Return separately from other ground traces to the (-) terminal of COUT. 5 VFB Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode. 6 COMP Output of the Error Amplifier. It is internally connected to the inverting input of the PWM comparator. An optimal filter combination is chosen and connected to this pin and either ground or VFB to stabilize the voltage mode loop. 7 UVIN 9 SS Soft Start. Connect an external capacitor between SS and GND to set the soft start rate based on the 10µA source current. The SS pin is held low via a 1mA (min) current during all fault conditions. 10-13 VIN Input connection to the high side N-channel MOSFET. Place a decoupling capacitor between this pin and PGND. 14-16,23-26 LX Connect an inductor between this pin and VOUT 17 NC No Connect UVLO input for Vin voltage. Connect a resistor divider between VIN and UVIN to set minimum operating voltage. THEORY OF OPERATION General Overview The SP7653 is a fixed frequency, voltage mode, synchronous PWM regulator optimized for high efficiency. The part has been designed to be especially attractive for high input voltages of 2.5V to 20V. The SP7653 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is enabled during start up, to prohibit the low side switch from pulling down the output until the high side switch has attempted to turn on. Second, a 100% duty cycle timeout ensures that the low side switch is periodically enhanced during extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the Boost capacitor during very large duty ratios. The heart of the SP7653 is a wide bandwidth transconductance amplifier designed to accommodate Type II and Type III compensation schemes. A precision 0.8V reference, present on the positive terminal of the error amplifier permits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a 1.1V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp, and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to 1.3MHz. Date: 03/25/05 The SP7653 also contains a number of valuable protection features. Programmable VIN UVLO allows the user to set the exact value at which the conversion voltage can safely begin down conversion, and an internal VCC UVLO which ensures that the controller itself has enough voltage to properly operate. Other protection fea- SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 4 © Copyright 2005 Sipex Corporation THEORY OF OPERATION Thermal and Short-Circuit Protection tures include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP7653 is forced into an idle state where the output drivers are held off for a finite period before a restart is attempted. Because the SP7653 is designed to drive large output current, there is a chance that the power converter will become too hot. Therefore, an internal thermal shutdown (145°C) has been included to prevent the IC from malfunctioning at extreme temperatures. Soft Start “Soft Start” is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. In a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor: A short-circuit detection comparator has also been included in the SP7653 to protect against an accidental short at the output of the power converter. This comparator constantly monitors the positive and negative terminals of the error amplifier, and if the VFB pin falls more than 250mV (typical) below the positive reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP7653 is capable of detecting shortcircuit faults throughout the duration of soft start as well as in regular operation. IVIN = COUT * (DVOUT / DTSOFT-START) The SP7653 provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 10uA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, the excess source can be redefined as: Handling of Faults: Upon the detection of power (UVLO), thermal, or short-circuit faults, the SP7653 is forced into an idle state where the SS and COMP pins are pulled low and both switches are held off. In the event of UVLO fault, the SP7653 remains in this idle state until the UVLO fault is removed. Upon the detection of a thermal or short-circuit fault, an internal 200ms timer is activated. In the event of a short-circuit fault, a re-start is attempted immediately after the 200ms timeout expires. Whereas, when a thermal fault is detected the 200ms delay continuously recycles and a re-start cannot be attempted until the thermal fault is removed and the timer expires. IVIN = COUT *[ (DVOUT *10µA) /(CSS * 0.8V)] Under Voltage Lock Out (UVLO) The SP7653 contains two separate UVLO comparators to monitor the bias (VCC) and conversion (VIN) voltages independently. The VCC UVLO threshold is internally set to 4.25V, whereas the VIN UVLO threshold is programmable through the UVIN pin. When the voltage on the UVIN pin is greater than 2.5V, the SP7653 is permitted to start up pending the removal of all other faults. Both the VCC and VIN UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault. Date: 03/25/05 Error Amplifier and Voltage Loop The heart of the SP7653 voltage error loop compensation is a high performance, wide bandwidth transconductance amplifier. Because of the amplifier’s current limited (+/-150µA) transconductance, there are many ways to compensate the voltage loop or to control the COMP SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 5 © Copyright 2005 Sipex Corporation THEORY OF OPERATION pin externally. If a simple, single pole-single zero response is desired, then compensation can be as simple as an RC circuit to ground. If a more complex compensation is required, then the amplifier has enough bandwidth (45° at 4 MHz) and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase margins at cross over frequencies greater than 50kHz. VBST GH Voltage VSWN V(VCC) GL Voltage 0V V(VIN) The common mode output of the error amplifier is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between 1.1V and 2.2V to ensure proper 0% to 100% duty cycle capability. The voltage loop also includes two other very important features. One is an asynchronous start up mode. Basically, the synchronous rectifier cannot turn on unless the high side switch has attempted to turn on or the SS pin has exceeded 1.7V. This feature prevents the controller from “dragging down” the output voltage during startup or in fault modes. The second feature is a 100% duty cycle timeout that ensures synchronized refreshing of the Boost capacitor at very high duty ratios. In the event that the high side NFET is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 21st cycle. This forces GL to rise for the cycle, in turn refreshing the Boost capacitor. The boost capacitor is used to generate a high voltage drive supply for the high side switch, which is 5V above VIN. SWN Voltage -0V -V(Diode) V V(VIN)+V(VCC) BST Voltage V(VCC) TIME Setting Output Voltages The SP7653 can be set to different output voltages. The relationship in the following formula is based on a voltage divider from the output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V. Standard 1% metal film resistors of surface mount size 0603 are recommended. Vout = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ ( Vout / 0.80V ) – 1 ] Power MOSFETs The SP7653 contains a pair of integrated low resistance N-channel switches designed for up to 3A. Care should be taken to de-rate the output current based on the thermal conditions in the system such as ambient temperature, airflow and heat sinking. Maximum output current could be limited by thermal limitations of a particular application by taking advantage of the integrated-over-temperature protective scheme employed in the SP7653. The SP7653 incorporates a built-in overtemperature protection to prevent internal overheating. Date: 03/25/05 Where R1 = 68.1KΩ and for Vout = 0.80V setting, simply remove R2 from the board. Furthermore, one could select the value of the R1 and R2 combination to meet the exact output voltage setting by restricting the resistance range of R1 such that 50KΩ < R1 < 100KΩ for overall system loop stability. SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 6 © Copyright 2005 Sipex Corporation APPLICATIONS INFORMATION Inductor Selection There are many factors to consider in selecting the inductor including core material, inductance vs. frequency, current handling capability, efficiency, size and EMI. In a typical SP7653 circuit, the inductor is chosen primarily for value, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. The inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. I PEAK = I OUT (max) + and provide low core loss at the high switching frequency. Low cost powdered iron cores have a gradual saturation characteristic but can introduce considerable AC core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, although more expensive, have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss while the designer is only required to prevent saturation. In general, ferrite or molypermalloy materials are a better choice for all but the most cost sensitive applications. The switching frequency and the inductor operating point determine the inductor value as follows: L= Optimizing Efficiency The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetic vendor. Proper inductor selection can affect the resulting power supply efficiency by more than 15%! VOUT (V IN (max) − VOUT ) VIN (max) FS Kr I OUT ( max) where: fS = switching frequency Kr = ratio of the AC inductor ripple current to the maximum output current The peak to peak inductor ripple current is: I PP = I PP 2 The copper loss in the inductor can be calculated using the following equation: VOUT (VIN (max) − VOUT ) PL( Cu) = I L2 ( RMS ) RWINDING VI N (max) FS L where IL(RMS) is the RMS inductor current that can be calculated as follows: Once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency requirements. The core must be large enough not to saturate at the peak inductor current Date: 03/25/05 IL(RMS) = IOUT(max) 1 + 1 3 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 7 ( IPP IOUT(max) ) 2 © Copyright 2005 Sipex Corporation APPLICATIONS INFORMATION Output Capacitor Selection FS = Switching Frequency The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP7653 adjusts the inductor current to the new value. D = Duty Cycle COUT = Output Capacitance Value Input Capacitor Selection The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle VOUT/VIN. More accurately the current wave form is trapezoidal, given a finite turn-on and turn-off, switch transition slope. Most of this current is supplied by the input bypass capacitors. The RMS current handling capability of the input capacitors is determined at maximum output current and under the assumption that the peak-to-peak inductor ripple current is low, it is given by: ICIN(RMS) = IOUT(max) √D(1 - D) In order to maintain VOUT ,the capacitance must be large enough so that the output voltage is helped up while the inductor current ramps to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the current. Because of the fast transient response and inherent 100%/0% duty cycle capability provided by the SP7653 when exposed to output load transient, the output capacitor is typically chosen for ESR, not for capacitance value. The worse case occurs when the duty cycle D is 50% and gives an RMS current value equal to IOUT/2. Select input capacitors with adequate ripple current rating to ensure reliable operation. The output capacitor’s ESR, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by: The power dissipated in the input capacitor is: 2 PCIN = ICIN ( rms ) R ESR ( CIN ) RESR ≤ ∆VOUT IPK-PK This can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. The input voltage ripple primarily depends on the input capacitor ESR and capacitance. Ignoring the inductor ripple current, the input voltage ripple can be determined by: where: ∆VOUT = Peak to Peak Output Voltage Ripple IPK-PK = Peak to Peak Inductor Ripple Current The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows: ∆ VIN = I out (max) RE SR (CIN ) + ( ∆VOUT = IPP (1 – D) COUTFS Date: 03/25/05 ) 2 I OUT ( MAX )VOUT (VI N − VOUT ) FS C INV IN 2 + (IPPRESR)2 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 8 © Copyright 2005 Sipex Corporation APPLICATIONS INFORMATION The first step of compensation design is to pick the loop cross over frequency. High cross over frequency is desirable for fast transient response, but often jeopardizes the power supply stability. Cross over frequency should be higher than the ESR zero but less than 1/5 of the switching frequency or 60kHz. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by: The capacitor type suitable for the output capacitors can also be used for the input capacitors. However, exercise extra caution when tantalum capacitors are used. Tantalum capacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are connected “live” to low impedance power sources. Although tantalum capacitors have been successfully employed at the input, it is generally not recommended. 2π COUT RESR The next step is to calculate the complex conjugate poles contributed by the LC output filter, Loop Compensation Design The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter output stage, and feedback resistor divider. In order to cross over at the desired frequency cut-off (FCO), the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. The goal of loop compensation is to manipulate loop frequency response such that its cross-over gain at 0db, results in a slope of -20db/dec. + _ 1 ƒP(LC) = 2π L COUT When the output capacitors are of a Ceramic Type, the SP7653 Evaluation Board requires a Type III compensation circuit to give a phase boost of 180° in order to counteract the effects of an under damped resonance of the output filter at the double pole frequency. Type III Voltage Loop Compensation GAMP (s) Gain Block VREF (Volts) 1 ƒZ(ESR) = PWM Stage GPWM Gain Block Output Stage GOUT (s) Gain Block VIN (SRz2Cz2+1)(SR1Cz3+1) (SRESRCOUT+ 1) VRAMP_PP SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1) [S^2LCOUT+S(RESR+RDC) COUT+1] VOUT (Volts) Notes: RESR = Output Capacitor Equivalent Series Resistance. RDC = Output Inductor DC Resistance. VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> RESR & RDC Voltage Feedback GFBK Gain Block R2 VFBK (Volts) (R1 + R2) or VREF VOUT SP7653 Voltage Mode Control Loop with Loop Dynamic Definitions: RESR = Output Capacitor Equivalent Series Resistance RDC = Output Inductor DC Resistance RRAMP_PP = SP7653 internal RAMP Amplitude Peak to Peak Voltage Conditions: CZ2 >> Cp1 and R1 >> Rz3 Output Load Resistance >> RESR and RDC Date: 03/25/05 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 9 © Copyright 2005 Sipex Corporation APPLICATIONS INFORMATION Gain (dB) Error Amplifier Gain Bandwidth Product Condition: C22 >> CP1, R1 >> RZ3 1/6.28 (RZ3) (CZ3) 1/6.28 (RZ2) (CP1) 1/6.28 (R1) (CZ2) 1/6.28 (R1) (CZ3) 1/6.28(R22) (CZ2) 20 Log (RZ2/R1) Frequency (Hz) Bode Plot of Type III Error Amplifier Compensation. CP1 RZ3 CZ3 CZ2 RZ2 VOUT R1 68.1k, 1% 5 VFB R SET + + - 0.8V R SET 6 COMP CF1 -0.8V)(kΩ) =54.48/ (V OUT Type III Error Amplifier Compensation Circuit Date: 03/25/05 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 10 © Copyright 2005 Sipex Corporation PACKAGE: 26 PIN DFN D (7 x 4 mm) E Top View A A3 K Side View A1 e b L E2 J D2 SYMBOL A A1 A3 b D D2 D3 e E E2 K J L 26 Pin DFN MIN NOM 0.800 0.850 0.000 0.178 0.203 0.170 0.220 6.950 7.000 2.000 2.050 1.780 1.830 0.500 BSC 3.950 4.000 2.730 2.780 0.340 0.390 0.200 0.250 0.350 0.400 D2 D3 Bottom View MAX 0.900 0.050 0.228 0.270 7.050 2.100 1.880 4.050 2.830 0.440 0.300 0.450 Note: Dimensions in (mm) Date: 03/25/05 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 11 © Copyright 2005 Sipex Corporation ORDERING INFORMATION Part Number Temperature Package SP7653ER/TR ......................................... -40°C to +85°C ................................. 26 Pin 7 X 4 DFN SP7653ER-L/TR ..................................... -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN /TR = Tape and Reel Pack quantity is 3,000 DFN. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 03/25/05 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator 12 © Copyright 2005 Sipex Corporation