SL4053B . Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS The SL4053B analog multiplexer/demultiplexer is digitally controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V peak-to-peak can be achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V, a VCC - VEE of up to 13 V can be controlled; for VCC - VEE level differences above 13V a VCC - GND of at least 4.5V is required). These multiplexer circuits dissipate extremely low quiescent power over the full VCC -GND and VCC - VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1”is present at the ENABLE input terminal all channels are off. The SL4053B is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an enable input. Each control input selects one of a pair of channels which are connected in a singlepole double-throw configuration. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4053BN Plastic SL4053BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Triple Single-Pole, Double-Position Plus Common Off FUNCTION TABLE Control Inputs Enable PIN 16 =VCC PIN 7 = VEE PIN 8 = GND Select System Logic Semiconductor Channels C B A L L L L Z0 Y0 X0 L L L H Z0 Y0 X1 L L H L Z0 Y1 X0 L L H H Z0 Y1 X1 L H L L Z1 Y0 X0 L H L H Z1 Y0 X1 L H H L Z1 Y1 X0 L H H H Z1 Y1 X1 H X X X X = don’t care SLS ON None SL4053B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA I ROH * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Multiplexer Switch Input Current Capability Output Load Resistance * Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C - 25 mA 100 - Ω In certain applications, the external load-resistor current may include both VCC and signal-line components. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused digital pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. SLS System Logic Semiconductor SL4053B DC ELECTRICAL CHARACTERISTICS Digital Section VCC Guaranteed Limit V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit VIS=VCC thru 1kΩ VEE=GND IIS<2µA on all OFF Chanels RL=1kΩ to GND 5 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V Maximum Low -Level Input Voltage, ChannelSelect or Enable Inputs VIS=VCC thru 1kΩ VEE=GND IIS<2µA on all OFF Chanels RL=1kΩ to GND 5 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V IIN Maximum Input Leakage Current, Channel-Select or Enable Inputs VIN=VCC or GND 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND 5 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA Symbol Parameter VIH Minimum High-Level Input Voltage, ChannelSelect or Enable Inputs VIL Test Conditions DC ELECTRICAL CHARACTERISTICS Analog Section VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit RON Maximum “ON” Resistance VEE=GND=0 VIS = GND to VCC 5 10 15 800 310 200 1050 400 240 1300 550 320 Ω ∆RON Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VEE=GND=0 5 10 15 - 10 15 5 - Ω IOFF Maximum Off- Channel Leakage Current, Any One Channel VEE=GND=0 18 ±100 ±100 ±1000 nA Maximum Off- Channel Leakage Current, Common Channel VEE=GND=0 18 ±100 ±100 ±1000 SLS System Logic Semiconductor SL4053B AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=20.0 ns) VCC Symbol Parameter Guaranteed Limit V ≥ -55 °C ≤ 25 °C ≤ 125 °C Unit tPLH, t PHL Maximum Propagation Delay , Analog Input to Analog Output (Figure 1) RL=200kΩ 5 10 15 60 30 20 60 30 20 120 60 40 ns tPLZ, t PHZ Maximum Propagation Delay , Address to Analog Output (Figure 2) RL=10kΩ VEE=GND=0 5 10 15 720 320 240 720 320 240 1440 640 480 ns VEE=-5V 5 450 450 900 Maximum Propagation Delay, Enable to Analog Output (Figure 2) RL=10kΩ VEE=GND=0 5 10 15 720 320 240 720 320 240 1440 640 480 VEE=-10V 5 400 400 800 Maximum Propagation Delay, Enable to Analog Output (Figure 2) RL=10kΩ VEE=GND=0 5 10 15 450 210 160 450 210 160 900 420 320 VEE=-10V 5 300 300 600 - 7.5 7.5 7.5 pF pF tPLZ, tPZL tPHZ, tPZH CIN Maximum Input Capacitance, Channel-Select or Enable Inputs CI/O Maximum Capacitance VEE=GND=-5V CIS 5 - 5 - COS 5 - 9 - Feedthrough CIOS 5 - 0.2 - SLS ns ns System Logic Semiconductor SL4053B ADDITIONAL APPLICATION CHARACTERISTICS Symbol BW Parameter Maximum OnChannel Bandwidth or Minimum Frequency Response (-3db) Test Conditions Feedthrough Frequency (All Channels OFF) Limit* V V 25 °C Unit 10 5* 30 MHz 10 5* 60 10 5* 8 10 5* 8 VOS at Common OUT/IN VEE=GND RL=1kΩ 20 log(VOS/VIS)=-40db VOS at Common OUT/IN VOS at Any Channel (-40db) Signal Crosstalk Frequency VIS VEE=GND RL=1kΩ 20 log(VOS/VIS)=-3db VOS at Any Channel (-40db) VCC VEE=GND RL=1kΩ 20 log(VOS/VIS)=-40db Between any 2 Sections : In Pin 2, Out Pin 14 In Pin 15, Out Pin 14 2.5 6 THD Total Harmonic Distortion VEE=GND fIS=1kHz sine wave 5 10 15 2* 3* 5* 0.3 0.2 012 % - Address-or Enable to Signal Crosstalk VEE=GND RL=10kΩ** tr,t f=20ns Square Wave 10 - 65 mv (peak) * Peak-to-peak voltage symmetrical about (VDD-VEE)/2 **Both ends of channel SLS System Logic Semiconductor SL4053B Figure 1. Switching Waveforms Figure 2. Switching Waveforms EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor