SL4069UB Hex Inverter High-Voltage Silicon-Gate CMOS The SL4069UB types consist of six inverter circuits. These devices are intended for all general-purpose inverter applications where the medium-power TTL-drive and logic-level-conversion capabilities of circuits such as the SL4049UB Hex Inverter/Buffers are not required. Each of the six inverters is a single stage • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 0.5 V min @ 5.0 V supply 1.0 V min @ 10.0 V supply 1.0 V min @ 15.0 V supply ORDERING INFORMATION SL4069UBN Plastic SL4069UBD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Output A Y L H H L PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor SL4069UB MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg Storage Temp erature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC DC Supply Voltage (Referenced to GND) VIN, VOUT TA Parameter DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL4069UB DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VIH Minimum High-Level Input Vo ltage VOUT=0.5V VOUT=1.0 V VOUT=1.5V 5.0 10 15 4 8 12.5 4 8 12.5 4 8 12.5 V VIL Maximum Low -Level Input Voltage VOUT= VCC - 0.5 V VOUT= VCC - 1 V VOUT= VCC - 1.5 V 5.0 10 15 1 2 2.5 1 2 2.5 1 2 2.5 V VOH Minimum High-Level Output Voltage VIN=GND 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN= VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 0.25 0.5 1.0 5.0 0.25 0.5 1.0 5.0 7.5 15 30 150 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 IOH mA mA SLS System Logic Semiconductor SL4069UB AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input t r=t f=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tPLH, t PHL Maximum Propagation Delay, Input A to Output Y (Figure 1) 5.0 10 15 110 60 50 110 60 50 220 120 100 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns CIN Maximum Input Capacitance - Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/6 of the Device) SLS System Logic Semiconductor 15 pF