SL4516B Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The SL4516B Presettable Binary Up/Down Counter consists of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. This counter can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRYIN of a more significant stage. The SL4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with ORDERING INFORMATION SL4516BN Plastic SL4516BD SOIC TA = -55° to 125° C for all packages the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16=VCC PIN 8= GND SLS System Logic Semiconductor Outputs CL CI U/D X H X L L NO COUNT L H L L COUNT UP L L L L COUNT DOWN X X X H L PRESET X X X X H RESET X = don’t care PE R Mode SL4516B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL4516B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level Input Voltage VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 IOH SLS System Logic Semiconductor mA mA SL4516B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input t r=t f=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tPHL, t PLH Maximum Propagation Delay, Clock to Q (Figure 1) 5.0 10 15 400 200 150 400 200 150 800 400 300 ns tPHL, t PLH Maximum Propagation Delay, Preset or Reset to Q (Figure 1) 5.0 10 15 420 210 160 420 210 160 840 420 320 ns tPHL, t PLH Maximum Propagation Delay, Clock to Carry Out (Figure 1) 5.0 10 15 480 240 180 480 240 180 960 480 360 ns tPHL, t PLH Maximum Propagation Delay, Carry In to Carry Out (Figure 1) 5.0 10 15 250 120 100 250 120 100 500 240 200 ns tPHL, t PLH Maximum Propagation Delay, Preset or Reset to Carry Out (Figure 1) 5.0 10 15 640 320 250 640 320 250 1280 640 500 ns tTHL, t TLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns CIN Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS (CL=50pF, RL=200 kΩ, Input t r=t f=20 ns) VCC Symbol Parameter Guaranteed Limit V ≥-55°C 25°C ≤125°C Unit 25 10 10 25 10 10 50 20 20 ns tsu Minimum Setup Time, P to Preset Enable (Figure 1) 5.0 10 15 tsu Minimum Setup Time, Up/Down to Clock (Figure 1) 5.0 10 15 ns tsu Minimum Setup Time, Carry In to Clock (Figure 1) 5.0 10 15 ns th Minimum Hold Time, Clock to Carry In (Figure 1) 5.0 10 15 60 30 30 60 30 30 120 60 60 ns th Minimum Hold Time, Clock to Up/Down (Figure 1) 5.0 10 15 30 30 30 30 30 30 60 60 60 ns th Minimum Hold Time, Preset enable to P (Figure 1) 5.0 10 15 70 40 40 70 40 40 140 80 80 ns SLS System Logic Semiconductor SL4516B 15 Figure 1. Switching Waveforms TIMING DIAGRAM SLS System Logic Semiconductor 40 40 80 SL4516B EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor