SL4518B Dual Up-Counter High-Voltage Silicon-Gate CMOS The SL4518B Dual BCD Up-Counter consists two identical, internally synchronous 4-stage counters. The counter stages are Dtype flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4518BN Plastic SL4518BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs CLOCK ENABLE RESET Mode H L Increment Counter L Increment Counter L No Change L No Change L No Change L No Change H Q1 thru Q4=L L PIN 16=VCC PIN 8= GND X X L H X X X = don’t care SLS System Logic Semiconductor Outputs SL4518B MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL4518B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VIH Minimum High-Level Input Voltage VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V VIL Maximum Low -Level Input Voltage VOUT= 0.5 V or VCC - 0.5V VOUT= 1.0 V or VCC - 1.0 V VOUT= 1.5 V or VCC - 1.5V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 IOH SLS System Logic Semiconductor mA mA SL4518B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input t r=t f=20 ns) VCC Guaranteed Limit V ≥-55°C 25°C ≤125°C Unit Maximum Clock Frequency, (Figure 1) 5.0 10 15 1.5 3 4 1.5 3 4 0.75 1.5 2 MHz Maximum Propagation Delay, Clock or Enable to Output (Figures 1,3) 5.0 10 15 560 230 160 560 230 160 1120 460 320 ns tPHL Maximum Propagation Delay, Reset to Output (Figure 2) 5.0 10 15 650 225 170 650 225 170 1300 450 340 ns tTHL, t TLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns Symbol fmax tPHL, t PLH CIN Parameter Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS (CL=50pF, RL=200 kΩ, Input t r=t f=20 ns) VCC Symbol Parameter Guaranteed Limit V ≥-55°C 25°C ≤125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 200 100 70 200 100 70 400 200 140 ns tw Minimum Pulse Width, Reset (Figure 2) 5.0 10 15 250 110 80 250 110 80 500 220 160 ns tw Minimum Pulse Width, Enable (Figure 3) 5.0 10 15 400 200 140 400 200 140 800 400 280 ns Maximum Input Rise and Fall Times (Figure 1) 5.0 10 15 15 5 5 15 5 5 15 5 5 µs tr, t f SLS System Logic Semiconductor SL4518B Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms TIMING DIAGRAM EXPANDED LOGIC DIAGRAM (1/2 of the Device) SLS System Logic Semiconductor SL4518B SLS System Logic Semiconductor