SLS SL74HC241N

SL74HC241
Octal 3-State Noninverting Buffer/Line
Driver/Line Receiver
High-Performance Silicon-Gate CMOS
The SL74HC241 is identical in pinout to the LS/ALS241. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3-state memory address drivers, clock drivers, and
other bus-oriented systems. The device has noninverting outputs and
two output enables. Enable A is active-low and Enable B is active-high.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC241N Plastic
SL74HC241D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 20=VCC
PIN 10 = GND
Output
System Logic
Semiconductor
Output
Enable
A
A
YA
Enable
B
B
YB
L
L
L
H
L
L
L
H
H
H
H
H
H
X
Z
L
X
Z
X = don’t care
Z = high impedance
SLS
Inputs
SL74HC241
MAXIMUM RATINGS *
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
IOUT
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, t f
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC241
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VIH
Minimum HighLevel Input
Voltage
VOUT= VCC-0.1 V
IOUT≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low Level Input
Voltage
VOUT= 0.1 V
IOUT ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
VIN= VIH
IOUT ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VIN= VIL
IOUT ≤ 6.0 mA
IOUT ≤7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VIN= VIH
IOUT ≤ 6.0 mA
IOUT ≤ 7.8 mA
VOL
Maximum LowLevel Output
Voltage
VIN = VIL
IOUT ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
IOZ
Maximum three
State Leakage
Current
Output in High-Impedance State
VIN = VIL or VIH
VOUT=VCC or GND
6.0
±0.5
±5.0
±10.0
µA
ICC
Maximum
Quiescent Supply
Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
4.0
40
160
µA
SLS
System Logic
Semiconductor
SL74HC241
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 °C to
-55°C
≤85°C
≤125°C
Unit
tPLH, t PHL
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
2.0
4.5
6.0
90
18
15
115
23
20
135
27
23
ns
tPLZ, t PHZ
Maximum Propagation Delay, Output Enable to
YA or YB (Figures 2 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tPZH, t PZL
Maximum Propagation Delay, Output Enable to
YA or YB (Figures 2 and 4)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tTLH, t THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
Maximum Input Capacitance
-
10
10
10
pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
15
15
15
pF
CIN
COUT
Power Dissipation Capacitance (Per Transceiver
Channel)
CPD
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
Typical @25°C,VCC=5.0 V
34
pF
Figure 2. Switching Waveforms
SLS
System Logic
Semiconductor
SL74HC241
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
SLS
System Logic
Semiconductor