SL74HC595 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High-Performance Silicon-Gate CMOS The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC595 consists of an 8-bit shift register and an 8-bit Dtype latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC595N Plastic SL74HC595D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND SLS System Logic Semiconductor SL74HC595 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC595 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage, QAQH VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA VOL Maximum Low-Level Output Voltage, QAQH VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA VOH Minimum High-Level Output Voltage, SQH VIN=VIH or VIL IOUT ≤ 20 µA VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Maximum Low-Level Output Voltage, SQH VIN=VIH or VIL IOUT ≤ 20 µA V V V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three-State Leakage Current, QAQH Output in High-Impedance State VIN= VIL or VIH VIN=VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA SLS System Logic Semiconductor SL74HC595 SLS System Logic Semiconductor SL74HC595 AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum Clock Frequency (50% Duty Cycle) (Figures 1and 7) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz Maximum Propagation Delay, Shift Clock to SQH (Figures 1and 7) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns Maximum Propagation Delay , Reset to SQH (Figures 2 and 7) 2.0 4.5 6.0 145 29 25 180 36 31 220 44 38 ns tPLH, t PHL Maximum Propagation Delay , Latch Clock to QAQH (Figures 3 and 7) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns tPLZ, t PHZ Maximum Propagation Delay , Output Enable to QA-QH (Figures 4 and 8) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPZL, t PZH Maximum Propagation Delay , Output Enable to QA-QH (Figures 4 and 8) 2.0 4.5 6.0 135 27 23 170 34 29 205 41 35 ns tTLH, t THL Maximum Output Transition Time, QA-QH (Figures 3 and 7) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tTLH, t THL Maximum Output Transition Time, SQH (Figures 1 and 7) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State), QA-QH - 15 15 15 pF Symbol fmax tPLH, t PHL tPHL CIN COUT CPD SLS Parameter Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 300 System Logic Semiconductor pF SL74HC595 TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit Tsu Minimum Setup Time,Serial Data Input A to Shift Clock (Figure 5) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns Tsu Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns th Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns Trec Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns Tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Tw Minimum Pulse Width, Shift Clock (Figure 1) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns Tw Minimum Pulse Width, Latch Clock (Figure 6) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns tr, t f Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns SLS System Logic Semiconductor SL74HC595 FUNCTION TABLE Inputs Operation Resulting Function Reset Serial Shift Latch Output Input Clock Clock Enable A Reset shift register L X X Shift data into shift register H D Shift register remains unchanged H X L,H, Transfer shift register contents to latch register H X L,H, Latch register remains unchanged X X X Enable parallel outputs X X Force outputs into high-impedance state X X Shift Register Contents Latch Register Contents Serial Output SQH Parallel Outputs QA-QH L,H, L L U L U L,H, L D SRA SRN SRN+1 U SRG SRH U L,H, L U U U U L U SRN LRN U SRN L,H, L * U * U X X L * ** * Enabled X X H * ** * Z SR = shift register contents X = don’t care LR = latch register contents Z = high impedance D = data (L,H) logic level * = depends on Reset and Shift Clock inputs U = remains unchanged ** = depends on Latch Clock input PIN DESCRIPTIONS INPUTS: A - Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register. CONTROL INPUTS: Shift Clock - Shift Register Clock Input. A low-tohigh transition on this input causes the data at the Serial Input pin to be shifted into the 8-bit shift register. Reset - Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8-bit latch is not affected. SLS System Logic Semiconductor Latch Clock - Storage Latch Clock Input. A low-tohigh transition on this input latches the shift register data. Output Enable - Active-Low Output Enable. A low on this input allows the data from the latches to bepresented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance state. The serial output is not affected by this control unit. OUTPUTS: QA-QH - Noninverted, 3-state, latch outputs. SQH - Voninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register. This output does not have three-state capability. SL74HC595 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Test Circuit Figure 8. Test Circuit SLS System Logic Semiconductor SL74HC595 TIMING DIAGRAM SLS System Logic Semiconductor SL74HC595 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor