KBD42W11 Keyboard Controller FEATURES • • • Supports IBM PC and Compatible System Designs Runs Much Faster Than Traditional Keyboard Controllers Host interface Compatible with Traditional Keyboard Controller • • • • 6 MHz – 12 MHz Operating Frequency Communicates with Keyboard Directly High-reliability CMOS Technology 40 Pin DIP and 44 Pin PLCC Package GENERAL DESCRIPTION The KBD42W11 keyboard controller is programmed to support the IBM® compatible personal computer keyboard serial interface. The keyboard controller receives serial data from the keyboard, checks the parity of the data, translates the scan code, and presents the data to the system as a byte of data in its output buffer. The controller will interrupt the system when data is placed in its output buffer. The byte of data will be sent to the keyboard serially with an odd parity bit automatically inserted. The keyboard is required to acknowledge all data transmissions. No transmission should be sent to the keyboard until acknowledgment is received for the previous byte sent. The KBD42W11 keyboard controller and BIOS to improve the performance of IBM PC machines and their compatibles. A hardwire methodology is used in this keyboard controller instead of a software implementation, as in the traditional 8042 keyboard BIOS. This enables the keyboard controller to respond instantly to all commands sent from the keyboard to the CPU BIOS. The KBD42W11 enables popular programs such as AutoCAD®, Microsoft® Windows™, NOVELL®, and other programs to run much faster. IBM is a registered trademark of International Business Machines Corporation. AutoCAD is a registered trademark of Autodesk, Inc. Microsoft is a registered trademark and Windows is a trademark of Microsoft Corporation. NOVELL is a registered trademark of Novell, Inc. Standard Microsystems is a registered trademark and SMSC is a trademark of Standard Microsystems Corporation. Other product and company names are trademarks or registered trademarks of their respective holders. TABLE OF CONTENTS FEATURES ....................................................................................................................................... 1 GENERAL DESCRIPTION ................................................................................................................ 1 PIN CONFIGURATION ...................................................................................................................... 3 PIN DESCRIPTION ........................................................................................................................... 4 BLOCK DIAGRAM ............................................................................................................................ 5 AC TIMING........................................................................................................................................ 6 TIMING WAVEFORMS ...................................................................................................................... 7 WRITE CYCLE TIMING ........................................................................................................................ 7 READ CYCLE TIMING.......................................................................................................................... 7 SEND DATA TO K/B ........................................................................................................................... 8 RECEIVE DATA FROM K/B................................................................................................................... 8 XIN/XOUT CLOCK ........................................................................................................................... 8 ABSOLUTE MAXIMUM RATINGS..................................................................................................... 9 ELECTRICAL CHARACTERISTICS & CAPACITANCE ..................................................................... 9 STATUS REGISTER ....................................................................................................................... 10 OUTPUT BUFFER........................................................................................................................... 10 INPUT BUFFER .............................................................................................................................. 10 I/O PORTS ...................................................................................................................................... 10 COMMANDS (I/O ADDRESS HEX 64)............................................................................................. 12 APPLICATION CIRCUIT ................................................................................................................. 13 ASYNCHRONOUS ............................................................................................................................. 13 SYNCHRONOUS............................................................................................................................... 14 PACKAGE DIMENSIONS................................................................................................................ 15 80 Arkay Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 273-3123 2 PIN CONFIGURATION T0 XIN 40 Pin DIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD T1 P27(KDAT) P26(KCLK) P25(IEMP) P24(INIT) P17(KINH) P16(DISP) P15(JUMP) P14(RAM) P13 P12 P11 P10 NC VDD P23 P22 P21(nGA20) P20(nRC) 44 Pin PLCC 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 D4 D5 D6 D7 VSS NC P20 P21 P22 P23 VDD nCS VSS nRD A2 nWR NC NC D0 D1 D2 D3 6 5 4 3 2 1 44 43 42 41 40 VDD nRESET XOUT XIN T0 NC VDD T1 P27 P28 P25 XOUT nRESET VDD nCS VSS nRD A2 nWR NC D0 D1 D2 D3 D4 D5 D6 D7 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 39 38 37 36 35 34 33 32 31 30 29 P24 P17 P18 P15 P14 NC P13 P12 P11 P10 NC PIN DESCRIPTION PIN NO. PIN NO. (40 Pin DIP) (44 Pin PLCC) 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11,26 1,12,13,23,29, 34 12,13,14, 14,15,16,17,18, 15,16,17, 19,20,21 18, 19 20 22 21 24 I/O I I O I I I I I I/O NAME T0 XIN XOUT nRESET VDD nCS VSS nRD A2 nWR NC D0-D7 O VSS P20 22 23 24 25 27 28 29 30 31 25 26 27 28 30 31 32 33 35 O I/O I/O I/O I/O I/O I/O I P21 P22 P23 VDD P10 P11 P12 P13 P14 32 33 34 35 36 37 38 39 40 36 37 38 39 40 41 42 43 44 I I I O O O O I - P15 P16 P17 P24 P25 P26 P27 T1 VDD 4 FUNCTION K/B Clock Input Crystal Clock I/P Crystal Clock O/P Chip Reset Optional +5V Power Supply Chip Select Optional Ground Power I/O Read Connect to Address A2 I/O Write Reserved Data Bus D0 - D7 Ground Power Supply Bit 0 of Port 2 (RCB: System Reset) Bit 1 of Port 2 (GA20: GATE A20) Bit 2 of Port 2 Bit 3 of Port 2 Optional +5V Power Supply Bit 0 of Port 1 Bit 1 of Port 1 Bit 2 of Port 1 Bit 3 of Port 1 Bit 4 of Port 1 (RAM Jumper Select) Bit 5 of Port 1 (JUMP) Bit 6 of Port 1 (Display Select) Bit 7 of Port 1 (K/B Inhibit Switch) Bit 4 of Port 2 (OBF O/P Interrupt) Bit 5 of Port 2 (I/P Buffer Empty) Bit 6 of Port 2 (K/B Clock O/P) Bit 7 of Port 2 (K/B Data O/P) K/B Data Input +5V Power Supply BLOCK DIAGRAM TRANSMIT CONTROL T0 T1 RECEIVE CONTROL XOUT XIN nWR nRD nCS A2 nRESET SCAN CODE ROM HARDWIRE CONTROL & SELECT LOGIC STATUS REGISTER R64 D0 - D7 DATA BUFFER REGISTER TRANSMIT REGISTER W60 W64 STATUS BUFFER REGISTER INPUT & INPUT BUFFER REGISTER INTERFACE OUTPUT PORT P1 0 P1 1 P1 2 P1 3 P1 4 (RAM Select) P1 5 (Manufacture Mode) P1 6 (Display) P1 7 (KBNH) R60 OUTPUT BUFFER REGISTER OUTPUT PORT INTERFACE 5 P2 0 (nRC) P2 1 (Gate A20) P2 2 P2 3 P2 4 P2 5 P2 6 (Keyboard Clock) P2 7 (Keyboard Data) AC TIMING NO. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DESCRIPTION Address Setup Time from nWR Address Setup Time from nRD nWR Strobe Width nRD Strobe Width Address Hold Time from nWR Address Hold Time from nRD Data Setup Time Data Hold Time Gate Delay Time from nWR nRD to Drive Data Delay nRD to Floating Data Delay Data Valid After Clock Falling (SEND) K/B Clock Period K/B Clock Pulse Width Data Valid Before Clock Falling (RECEIVE) K/B ACK After Finish Receiving nRC Fast Reset Pulse Delay (8 MHz) nRC Pulse Width (8 MHz) Transmit Timeout Data Valid Hold Time XIN/XOUT Period ( 6-12 MHz ) 6 MIN. 0 0 20 20 0 0 50 0 10 0 20 10 4 20 2 6 MAX. 20 20 4 3 2 0 83 167 UNIT nS nS nS nS nS nS nS nS nS nS nS µS µS µS µS µS µS µS mS µS nS TIMING WAVEFORMS Write Cycle Timing A2, nCS T1 nWR T5 T3 ACTIVE T8 T7 D0 - D7 DATA IN T9 A20 OUTPUT PORT T17 FAST RESET PULS nRC FE COMMAND Read Cycle Timing A2, nCS AEN T2 T6 T4 nRD ACTIVE T10 D0 - D7 T11 DATA OUT 7 T18 Send Data to K/B CLOCK ( KCLK ) T12 T13 T14 SERIAL DATA ( KDAT ) START D0 D1 D2 D3 T16 D4 D5 D6 D7 P STOP T19 Receive Data from K/B CLOCK ( KCLK ) T15 SERIAL DATA ( T1 ) START D0 T13 T14 D1 D2 D3 D4 T20 XIN/XOUT Clock XIN CLK T21 8 D5 D6 D7 P STOP ABSOLUTE MAXIMUM RATINGS PARAMETER Ambient Operating Temperature Storage Temperature Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Note: Exposure to conditions beyond those listed affect the life and reliability of the device. RATING UNIT -0 to +85 °C -65 to +150 °C -0.3 to +7.0 V -0.3 to +7.0 V 50 mW under Absolute Maximum Ratings may adversely ELECTRICAL CHARACTERISTICS & CAPACITANCE (Ta = 0° C to +70° C, VDD = +5V ±5%) SYMBOL DESCRIPTION VDD Power Supply TA Operating Temperature VIH High Level Voltage for TTL Min. I/P VIL Low Level Voltage for TTL Max. I/P VOH High Level Voltage for TTL Min. O/P VOL Low Level Voltage for TTL Max. O/P RIP Min. I/P Resist ILI I/P Leakage Current ILO O/P Leakage Current IOL O/P Sink Current CL O/P Load Capacity MIN. 4.75 0 2.0 -0.3 TYP. 5.0 25 MAX. 5.25 70 VDD UNIT V V V 0.8 V VDD-0.5 V 0.5 10K -10 -10 4 15 9 10 10 50 V Ω µA µA mA pF STATUS REGISTER The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the state of the keyboard controller and interface. It may be read at any time. BIT 0 BIT DESCRIPTION Output Buffer Full 1 Input Buffer Full 2 System Flag 3 Command/data 4 Inhibit Switch 5 Transmit Time Out 6 Receive Time Out 7 Parity Error FUNCTION 0: Output Buffer Empty 1: Output Buffer Full 0: Input Buffer Empty 1: Input Buffer Full This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset 0: Data Byte 1: Command Byte 0: Keyboard is Inhibited 1: Keyboard is Not Inhibited 0: No Transmit Time Out Error 1: Transmit Time Out Error 0: No Receive Time Out Error 1: Receive Time Out Error 0: Odd Parity (No Error) 1: Even Parity (Error) OUTPUT BUFFER The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by command to the system. The output buffer should be read only when the output buffer full bit in the register is 1. INPUT BUFFER The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60 sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status register is set to 0. I/O PORTS The keyboard controller has two 8-bit I/O ports and two test inputs. One of the ports is assigned for input and the other for output. The controller uses the test inputs to read the state of the keyboard's clock line and data line. 10 The following figures show bit definitions for the input, output, and test-input ports. (A) Input Port Definitions BIT FUNCTION 0 Undefined 1 Undefined 2 Undefined 3 Undefined 4 RAM on System Board 0: Disable 2nd 256 KB of System Board RAM 1: Enable 2nd 256 KB of System Board RAM 5 Manufacturing Jumper Installed 0: Manufacturing Jumper 1: Jumper Not Installed 6 Display Type Switch 0: Primary Display Attached to Color/graphics 0: Primary Display Attached to Monochrome 7 Keyboard Inhibit Switch 0: Keyboard Inhibited 1: Keyboard Not Inhibited (B) Output Port Definitions BIT FUNCTION 0 System Reset 1 Gate A20 2 Undefined 3 Undefined 4 Output Buffer Full 5 Input Buffer Empty 6 Keyboard Clock (Output) 7 Keyboard Data (Output) (C) Test-Input Definitions BIT FUNCTION 0 Keyboard Clock (Input) 1 Keyboard Data (Input) 11 COMMANDS (I/O ADDRESS HEX 64) COMMAND 20 60 AA AB AD AE C0 D0 D1 E0 F0-FF FUNCTION Read Command Byte of Keyboard Controller Write Command Byte of Keyboard Controller BIT BIT DEFINITIONS 7 Reserved 6 IBM PC Compatible Mode 5 IBM PC Mode 4 Disable Keyboard 3 Inhibit Override 2 System Flag 1 Reserved 0 Enable Output Buffer Full Interrupt Self-test BIT 00 01 02 03 04 BIT DEFINITIONS No Error Detected K/B Clock Line is Stuck Low K/B Clock Line is Stuck High K/B Data Line is Stuck Low K/B Data Line is Stuck High Interface Test Disable Keyboard Feature Enable Keyboard Interface Read Input Port Read Output Port Write Output Port Read Test Inputs Pulse Output Port 12 APPLICATION CIRCUIT Asynchronous 2 RESETB SA2 IORB IOWB D0 - D7 X1 3 X2 4 1 39 9 6 5 8 10 RESET T0 T1 A2 nCS VDD nRD nWR 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 7 VSS VDD P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24/OB P25/nBF P26/KCLK P27/KDAT NC 25 27 28 29 30 31 32 33 34 RAM SELECT JUMPER MANUFACTURING MODE JUMPER DISPLAY TYPE SWITCH 21 22 23 24 35 36 37 38 11 RCB GATE A20 KEYBOARD INHIBIT SWITCH KEYBOARD INTERRUPT KEYBOARD CLOCK KEYBOARD DATA VDD U?A 1 U?A 2 1 74ALS04 2 VCC KEYBOARD CLOCK 7407 U?B 3 4 7407 13 KEYBOARD DATA Synchronous PCLK 2 3 RESETB SA2 IORB IOWB D0 - D7 4 1 39 9 6 8 10 12 13 14 15 16 17 18 19 X1 X2 RESET T0 T1 A2 nCS nRD nWR D0 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14/RAM P15/MOD P16/DIS P17/INH P20/RCB P21/A20 P22 P23 P24 P25 P26/KCLK P27/KDAT 27 28 29 30 31 32 33 34 RAM SELECT JUMPER MANFACTURING MODE JUMPER DISPLAY TYPE SWITCH 21 22 23 24 35 36 37 38 RCB GATE A20 KEYBOARD INHIBIT SWITCH KEYBOARD INTERRUPT KEYBOARD CLOCK KEYBOARD DATA VDD U?A 1 U?A 2 1 2 VDD 74ALS04 KEYBOARD CLOCK 7407 U?B 3 4 7407 14 KEYBOARD DATA PACKAGE DIMENSIONS 40 Pin PDIP Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 1 a E eA S 1 Dimension in mm 5.33 0.210 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 2.055 2.070 52.20 52.58 0.590 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0 0.630 0.650 15 0.090 2.29 Notes: 20 E S c 2 AA 1 A Base Plane Seating Plane L B Dimension in inch Min. Nom. Max. Min. Nom. Max. e1 eA a B1 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 44 Pin PLCC HD D 6 1 44 40 7 Symbol 39 E E E H 17 G 29 18 28 L c e b b1 Dimension in mm Min. Nom. Max. 0.185 4.70 0.020 0.51 0.145 0.150 0.155 3.68 3.81 3.94 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.36 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.29 2.54 0.004 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. 1 A y GD 15 BSC 0.590 0.610 0.630 14.99 15.49 Notes: 2 A A Seating Plane A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Min. Nom. Max. 2.79 0.10 © 1998 STANDARD MICROSYSTEMS CORPORATION (SMSC) Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. SMSC reserves the right to make changes at any time in order to improve design and supply the best product possible. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. KBD42W11 Rev. 10/20/98