CXA1202Q-Z/CXA1202R REC/PB Amplifier for VCR For the availability of this product, please contact the sales office. Description CXA1202Q-Z/CXA1202R are bipolar ICs developed as REC/PB amplifiers for VCR's. CXA1202Q-Z 48 pin QFP (Plastic) CXA1202R 48 pin LQFP (Plastic) Features • Built-in head amplifier feedback dumping contributes to the reduction of external components and simplification of the print circuit board design. • Built-in BPF for PB signals medium range frequency compensation totally eliminates external resonance circuits (L. C. R.) • Low range recording signal variable-level mix amplifier allows for both metal powder and metal evaporated tapes application. • Consumption saving through power save function of the REC AMP. • 4-head system switch incorporated. Functions • Recording: 2-channel REC AMP, 5-input (Y, Chroma, AFM, ATF, PCM) Mix AMP. • Playback: 2-channel low-noise head amplifier, medium range frequency compensation circuit, RF AGC, dropout detecting circuit. Structure Bipolar silicon monolithic IC Applications • 8-mm system VCR • β-system VCR • VHS-system VCR Absolute Maximum Ratings (Ta = 25°C) • Supply voltage Vcc 8 V • Operating temperature Topr –10 to +75 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD (CXA1202Q-Z) 920 mW PD (CXA1202R) 1100 mW (CXA1202R: Substrate area 40 × 25mm2, t = 0.635mm when ceramic print circuit board mounted) Recommended Operating Condition Supply voltage Vcc 5 ± 0.25 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E88012-PS CXA1202Q-Z/CXA1202R REC2 IN MT Q VCC 2CH REC2 OUT PB IN 2P PB IN 2N PB IN 1N PB IN 1P REC1 OUT VCC 1CH MT Fφ REC1 IN Block Diagram and Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 CH2 REC AMP MIX2 OUT 37 CH1 REC AMP 24 MIX1 OUT MT 2 38 23 MT1 46dB RF SWP 39 CH2 HEAD AMP GND 2CH 40 46dB 9dB 20 V RF OUT MTFφ MTQ ME LEVEL 42 VP1 VP2 –6dB SW SW GND REC 43 21 GND 1CH 9dB CONTROL LOGIC PCM SEL 41 22 MULTI CH1 HEAD AMP BPF Video –6dB CH2 SW CH1 BPF 19 GND PB 18 DOC IN Mute P V ATF LEVEL 44 P V VCA MT2 MT1 VCA RP PB 1CH 45 ME LEVEL ATF SW Normal VCA 6dB GCA PCM MIX SW AMP 6dB VCA DOC DET RF DET AGC A Multi 15 DOC TC 14 RF IN B 5 VREG AFM IN VG 6 7 8 9 10 11 12 RF IN A 4 HCHG 3 AGC OUT 2 AGC TC 1 C IN 13 DOC PULSE RP PB EN PCM IN 48 B RF SW PCM RF OUT RP PB 2CH 47 12dB CH1 VCC VCA 17 VCC EF 16 RF OUT CH2 Y IN ATF IN 46 DOC DET 6dB Medium range freq. compensation –2– CXA1202Q-Z/CXA1202R Pin Description Voltage No. Symbol DC AC I/O resistance Equivalent circuit Description VCC 1 1 (Open: RP PB EN "L") — Power-save recording at Low. High: over 3V Low: under 1V 40k 40kΩ 20k GND VCC 2 2 C IN 3.2V 134 mVp-p 20kΩ Input pin for Chroma signal. 20k 100 GND VCC 24k 3 VREG 4.2V — — 3 Output pin for VREG 4.2V. Decoupling with capacitance. 35k GND 4 AFM IN 3.2V 80 mVp-p 20kΩ Same as for Pin No. 2 Input pin for AFM signal. VCC 150 5 VG 2.5V — Output pin for virtual GND. Decoupling with capacitance. — 5 2.5k GND 6 Y IN 3.2V 250 mVp-p 20kΩ Same as for Pin No. 2 7 Vcc 5.0V — — — Input pin for Y signal. Supply pin for circuits other than REC AMP and Head AMP. VCC 440 8 PCM RF OUT 1.8V 50 to Emitter 500 follower mVp-p (IE = 1mA) 8 1mA GND –3– Output pin for PB PCM signal. CXA1202Q-Z/CXA1202R Voltage No. Symbol DC AC I/O resistance Equivalent circuit Description VCC 500 200 9 AGC TC 4.25V (Load: 150kΩ — Pin to apply time constant of envelope detection for RF AGC. Optimum load resistance across Vcc is 150kΩ. 200 9 — GND VCC 200 17 10 AGC OUT 2.5V Emitter 100 follower mVp-p (IE = 1mA) AGC output pin for PB VIDEO signal (Max. gain of AGC AMP is about 7dB). 10 1mA GND VCC 11 HCHG — (Open: "L") — 50kΩ Control signal input pin for RF SW switching: High (over 3V): selects RF IN A Low (under 0.3V): selects RF IN B 50k 11 GND VCC 150 12 RF IN A 2.5V 100 mVp-p 12 Input pin for RF switch and 12dB AMP. 20k — 5 GND VCC 100 13 DOC PULSE H: 3.2V L: 0V — Emitter follower (H: IE = 1mA) 13 80k Dropout detection signal output pin; High upon dropout. 3.5k GND 14 RF IN B 2.5V 100 mVp-p 20kΩ Same as for Pin No. 12 Input pin for RF switch and 12dB AMP. VCC 90 15 DOC TC 2.5V — — 8k 3.3k 15 Pin to connect time constant of dropout detection. GND –4– CXA1202Q-Z/CXA1202R Voltage No. Symbol DC AC I/O resistance Equivalent circuit Description VCC 200 16 RF OUT 2.5V Emitter 400 follower mVp-p (IE = 500µA) 16 500µA Output pin of signal selected by HCHG from RF IN A and RF IN B. GND VCC 17 17 Vcc EF 5.0V — 200 — Supply pin for emitter followers of AGC OUT, DOC TC and RF OUT. GND VCC 150 18 DOC IN 2.5V 400 mVp-p 18 8k 8kΩ Input pin for dropout detection. 2.5V GND 19 GND PB 0V — GND pin for medium range frequency compensation circuit, RF AGC and DOC DET. — — VCC 400 20 V RF OUT 1.8V Emitter 50 to follower 500 (IE = mVp-p 500µA) Output pin for PB VIDEO signal. 20 500µA 21 GND 1CH 22 MULTI GND 0V — — — GND pin for CH1 REC AMP and CH1 Head AMP. — (OPEN: "L") — 40kΩ Same as for Pin No. 1 Multi-channel PCM REC mode at High. VCC 23 MT1 — (2.5V at OPEN of pin) 25k — 100kΩ 47k 53k 23 5 GND –5– Boost level adjusting pin for CH1 medium range frequency compensation circuit. Variable between 0 and +12dB at 4.2 to 0.8V. CXA1202Q-Z/CXA1202R Voltage No. Symbol DC AC I/O resistance Equivalent circuit Description VCC 400 24 MIX1 OUT 2.5V Emitter 203 follower mVp-p (IE = 1mA) Mix circuit output pin for CH1. 24 1mA GND VCC 100 25 REC1 IN 1.8V 92µA (Y signal) 25 ~ –0 100 CH1 REC AMP input pin. 200 GND VCC 26 MT Fφ 2.5V — 26 — 90 GND 27 Vcc 1CH 5.0V — Power supply pin for CH1 REC AMP and CH1 Head AMP. — — Fφ adjusting pin for medium range frequency compensation circuit; Fφ is controlled through current value by connecting resistance between GNDs. Mutually affected by MT Q. Do not connect capacitance. 28 28 REC1 OUT 15mA 13 Open mAp-p collector CH1 REC AMP output pin. 20 GND VCC 29 29 PB IN 1P 2.4V 90 to 900 µVp-p CH1 head AMP positive phase input pin (PB signal input pin). 1.3kΩ 10k GND VCC 30 PB IN 1N 2.4V — 1.3kΩ CH1 Head AMP inverter phase input pin (decoupling with capacitance). 30 GND –6– CXA1202Q-Z/CXA1202R Voltage I/O resistance Equivalent circuit No. Symbol 31 PB IN 2N 2.4V — 1.3kΩ Same as for Pin No. 30 CH2 Head AMP Inverter phase input pin (decoupling with capacitance). 32 PB IN 2P 2.4V 90 to 900 µVp-p 1.3kΩ Same as for Pin No. 29 CH2 Head AMP positive phase input pin (PB signal input pin). 33 REC2 OUT 15mA 13 mAp-p Same as for Pin No. 28 CH2 REC AMP output pin. 34 Vcc 2CH DC 5.0V AC — Power supply pin for CH2 REC AMP and CH2 Head AMP. — — Description 35 MT Q 2.5V — — Same as for Pin No. 26 Q adjusting pin for medium range frequency compensation circuit. Controls Q through current value by connecting resistance between GNDs; Mutually effected by MT Fφ. Do not connect capacitance. 36 REC2 IN 1.8V 92µA (Y signal) ~ –0 Same as for Pin No. 25 CH2 REC AMP input pin. 37 MIX2 OUT 2.5V Same as for Pin No. 24 Mix circuit output pin for CH2. Emitter 203 follower mVp-p (IE = 1mA) 38 MT 2 — (2.5V at OPEN of pin) 39 RF SWP — (Open: "L") — 40kΩ Same as for Pin No. 1 RF switching pulse input pin for CH switchover. 40 GND 2CH 0V — — — GND pin for CH2 REC AMP and CH2 head AMP. PCM SEL — (Open: "L") 41 — 100kΩ Same as for Pin No. 23 Boost level adjusting pin for CH2 medium range frequency compensation circuit; variable between 0 and +12dB at 4.2 to 0.8V. — 40kΩ Same as for Pin No. 1 PCM AREA input pin; High: PCM REC period During High period after recording, MUTE is applied to PB VIDEO output. VCC 42 — (2.1V ME LEVEL at OPEN of pin) 2.1V — 18k 100kΩ 42 24k 76k GND –7– Level of low range REC signals (Chroma, AFM, ATF rec. with VIDEO) can be boosted by 0 to 3dB by voltage (0 to 5V) applied to this pin. CXA1202Q-Z/CXA1202R Voltage No. Symbol 43 GND REC 44 45 ATF LEVEL RP PB 1CH DC AC I/O resistance 0V — — — (2.1V at OPEN of pin) — (Open: "L") — — 100kΩ 40kΩ Equivalent circuit — Description GND pin for VG, VREG, LOGIC and mix circuit. Same as for Pin No. 42 REC Ievel of ATF signal can be boosted by 0 to 3dB by the voltage (0 to 5V) applied to this pin. In multi PCM mode, priority given to 6dB AMP. Same as for Pin No. 1 REC/PB switchover signal for CH1: High: PB Low: REC However, when RP PB EN pin is at Low: High: power save REC Low: REC VCC 46 ATF IN 2.5V 250 mVp-p 100 20kΩ Input pin for ATF pilot signal. 46 20k 5 GND 47 RP PB 2CH — (Open: "L") — 40kΩ Same as for Pin No. 1 REC/PB switchover signal for CH2: High: PB Low: REC However, when RP PB EN pin is at Low: High: power save REC Low: REC 48 PCM IN 3.2V 250 mVp-p 20kΩ Same as for Pin No. 2 Input pin for PCM signal. –8– Item CH2 VFY2 CH1 VFY1 CH2 GY2 CH1 GY1 IREC Symbol –9– 48 48 2 Mix AMP CH1 VFP1 PCM frequency CH2 VFP2 response Mix AMP CH1 DP1 PCM secondary distortion factor CH2 DP2 Mix AMP Chroma gain 6 7 8 150 mVp-p 500 mVp-p 250 mVp-p 250 mVp-p 500 mVp-p 250 mVp-p 250 mVp-p 750kHz 5MHz 10MHz 1MHz 1MHz 5MHz 10MHz 1MHz 1MHz ∗1 See the Control Logic Truth Table for control logic conditions. GC1 CH2 GP2 Mix AMP PCM gain 48 6 6 6 Level D K K J E F C B A A 42, 44 24 37 24 37 24 37 24 37 24 37 24 37 24 IVCC At min. gain of 0V at ME LEVEL pin 10MHz Ievel 1MHz Ievel 10MHz Ievel 1MHz Ievel In both CH REC, internal consumption current (excluding REC output current) Test method –50 –0.2 –1.8 –50 –0.2 –1.8 27.5 Typ. –12.7 –11.7 –1.0 –2.8 –1.0 –2.6 20.5 Min. –10.7 –40 –0.8 –40 –1.0 35.0 Max. dB dB dB dB dB dB dB mA Unit (Ta = 25°C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) Test point, Ammeter Control Other ∗ 1 SW ON name Frequency logic Test conditions Input condition Input pin 5 CH1 GP1 Mix AMP CH1 DY1 Y secondary distortion factor CH2 DY2 Mix AMP Y frequency response 3 4 Mix AMP Y gain 2 1 REC mode circuit current <Recording> No. Electrical Characteristics CXA1202Q-Z/CXA1202R GAF1 DAF1 GATV GATP ∆GATA ∆GATM Mix AMP AFM gain Mix AMP AFM secondary distortion factor Mix AMP ATF gain (rec. with VIDEO) Mix AMP ATF gain (rec, with PCM) Mix AMP ATF variable gain by ATF LEVEL pin Mix AMP ATF rec. with PCM variable gain by ME LEVEL pin 11 12 13 – 10 – 14 15 16 250 mVp-p 250 mVp-p 250 mVp-p 250 mVp-p 100kHz 100kHz 100kHz 100kHz 1.5MHz 1.5MHz 100 mVp-p 250 mVp-p 750kHz 250 mVp-p 750kHz ∗1 See the Control Logic Truth Table for control logic conditions. 46 46 46 46 4 4 2 DCI Mix AMP Chroma secondary distortion factor 10 150 mVp-p Level J J J J F D K E D 42 44 42 42 42 24 37 24 37 37 37 24 24 Test point, Ammeter Control Other ∗ 1 SW ON name Frequency logic Input condition Input pin 2 Symbol 9 Item Mix AMP Low range freq. (Chroma, AFM, ∆GME ATF rec. with VIDEO) variable gain by ME LEVEL pin No. Test conditions Change in gain when ME LEVEL pin is brought from 0 to 5V 2.3 3.3 3.4 4.3 4.4 –26.3 At min. gain of 0V at both ME LEVEL pin and ATF –28.9 –27.6 LEVEL pin 2.4 –26.3 At min. gain of 0V at both ME LEVEL pin and ATF –28.9 –27.6 LEVEL pin Change in gain when ATF LEVEL pin is brought from 0 to 5V –40 –9.0 –40 4.4 Max. –50 At max. gain of 5V at ME LEVEL pin –11.2 –10.1 At min. gain of 0V at ME LEVEL pin 3.4 Typ. –50 2.4 Min. At max. gain of 5V at ME LEVEL pin Change in gain when ME LEVEL pin is brought from 0 to 5V Test method dB dB dB dB dB dB dB dB Unit (Ta = 25°C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) CXA1202Q-Z/CXA1202R ∆GATMU Mix AMP ATF gain increment at multi PCM REC AMP output bias current REC AMP output bias current REC AMP channel balance 17 18 19 20 – 11 – Head AMP PCM RF OUT gain AGC OUT Ievel 24 25 VAGC CH2 GP2 CH1 GP1 CH2 GV2 CH1 GV1 Input pin 29 32 29 32 29 36 25 36 25 36 25 36 25 46 200 µVp-p 200 µVp-p 200 µVp-p 300 mVp-p 200 mVp-p 200 mVp-p 200 mVp-p 250 mVp-p Level 5MHz 1MHz 1MHz 5MHz 10MHz 1MHz 1MHz 1MHz 100kHz H H I I H E B F F A G J 23 38 23 38 23 10 8 20 33 28 33 28 33 28 33 28 IREC2 IREC1 24 Test point, Ammeter Control Other ∗ 1 SW ON name Frequency logic Input condition ∗1 See the Control Logic Truth Table for control logic conditions. Head AMP VRF OUT gain 23 <Playback> REC AMP CH1 DR1 secondary distortion factor CH2 DR2 22 CH2 ∆VFR2 REC AMP frequency response 21 CH1 ∆VFR1 ∆VR21 CH2 IR2 CH1 IR1 CH2 IDR2 CH1 IDR1 Symbol Item No. Test conditions 10MHz Ievel 1MHz Ievel Difference in output level between CH1 and CH2 Output level [V] 100 [Ω] DC current testing Change in gain when control logic is set to multi PCM Test method 70 52.2 52.2 –3.2 –0.8 12.0 13.4 4.9 Min. 95 54.5 54.5 –49 –2.1 0.0 13.2 15.7 5.9 Typ. 120 57.2 57.2 –40 0.8 14.4 18.0 6.9 Max. mV p-p dB dB dB dB dB mA p-p mA dB Unit (Ta = 25°C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) CXA1202Q-Z/CXA1202R ∆VAGCL ∆VDC12 AGC control characteristics "L" DC offset between channels CH1 – CH2 DC offset at MUTE, CH1, CH2 – MUTE 27 28 29 – 12 – Dropout detection, ON level 32 12 14 10 10 Output level at input 100µV 10MHz 300kHz 300kHz 1MHz 1MHz See the following figure ∗2 100 mVp-p 100 mVp-p 100 µVp-p 900 µVp-p H K J I H 11 11 11 38 23 H→J I→J 38 23 I H 18 16 16 10 10 –2.0 11.1 –60 –60 –0.8 –0.3 Min. –0.4 12.1 0 0 –0.1 0.5 Typ. Pin 18 Ievel when DOC PULSE pin becomes High –16.5 –13.0 (0dB = 400mVp-p) 10MHz Ievel 300kHz Ievel Difference of DC voltage at logic switchover DC voltage testing At CH1 Low input – at CH2 High input At CH2 High input – at CH1 Low input 23 23 100 µVp-p H H Output level at input 200µV 5MHz 5MHz Output level at input 900µV Output level at input 200µV Test method 200 µVp-p 100 µVp-p 200 µVp-p 900 µVp-p Level ∗1 See the Control Logic Truth Table for control logic conditions. VD ON B input ∆VFRFB 12 A input ∆VFRFA RF SW frequency response 31 14 12 32 29 32 29 29 29 Test point, Ammeter Control Other ∗ 1 SW ON name Frequency logic Input condition Input pin B input GRFB RF SW gain 30 A input GRFA ∆VDCM ∆VAGCH Symbol AGC control characteristics "H" Item 26 No. Test conditions –10.5 13.1 60 60 0.6 1.3 Max. dB dB dB mV mV dB dB Unit (Ta = 25°C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) CXA1202Q-Z/CXA1202R VPDL VPDH IPB Dropout pulse, Low level Dropout pulse, High level PB mode circuit current 34 35 36 VREG pin DC voltage VREG 38 Input pin 12 12 100 mVp-p 5MHz see the figure below ∗2 Level – 13 – Pin 13 DOC PULSE Pin 12 input signal 100mVp-p 100µs A H H H H I 0V 3.2V Min. V 4.38 4.23 4.08 mA V 50.5 V V dB Unit 2.61 40.0 3.4 0.1 –5.0 Max. 2.51 30.0 Current consumption with both CHS in PB 3.2 0.0 –7.0 Typ. 2.41 3.1 DC voltage testing DC voltage testing Pin 18 Ievel when DOC PULSE pin becomes Low –9.5 (0dB = 400mVp-p) Test method ON, OFF level testing at Pin 18 3 5 IVCC 13 13 18 5MHz OFF level ON level 42.44 11 11 11 Test point, Ammeter Control Other ∗ 1 SW ON name Frequency logic Input condition ∗1 See the Control Logic Truth Table for control logic conditions. ∗2 Signal description of dropout detection. VG pin DC voltage 37 VG <Standard voltage supply in IC> VD OFF Symbol Dropout detection, OFF Ievel Item 33 No. Test conditions (Ta = 25°C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) CXA1202Q-Z/CXA1202R L H H L H L H H H H H H H H G H I J K L M L L L B C D L L L H L H A H H L (Pin 1) RP PB EN E F (Pin 45) RP PB 1CH Control Iogic condition (Pin 47) RP PB 2CH – 14 – L H L H H H L L L L L H L (Pin 39) RF SWP H L H L H L — H L — — — — (Pin 22) MULTl H H L L — — H L L L L L L (Pin 41) PCM SEL H H H H L L — H H L L L L P V V V V V V P V X V V P V V V X V (Pin 33) REC2 OUT P V X X X P X X MP MP X MP MP MP V P X X MP X P X X X MP MP MP MP V P V V V V (Pin 24) MIX1 OUT Recording CH1 HEAD AMP O X O X O O X X X X X X X CH2 HEAD AMP X O X O O O X X X X X X X medium range freq. compensation circuit, DOC DET, RF SW O O O O O O X X X X X X X CH1 CH2 X X X X X X X CH1 CH2 X X X X X X X O MUTE MUTE (No signal) O MUTE MUTE (No signal) O MUTE MUTE (No signal) O MUTE MUTE (No signal) CH2 CH1 X X X X X X X (Pin 8) PCM RF OUT Playback (Pin 10) AGC OUT Operation of each section under respective input condition (Pin 37) MIX2 OUT Control Iogic input condition (Pin 28) REC1 OUT Input condition and operation (Pin 20) V RF OUT Control Logic Truth Table MULTI • PCM PCM after recording VIDEO • PCM PCM after recording PB MULTI PCM REC VIDEO • PCM REC Power save VIDEO REC VIDEO REC Operation PCM after recording PB REC Mode CXA1202Q-Z/CXA1202R CXA1202Q-Z/CXA1202R 1. Description of input condition "High" … Control logic input, over 3V. "Low" .… Control logic input, under 1V. "—" …… Independent of High, Low. 2. Description of operation mode O ……… Operating X ……… Not operating • In recording mode V ......... VIDEO signal is output. P ......... PCM signal is output. MP....... ATF signal that passed through fixed 6-dB AMP in mix circuit is output, mixed with PCM signal. • In playback mode CH1 ...... CH1 signal is output. CH2 ...... CH2 signal is output. MUTE ... MUTE is applied to PB VIDEO signal in PCM after recording; at the same time, RF AGC gain is held. – 15 – IVCC VCC 5V 10µ 0.1µ 0.1µ PCM IN RP PB 2CH ATF IN RP PB 1CH PCM SEL RF SWP MIX2 OUT SW44 22µ 25k 50 50 ME LEVEL MT 2 0.01µ 0.047µ ATF LEVEL SW42 SW38 2.2k 0.1µ 48 47 46 45 44 43 42 41 40 39 38 37 0.1µ ∗ 2.2k 34 6dB 2 VCA 3 50 32 P V Multi 4 5 50 33p 5.6µ 3.3 MTQ MT1 MT2 6 7 0.1µ 50 1k 0.1µ 0.01µ VG PCM MIX SW AMP 6dB VCA CH2 8 VCA BPF 46dB 28 26 150k GCA 0.1µ 10 RF DET AGC 9 CH1 6dB Mute 0.1µ ∗ 2.2k 12 11 13 14 50 0.047µ B RF SW 0.3V 3V 16 17 18 19 20 21 22 23 24 50 DOC 15 DET A 12dB Video –6dB CH2 SW CH1 25 REC1 IN DOC DET 51k CH1 REC AMP 27 ∗ 100 CH1 HEAD AMP 29 9dB Medium range freq. compensation VCA 30 MTFφ 46dB 31 BPF 9dB ME LEVEL ATF SW Normal VCA P V 5.6µ 3.3 IREC1 0.33µ 0.22µ 0.22µ 0.33µ PB IN 2P CH2 HEAD AMP 33 33p ∗ 100 VP1 VP2 –6dB SW SW CONTROL LOGIC CH2 REC AMP 35 1 36 8.2k MT Q RP PB EN ∗ 22k 0.047µ REC2 IN CIN IREC2 AFM IN 50 Y IN 0.047µ 5V AGC OUT PB IN 1P PCM RF OUT 5.8k 0.047µ MT Fφ HCHG – 16 – RF IN A Electrical Characteristics Test Circuit ∗ 0.047µ 100k 220p 150k 0.1µ 5.8k 0.01µ 47k 50 SW23 0.01µ 0.1µ 5.8k MT1 0.1µ 2.2k 22k DOC PULSE RF IN B RF OUT V RF OUT MULTI MIX1 OUT Resistance accuracy: 1% Signal source 50Ω 1Ω 49Ω PB IN 2P PB IN 1P input by attenuating 50Ω signal source to 1/50 as shown below. Input level is controlled at 1/50. Control point of input manner and input level of signal to head AMP: ∗ Signal input pin (Input level control point) Signal source impedance: 50Ω Control logic pin Signal output pin (Test) CXA1202Q-Z/CXA1202R CXA1202Q-Z/CXA1202R Description of Operations The functional blocks, voltage supply and GND pins of CXA1202Q-Z and CXA1202R are configured as follows: Block name Voltage supply pin GND pin 7 43 CH1 27 21 CH2 34 40 CH1 27 21 CH2 34 40 7 19 RF AGC section 7, 17 (Output emitter follower section) 19 RF SW section 7, 17 (Output emitter follower section) 19 7, 17 (Peak hold section) 19 Control logic section 7 43 Standard voltage supply section in IC (VREG, VG) 7 43 Mix AMP + SW section REC AMP section Head AMP section Medium range frq. compensation circuit + SW section Dropout detecting section Individual blocks are described in the following paragraphs. [Mix AMP + SW] Here, each of Y, Chroma, AFM, ATF and PCM signals is input at a prescribed input level so that they are mixed together internally to achieve an appropriate current value at the head, and output to MIX1 OUT pin (CH1 signal) and MIX2 OUT (CH2 signal) at a correct timing. Control is possible at ATF LEVEL pin (0 to 3dB at 0 to 5V, OPEN not allowed) when only the ATF recording level is to be increased as required, and at ME LEVEL pin (0 to 3dB at 0 to 5V, OPEN not allowed) when only the low range signal (Chroma + AFM + ATF) recording level is to be increased. In MULTI PCM mode, the ATF recording level is boosted by 6dB. In SW, the signal is output to MIX1 OUT and MIX2 OUT pins under control of the control logic section. [REC AMP] Mix AMP + SW output is input after it is converted into a suitable current by an external resistor, to drive the head. Adjustment of the external resistor makes it possible to set a gain and DC bias current to match that of the head. Feedback dumping is applied to inhibit head resonance (refer to the Application Circuit), and take care that capacitance coupling will not occur across the input and output. Control signals of RP PB EN, RP PB 1CH and RP PB 2CH permit power saving in the channels while recording (refer to the Control Logic Truth Table). Power saving of about 85mW is possible through a single channel. – 17 – CXA1202Q-Z/CXA1202R [Head AMP] The playback signal from the head is amplified with low noise and high gain. For example, the equivalent input noise level at 1MHz is 662pVrms/ √ Hz.∗1 In PB, the total input capacitance∗2 will be about 75pF. To inhibit resonance between this capacitance and the head inductance, a feedback dumping is incorporated. Connect a bypass capacitor for PB IN 1N and PB IN 2N pins between these pins and the rotary transformer Vcc. So far as this capacitor is over 0.2µF, the low-Ievel frequency response does not deteriorate. Beside the 0.1µF good frequency response capacitor connected to pin VREG, by adding a capacitor of over 10µF, degradation of noise level at low range can be prevented. Take care not to allow capacitance coupling between PB output and Head AMP input. ∗1 and ∗2 See the next page. [Medium range frequency compensation circuit + SW] This corrects the frequency response of the PB signal. It is possible to set to and Q magnitude by means of the external resistance value of MT Fφ and MTQ pins (refer to the Fφ graph). The amount of boost may be adjusted through the external volumes of MT1 and MT2 pins (refer to the graph showing the effect of standard response MT2 pin voltage on the amount of boost). By controlling the control logic section, SW is changed over with the timing of RF SW (switching pulse), to output PCM RF signals and VIDEO RF signals. Mute is applicable to VIDEO RF signals during PCM after recording within the PCM recording area period. [RF AGC] The played back VIDEO RF signal are output here to achieve a constant level of 100mVp-p. The time constant for AGC is set by means of the resistance and capacitance external to AGC TC pin. At the input section of the detector a HPF with a cutoff frequency of about 1MHz is incorporated. This is to permit detection within the Y signal band. In PCM after recording, MUTE applies during the PCM recording area period to keep the gain on an unchanged level. [RF SW] Signals input to RF IN A and RF IN B pins are selected by means of HCHG control signals and output via the 12-dB amplifier to RF OUT pin. This switch is utilized for SP/LP head changeover when a 4-head system is employed. [Dropout detection] Dropout is detected here from RF signals of played-back VIDEO and dropout pulse is output. The time constant is set by means of the external resistance and capacitance external to DOC TC pin. The detection level is set in the interior with 400mVp-p input as standard to obtain optimum level. Use an external coupling capacitance value of input of 47pF to achieve HPF function. [Control Logic] The IC is controlled from this section as it will save power when circuit blocks are not in use. Therefore, power saving is automatically executed while all the power supplies are switched on. Many SWs are also available to switch inputs or outputs with complicated timing. Internal logic circuits to control them are provided. It is possible to achieve all possible combinations of inputs/outputs necessary for the basic operations by means of the 13 modes shown in the Control Logic Truth Table. L is set when the control logic pin is open. [Standard voltage supplies in the IC] VREG 4.2V and VG 2.5V are provided as the standard voltage supplies in the IC. – 18 – CXA1202Q-Z/CXA1202R ∗1 (Reference) Test Method of Head AMP C/N (1) input signal Level –42.0dBm [signal source: 50Ω] (generates a voltage of 100µVp-p at both ends of 1Ω). (2) Signal injection circuit 50Ω 49Ω CXA1202Q-Z CXA1202R head AMP 1Ω Signal source B A Head inductance 1.55µH Winding ratio 3:5 Fig. 1 The signal is input from A and B in Fig. 1. The equipment used for the input is shown in Fig. 2. BNC 51Ω 1200Ω A 1Ω B To drum GND Notes) 1. A chip resistance is used for 1Ω (ordinary carbon resistance produces inductance.) 2. 49Ω is composed of 51Ω/1200Ω. Fig. 2 During signal (3) SPECTRUM ANALYZER setting conditions: RBW: 10kHz VBW: 1Hz Sweep time: 500s Span: 500kHz C/N During shortcircuit between A – B 5MHz Span 500kHz (4) Keep the medium range frequency compensation circuit flat. (Voltage of Pins MT1 and MT2 is made equal to that of Pin VREG) (5) Observe the output at Pin 20 V RF OUT. ∗2 The total input capacitance includes all capacitances of REC AMP, rotary transformer, shielding wire, etc., in addition to the input capacitance of the Head AMP alone (47pF). – 19 – 10µ 0.1µ ME/MP ATF LEVEL MULTI 22µ 10k 10k 22k 0.01µ 2 24 48 47 46 45 44 43 42 41 40 39 38 37 ATF BLOCK PCM IN RP PB 2CH ATF IN RP PB 1CH ATF LEVEL GND REC ME LEVEL PCM SEL GND 2CH RF SWP MT 2 MIX2 OUT 0.047µ 47k 2200 1 36 34 2 VCA 6dB P V 3 Multi 4 ME LEVEL 9dB 0.1µ 6 44 8 46dB 28 CH1 REC AMP 27 26 GCA 12 11 1000p B RF SW DOC DET DOC DET A 12dB 13 14 15 16 17 18 220p 47p 0.01µ 100k DTC 144 10k ∗∗ DOC 0.022µ PULSE RF IN B DOC TC RF OUT VCC EF DOC IN GND PB V RF OUT GND 1CH MULTI MT1 15k JOG : High Normal : Low 5.6k 3.9k 4.7k 1000p DTA144 ∗ DTA144 150k 56k 22k DTC144 100k 47k 0.01µ 22k 5V/0V 10k AMP AFM Trap AFM Trap PF EQ C Trap ATF Trap ATF Trap VIDEO BLOCK Half Trap AFM Trap S.L. LPF PB C RF IN 59 REC Y RF 5 REC C RF OUT 60 PB Y RF 2 DOP 3 CXA1200Q 17 DOC PULSE CXA1201M ∗∗ Drop out countermeasures for virgin tape in playback. During playback of virgin tape, as drop out pulse is generated, drop out compensation is activated for long periods to deal with noise. V sync is disturbed and the picture loses its clarity. To prevent that, drop out pulse is passed through HPF and after continuation for a certain period the pulse disappears. JOG : High Normal : Low DTA144 220k 10 470k 9 RF DET AGC CH1 6dB Mute 19 20 21 22 23 24 MIX1 OUT 2200 0.1µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 25 22k 27k 22k 0.01µ Video –6dB CH2 SW CH1 AFM BLOCK 7 PCM MIX SW AMP 6dB VCA CH2 8 VCA BPF MT1 MT2 7 0.1µ 5 MTQ 29 0.1µ 0.1µ CH1 HEAD AMP Medium range freq. compensation VCA 30 0.1µ MTFφ 46dB 31 0.1µ BPF 9dB ATF SW Normal VCA P V 32 CH2 HEAD AMP 33 VP1 VP2 –6dB SW SW CONTROL LOGIC CH2 REC AMP 35 0.1µ 0.1µ CH1 HEAD ∗ Countermeasure for drop out pulse in EE or editing mode. On a Virgin tape, drop out pulse shows with EE or editing mode in the absence of playback output. In such case CXA1201M holds AGC gain. This may cause image disturbance at the beginning of either recording or editing from EE mode. To prevent this inconvenience, a 0V signal in recording and 5V in playback, synchronized with the REC/PB signal of CXA1201M is entered. At 0V, the voltage of Pin 18 rises as if the input level for drop out detection had increased. This prevents the drop out pulse even if there is no signal. REG 5V GND To system contoller To PCM REC PCM PB PCM after recording area RF SWP PCM area MT Q 0.047µ C IN To servo To PCM To system contoller 22k 27k VREG 0.1µ LPF REC Pilot OUT 22k 0.01µ 10µ 22k CXA1204Q VCC LPF PB Pilot IN VCC 2CH AFM IN 0.1µ REC2 IN RP PB EN REC2 OUT CH2 HEAD VCO OUT 0.047µ PB IN 2N Y IN REC RF BPF REC1 OUT AGC TC 0.047µ PB IN 1N PBIN2 VCC 1CH AGC OUT PB IN 2P VG EQ PB IN 1P PCM RF OUT CX20137 VCC REC1 IN MT Fφ HCHG – 20 – RF IN A Application Circuit CXA1202Q-Z/CXA1202R CXA1202Q-Z/CXA1202R C1 Recording current Precautions 1. Do not connect parasite capacitance to REC AMP dumping. C1 C2 25 28 Effect of C2 Effect of C1 Frequency REC AMP 2. Do not bring Head AMP input near PB output. Normally, there is a gain of 67dB between Head Amp input (Pins 29, 30) and RFOUT (Pin 16). During no signal, the gain is 74dB (as AGC reaches maximum gain). Bringing those closer on the pattern may cause oscillations in the vicinity of 6 to 7MHz. 3. Use 150kΩ for RF AGC time constant, Resistance Because a change in this R causes a change in the AGC output level, change the time constant using the value of capacitance. 4. Watch the time constant of dropout detection. Time constant: t = C × (R1//R2) C: over 150pF VCC R2 = 1.2 to 2.0V R1 + R2 Oscillations may occur unless this condition is satisfied. R1 R1, R2: 5 × DOC TC 15 R2 C 5. Take AFM PB output from V RF OUT (Pin 20) Passing AFM signal through RF AGC causes AGC to reach maximum gain when playing back a virgin tape. As a result MUTE may not apply to AFM IC (CX20137, CX20037). 6. Adjust tape path by mixing V RE OUT signal and PCM RF OUT signal. In the absence of a signal before switching, observe the envelope comprising the combination of the VIDEO area and the PCM area by mixing outputs from V RF OUT (Pin 20) and PCM RF OUT (Pin 8). RF SWP V RF OUT PCM RF OUT After mixing – 21 – CXA1202Q-Z/CXA1202R Mix AMP ATF gain vs. ATF LEVEL pin voltage 5 5 4 4 Gain [dB] Gain [dB] Mix AMP Chroma gain vs. ME LEVEL pin voltage 3 2 1 3 2 1 0 1 2 3 4 ME LEVEL pin voltage [V] 5 0 Conditions: Input: Pin 2, 126mVp-p, 750kHz Output: Pin 24 Logic A Relative gain [dB] Secondary distortion factor [dB] REC AMP frequency response –40 –50 –60 4 6 8 f – Frequency [MHz] –10 2 4 6 8 10 12 14 16 18 20 f – Frequency [MHz] Conditions: Input: At resistance (2.2kΩ) with Pin 25, 200mVp-p Output: Pin 28, load resistance: 100Ω Logic A REC AMP distortion factor vs. Frequency Distortion factoc [dB] Secondary distortion factor [dB] 0 –5 0 REC AMP secondary distortion factor vs. input level, output current –40 –50 –60 Output current 5 10 Conditions: Input: Pin 6, 250mVp-p Output: Pin 37 Logic A Input level 5 Conditions: Input: Pin 46, 250mVp-p, 100kHz Output: Pin 24 Logic A Mix AMP Y output secondary distortion factor vs. Frequency 2 1 2 3 4 ATF LEVEL pin voltage [V] –40 –50 Second –60 Third –16–14–12–10 –8 –6 –4 0 [dBm] 6 [mAp-p] 8 10 1315 20 2 Conditions: Input: At resistance (2.2kΩ) with Pin 25, 5MHz Output: Pin 28, load resistance: 100Ω Logic A 4 6 8 f – Frequency [MHz] 10 Conditions: Input: At resistance (2.2kΩ) with Pin 25, 200mVp-p Output: Pin 28, load resistance: 100Ω Logic A – 22 – CXA1202Q-Z/CXA1202R V RF OUT secondary distortion factor vs. Input level Secondary distortion factor [dB] Change in output level [dB] Head AMP output level vs. Frequency 5 0 –5 2 4 6 8 f – Frequency [MHz] –50 –60 –6 –4 –2 0 2 4 6 Input level [dB] 10 Conditions: Input: 25µm-wide head for NTSC, 100mVp-p at head tip Output: Pin 20 Logic H, medium range freq. conpensation circuit boost: 0 CH1 → CH2 crosstalk at PCM RF OUT vs. Frequency Crosstalk [dB] –30 –40 –30 –40 –50 –50 2 4 6 8 f – Frequency [MHz] Conditions: Input: Pin 29, 200µVp-p Output: Pin 20 Logic I 2 Crosstalk 29 20 32 0.1µF 4 6 8 f – Frequency [MHz] Conditions: Input: Pin 29, 200µVp-p 29 Output: Pin 8 Logic H 32 0.1µF Crosstalk 2 Medium range freq. compensation circuit MT2 pin voltage vs. Amount of boost Amount of boost [dB] Crosstalk in MUTE at V RF OUT vs. Frequency Crosstalk [dB] 8 10 12 Conditions: Input: Pin 29, 0dB = 200mVp-p, 5MHz Output: Pin 20 Logic H CH1 → CH2 crosstalk at RF OUT vs. Frequency Crosstalk [dB] –40 –50 –60 –70 14 12 10 8 6 4 2 0 2 4 6 8 f – Frequency [MHz] Conditions: Input: Pin 29, 200µVp-p Output: Pin 20 Pin 41 voltage: 5V Logic H 29 1 10 Crosstalk 20 – 23 – 2 3 4 MT2 pin voltage [V] Conditions: MT Fφ pin: 18kΩ MT Q pin: 33kΩ 5 CXA1202Q-Z/CXA1202R Medium range freq. compensation circuit MT Fφ, MT Q pin connection resistance value vs. Fφ Medium range freq. compensation circuit MT Fφ, MT Q pin connection resistance value vs. Q 12 MT Q pin connection resistance value [kΩ] MT Q pin connection resistance value [kΩ] 10 4.0 8 3.0 15 22 2.0 33 47 68 Q Fφ [MHz] 10 6 4 10 15 22 33 47 68 1.0 2 Medium range freq. compensation circuit boost amount vs. Operating temperature Medium range freq. compensation circuit Fφ, vs. Operating temperature Change in Fφ [kHz] 20 40 60 80 MT Fφ pin connection resistance value [kΩ] Amount of boost [dB] 20 40 60 80 MT Fφ pin connection resistance value [kΩ] 13 12 11 10 200 100 0 –100 –200 –20 0 20 40 60 80 Topr – Operating temperature [°C] –20 0 20 40 60 80 Topr – Operating temperature [°C] Conditions: Input: Pin 29 Output: Pin 20 Pin 23 voltage: 4.2V Logic H Conditions: Input: Pin 29 Output: Pin 20 Pin 23 voltage: 4.2V Q pin connection resistance value: 33kΩ Fφ pin connection resistance value: 18kΩ AGC output level vs. Operating temperature Difference in output level [dB] 0dB = 100mVp-p Output level [dB] RF AGC Control characteristics 2 1 0 –1 –2 –3 –4 –5 –6 VCC 0.047µF 150kΩ 9 1 0 –1 –20 0 20 40 60 80 Topr – Operating temperature [°C] –16–12 –8 –4 0 4 8 12 16 18 0dB = head tip, 100µVp-p [dB] Conditions: Input: Pin 29, 5MHz, 170µVp-p Output: Pin 10 Logic H Conditions: Input: 25µm-wide head for NTSC, 5MHz Output: Pin 10 Logic I Pin 9 time constant: R: 150kΩ, C = 0.047µF – 24 – CXA1202Q-Z/CXA1202R Dropout detection ON level vs. Operating temperature Dropout detection OFF level vs. Operating temperature VCC 150kΩ VCC 150kΩ 15 220pF OFF level [dB] ON level [dB] 15 100kΩ –10 –11 –12 –13 –5 –6 –7 –8 –15 –9 –20 0 20 40 60 80 Topr – Operating temperature [°C] Conditions: Input: Pin 14 400mVp-p to 0dB at Pin 16 Logic H Conditions: Input: Pin 14 400mVp-p to 0dB at Pin 16 Logic H RF SW Crosstalk (A → B) vs. Frequency 0 –10 –20 –30 –40 –50 –60 2 4 6 8 f – Frequency [MHz] Conditions: Input: Pin 12, 100mVp-p Output: Pin 16 Logic H Pin 11 = 3V 220pF –4 –14 –20 0 20 40 60 80 Topr – Operating temperature [°C] Crosstalk [dB] 100kΩ 10 Crosstalk 0.01µ 12 16 14 0.01µ – 25 – CXA1202Q-Z/CXA1202R Package Outline Unit: mm CXA1202Q-Z 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 0.15 36 25 24 48 13 13.5 37 12 + 0.15 0.3 – 0.1 0.8 0.24 M 0.9 ± 0.2 1 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE SONY CODE QFP-48P-L04 EIAJ CODE QFP048-P-1212 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER / PALLADIUM PLATING LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN LQFP (PLASTIC) CXA1202R 9.0 ± 0.2 7.0 ± 0.1 36 37 24 48 13 (8.0) 25 A 0.5 ± 0.2 ∗ (0.22) 12 1 + 0.05 0.127 – 0.02 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 0.13 M 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE LQFP-48P-L01 LEAD TREATMENT EIAJ CODE LQFP048-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 26 –