CXA1843Q High-Speed Sample-and-Hold IC For the availability of this product, please contact the sales office. Description The CXA1843Q is a bipolar IC designed to sampleand-hold video and various other signals with high speed. It is ideal for video and other signal conversions. Features • Maximum operating rate = 33MHz (min.) • Low power consumption: 320mW • S/H clock pulse generator circuit • Built-in clock pulse generator for A/D converter Structure Bipolar silicon monolithic IC 4.75 to 5.25 –4.75 to –5.25 V V –20 to +75 °C 21 20 AVCC4 22 REF IN 23 19 18 17 REX2 CLKOUT GND 24 NC 25 NC DVCC1 Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC 7 V VEE –7 V • Input voltage (VIN pin) VIN VEE to AVCC + 0.3 V (REFIN pin) VREFIN +1 to AVCC + 0.3 V (CLKIN pin) VCLK GND – 0.5 to DVCC + 0.3 V (REX 2, 3, 4 pins) VREX2, 3, 4 GND to GND + 4 V • Reference voltage (REFFB pin) VREFFB VEE to +3 V (REFOUT pin) VREFOUT VEE to AVCC + 0.3 V • Output current (REFFOUT pin) IREFOUT –1 to +1 mA (SHOUT pin) ISHOUT –12 to +12 mA (CLKOUT pin) IADC –1.5 to +1.5 mA • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.1 W Block Diagram and Pin Configuration DVCC2 Applications When used in combination of the CXA1844Q, the CXA1843Q achieves A/D conversion. Operating Conditions • Supply voltage VCC VEE • Operating temperature Topr 32 pin QFP (PIastic) A/D CONVERTER PULSE GENERATOR DVEE1 26 REF DC 16 SHIFT 15 REX3 27 SAMPLE HOLD PULSE GENERATOR REX4 28 DVEE2 29 DVCC3 30 SAMPLE HOLD CLK IN 31 5 6 7 8 NC NC NC HGND 4 CGND AVCC1 3 VIN 2 AVEE1 1 REFFB 14 REFOUT 13 AVEE3 12 AVCC3 11 SHOUT 10 AVEE2 9 NC 32 NC NC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E92855B7Y CXA1843Q Pin Description Pin No. 1 Symbol AVCC1 Pin voltage Equivalent circuit Description Analog positive power supply. 5V (Typ.) AVCC1 2 HGND Internal resistance GND for sample-and-hold. 0V HGND VIN 130 30k 3 VIN — Sample-and-hold-input. DVEE2 4 AVEE1 –5V (Typ.) 5 CGND 0V Analog negative power supply. Internal capacitance GND for sample-and-hold. AVCC1 AVEE1 500µ 500µ CGND DVEE2 6 NC — Connect to AGND. 7 NC — Connect to AGND. 8 NC — Connect to AGND. 9 NC — Connect to AGND. 10 AVEE2 –5V (Typ.) Analog negative power supply. AVCC3 11 SHOUT SHOUT DVEE2 –2– Sample-and-hold output. CXA1843Q Pin No. Symbol Pin voltage Equivalent circuit Description 12 AVCC3 5V (Typ.) Analog positive power supply. 13 AVEE3 –5V (Typ.) Analog negative power supply. 14 REFOUT 15 REFFB 16 NC 17 AVCC4 –2.8V As shown in the Application Circuit, PNP TR. is connected and 2.5V is applied to Pin18. –2V As shown in the Application Circuit, PNP TR. is connected and 2.5V is applied to Pin18. Connect the base of the external PNP transistor to create a –2V power supply. AVCC4 400µ 130 REFFB REFOUT DVEE2 AVEE3 Connect the emitter of the external PNP transistor to create a –2V power supply. Connect to AGND. — 5V (Typ.) Analog positive power supply. AVCC4 18 REFIN 2.5V (Typ.) External DC input for adjusting the –2V power supply. REFIN 130 300µ GND DVEE2 DVCC2 19 REX2 Approx. 0.5V When external resistor is connected between Pin 19 and AGND 1k 130 REX2 0.5V Connect external resistor that determines the time interval (T2) between master clock (MCLK) rise and A/D converter clock (A/D CLK) fall. (Normally connect to 1.6kΩ) GND DVEE2 20 NC — Connect to AGND. –3– CXA1843Q Pin No. 21 Symbol GND Pin voltage Equivalent circuit Description GND 0V DVCC2 600 H: DVCC2 – 0.78V 22 CLKOUT L: DVCC2 – 1.52V (Typ.) CLKOUT 2.2mA A/D converter clock (A/D CLK) output. GND DVEE2 23 DVCC1 5V (Typ.) Digital positive power supply. 24 DVCC2 5V (Typ.) Digital positive power supply. 25 NC 26 DVEE1 –5V (Typ.) DVCC2 REX3 Approx. 0.5V When external resistor is connected between Pin 27 and DGND Approx. 0.5V When external resistor is connected between Pin 28 and DGND REX3 27 28 REX4 Connect to DGND — Digital negative power supply. Connect external resistor that determines the time interval (T3) between master clock (MCLK) rise and sample-and-hold internal clock (S/H CLK) rise. (Normally connect 2.7kΩ) 1k 130 REX4 1k 130 0.5V GND DVEE2 Connect external resistor that determines the time interval (T4) between master clock (MCLK) rise and sample-and-hold internal clock (S/H CLK) rise. (Normally connect 1.5kΩ) 29 DVEE2 –5V (Typ.) Digital negative power supply. 30 DVCC3 5V (Typ.) Digital positive power supply. DVCC3 31 CLKIN — CLKIN Master clock (MCLK) input. TTL level. (Vth = 1.5V) 130 GND 300µ DVEE2 32 NC Connect to DGND. — –4– CXA1843Q Electrical Characteristics Item Maximun operating rate Current consumption (Ta = 25°C, VCC = 5V, VEE = –5V) Conditions Symbol Min. Typ. Max. Unit FC 33 ICC 32 41 50 mA IEE –28 –23 –18 mA 1 20 50 µA 0.2 V MHz S/H Amplifier Block VIN input current IVIN VIN = –1V VIN input voltage range VIN FIN = 1kHz, distortion factor ≤ –55dB –2.2 Droop HMDR VIN = –2V to 0V –20 20 80 mV/µs Feed through HMTH FIN = 16.5MHz (2Vp-p) –40 –50 –70 dB VIN = –1V, FCLK = 33MHz 55 90 120 mV –0.5 0.3 0.5 dB S/H output offset voltage VOFFSET S/H output gain Gsh FIN = 1kHz (2Vp-p), FCLK = 33MHz S/H output frequency response Fsh 20Log (VO (16.5MHz)/VO (200kHz)), Sampling time = 14ns –1 0.2 1 dB S/H output slew rate SR CL = 50pF 140 160 200 V/µs REFIN input current IREFIN VREFIN = 2.5V 0 1 10 µA REFFB output voltage VREFFB VREFIN = 2.5V –2.2 –2.0 –1.8 V ICLKL VCLKIN = 0V –10 –6 0 µA ICLKH VCLKIN = 5V 0 0 1 µA 0.8 V Reference Amplifier Block Digital I/O Block CLKIN input current CLKIN input voltage CLKIN clock width VCLKL VCLKH 2.0 V TPWH 9 ns TPWL 9 ns A/D clock low level VADCL A/D clock high level VADCH VCC – 1.52 VCC – 1.40 VCC – 0.90 VCC – 0.78 –5– V V CXA1843Q Timing Chart N+1 N+2 VIN (Pin 3) (0 to –2V) N Tsd Tsd Tsd TPWL TPWH Threshold voltage = 1.5V MCLK(Pin 31) (TTL) T4 T3 Hold S/H CLK (Not output to outside) Sample Sample Hold Hold Sample Hold Threshold voltage taqr tdr 10% S/H OUT (Pin 11) (0 to –2V) 90% N+1 N N–1 90% 2Vp-p N+2 10% tdf taqf A/D CLK (Pin 22) (PECL) Threshold voltage = VCC – 1.2V T1 = 6ns tD (max) T2 tD (min) A/D output (CXA1844Q) (TTL) DN – 3 Threshold voltage = 1.5V DN DN – 1 DN – 2 TS Th MCLK (Clock pulse for the device next to the ADC in order to latch the A/D output) Threshold voltage = 1.5V MCLK: S/H CLK: System master clock. This clock actuates the internal sample-and-hold circuit. The internal clock pulse circuit generates the S/H CLK, which is not output outside the IC. A/D CLK: This clock actuates the A/D converter. The internal clock buffer circuit generates the A/D CLK. This clock has the level where +5V is shifted from the ECL level. TPWH, TPWL: S/H CLKIN input clock width Tsd: S/H sampling delay for the S/H internal clock T1: Fixed time interval between master clock rise and A/D CLK rise, T1 = 6ns (typ.) T2: Time interval between MCLK rise and A/D CLK fall T3: Time interval between MCLK rise and S/H CLK rise T4: Time interval between MCLK rise and S/H CLK fall taqf, tdf: 10%/90% falling output delay of S/H from MCLK rise taqr, tdr: 10%/90% rising output delay of S/H from MCLK rise tD (min., max.): Minimum/maximum output delay of A/D converter (Refer to the CXA1844Q specification.) Ts: Setup time of A/D output and MCLK Th: Hold time of A/D output and MCLK –6– TTL DGND 0.1µ DGND 5V 0.1µ DGND REX4 0.1µ DGND REX3 0.1µ DGND 0.1µ DGND AGND 32 31 30 29 28 27 DVEE1 26 5V AGND 2 1 0.1µ (NC) 5 1.6kΩ 2.7kΩ 1.5kΩ REX2 REX3 REX4 ∗ Metal film resistors must be connected to the REX2 to REX4 pins. External resistance Symbol 7 6 8 AGND 0.1µ 9 10 11 12 AGND 0.1µ AGND 0.1µ –5V 5V 200 50 50 47µ 42 0.1µ 41 40 39 38 37 0.1µ AGND 0.1µ UNDER OVER DGND 5V –5V D1 D2 3 2 1 D0 D2 DGND1 48 D1 OVER 47 D0 UNDER DVCC2 AVEE (NC) AGND (NC) VINH VINL (NC) (NC) D3 4 D3 D4 5 D4 DGND DGND 7 6 CXA1844Q D5 8 D5 D7 10 9 D6 D7 D6 D8 11 D8 PS 17 16 DVEE DGND1 D9 12 D9 DGND1 13 DGND1 14 DVCC1 15 18 19 (NC) DGND2 20 21 22 23 24 LINV MINV CLK ENABLE 25 26 27 28 29 30 31 0.1µ 32 0.1µ 33 0.1µ DGND DGND 34 0.1µ AGND AGND AGND AGND 35 47µ AGND AGND 36 46 45 44 AGND AGND 43 D1 –5V 5V 0.1µ P1 25A1005 AGND AGND AGND 13 AGND 14 15 16 AGND 0.1µ DGND 0.1µ DGND –5V DGND DGND 5V DGND DGND LINV MINV ENABLE PS Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 0.1µ AGND AGND AGND AGND –5V 4 VIN = 2Vp-p (max) DC – 1V 3 (NC) AVEE2 CLKIN AVCC3 SHOUT VIN CXA1843Q AVEE3 REFOUT REFFB (NC) DVCC3 DVEE2 REX4 REX3 (NC) 25 17 18 19 20 CXA1843Q External Resistance MCLK –5V DGND DGND –5V DGND 5V 5V 0.1µ 21 0.1µ 47µ 22 2k 23 DGND 24 DGND 0.1µ DGND DVCC2 DGND DGND 0.1µ DGND REX2 DVCC1 VIN 0.1µ 5V (NC) 5V VREFBS 62 VREFB 1k 430 VREF3 AGND VREF2 CLKOUT AVCC1 VREF1 GND HGND VREFT (NC) AVEE1 VREFTS REX2 CGND (NC) REFIN (NC) (NC) AVCC4 (NC) DGND3 DGND1 –7– DGND1 (NC) DGND4 Application Circuit CXA1843Q CXA1843Q Notes on Operation (1) In circuit board layout, it is necessary that the AGND and DGND patterns be as large as possible and that double or more layer pattern be used to make low impedance. (2) To prevent digital system noise interference with the analog system, the AGND and DGND, AVCC and DVCC, AVEE and DVEE on the PCB must be separated from each other. However, connect the AVEE and DVEE with coil and others to prevent the generation of differential voltage. (3) The AVCC, DVCC, AVEE and DVEE pins must be connected to the AGND or DGND respectively via ceramic chip capacitors those are 0.1µF or more, as close to the pin as possible. (4) The length of the wiring between the S/H SHOUT and A/D converter VIN should be as short as possible. (5) The range of the signal input to VIN (Pin 3) of the sample-and-hold circuit is 0 to –2V. (6) Adjust the VREFIN applied voltage so that VREFFB = f – 2V. (7) As shown in the Block Diagram, the amplifier input and output are internally connected to the REFOUT and REFFB pins. To generate REFFB voltage for the reference voltage of A/D converter, the connection of an external PNP transistor (hFE ≥ 100 (typ.)) is required as shown in the Application Circuit. (8) Make the S/H DVCC2 voltage equal to the A/D converter DVCC1 voltage. –8– CXA1843Q Example of Representative Characteristics ICC vs. Ta IEE vs. Ta –21 41 –22 IEE [mA] ICC [mA] 42 40 39 –25 –23 0 25 Ta [°C] 50 –24 –25 75 ICC vs. VCC 0 25 Ta [°C] 50 75 IEE vs. VEE –19 43 42 –20 41 40 IEE [mA] ICC [mA] –21 39 –22 –23 38 –24 37 36 4.75 5 VCC [V] –25 –5.25 5.25 VOFFSET vs. VCC VOFFSET vs. VEE VIN = –2V VIN = –2V 95 VOFFSET [mA] 95 VOFFSET [mA] –4.75 100 100 VIN = –1V 90 VIN = –1V 90 VIN = 0V VIN = 0V 85 80 4.75 –5 VEE [V] 85 5 VCC [V] 80 –5.25 5.25 –9– –5 VEE [V] –4.75 CXA1843Q VOFFSET vs. Ta A/D converter reference voltage vs. Input voltage VREFFB – A/D converter reference voltage [V] 120 110 VOFFSET [mV] VIN = –2V 100 VIN = –1V 90 VIN = 0V 80 70 60 –25 –1.4 –1.6 –1.8 –2 –2.2 –2.4 –2.6 0 25 Ta [°C] 50 2 75 –1.99 VREFFB – A/D converter reference voltage [V] –2.004 –1.995 –2 –2.005 0 25 Ta [°C] 50 –2.005 –2.006 –2.007 –2.008 –2.009 –2.01 4.75 75 5 VCC [V] A/D converter reference voltage vs. VEE (VREFFIN = 2.5V) –2.004 VREFFB – A/D converter reference voltage [V] VREFFB – A/D converter reference voltage [V] 3 A/D converter reference voltage vs. VCC (VREFFIN = 2.5V) A/D converter reference voltage vs Ta (VREFFIN = 2.5V) –2.01 –25 2.5 VREFFIN – Input voltage [V] –2.005 –2.006 –2.007 –2.008 –2.009 –2.01 –5.25 –5 VEE [V] – 10 – –4.75 5.25 CXA1843Q A/D clock width Tpwh (T2-T1) variation vs. Ta (Ta = 25°C typ.) T2 vs. REX2 1 A/D clock width Tpwh variation [ns] 40 35 T2 [ns] 30 25 20 15 10 0 1 2 0.5 0 –0.5 –1 –25 3 0 REX2 [kΩ] For normal use. REX = 21.6kΩ A/D clock width Tpwh (T2-T1) variation vs. VCC (VCC = 5.0V typ.) 75 1 A/D clock width Tpwh variation [ns] A/D clock width Tpwh variation [ns] 50 A/D clock width Tpwh (T2-T1) variation vs. VEE (VEE = –5.0V typ.) 1 0.5 0 –0.5 –1 4.75 5 VCC [V] 0.5 0 –0.5 –1 –5.25 5.25 –5 VEE [V] –4.75 S/H output delay variation vs. Ta (Ta = 25°C typ.) S/H output delay (tdr, tdf) vs. REX3 (taqr, taqf) vs. REX4 45 1.5 S/H output delay variation [ns] 40 taqf tdr, tdf, taqr, taqf [ns] 25 Ta [°C] taqr 35 30 tdr 25 tdf 20 1 0.5 0 –0.5 –1 15 2 1.1 3 4 2 For normal use, REX3 = 2.7kΩ REX4 = 1.5kΩ 5 REX3 [kΩ] 2.8 REX4 [kΩ] – 11 – –1.5 –25 0 25 Ta [°C] 50 75 CXA1843Q S/H output delay variation vs. VCC (VCC = 5.0V typ.) S/H output delay variation vs. VEE (VEE = –5.0V typ.) S/H output delay variation [ns] 1 0.5 0 –0.5 –1 4.75 5 VCC [V] 0.5 0 –0.5 –1 –5.5 5.25 –5 VEE [V] –4.5 Input frequency vs. S/N ratio for CXA1843Q + CXA1844Q (clock frequency = 33MHz) 60 Amplitude = 2Vp-p 55 Amplitude = 1Vp-p 50 S/N ratio [dB] S/H output delay variation [ns] 1 45 40 35 30 0.001 0.01 0.1 Input frequency [MHz] – 12 – 1 10 20 CXA1843Q S/H + A/D EVALUATION BOARD The S/H + A/D Evaluation Board is a printed circuit board for evaluating the 10-bit 33MSPS high speed sample-and-hold IC (CXA1843Q) and 2-step A/D converter (CXA1844Q). This board is designed to enable users to make full use of the performance of CXA1843Q + CXA1844Q and evaluate them easily. Features • Resolution • Maximum operating conversion speed • 2 types analog input • Analog input dynamic range • Digital output level • Power supply voltage • Built-in D/A converter (For evaluation) 10bit 33MSPS VIN input (OP AMP input) and DIR. IN input (AC coupled input) are available. 2Vp-p TTL ±5V Generates the analog waveform. Block Diaram S2 CLK input (CON4) CLK/16 CLK/8 CLK/4 CLK/2 Counter 50Ω CLK/N 10 10 Latch DGND CLK CON MINV LINV DAINV PS SW1 Buffer ENABLE Buffer FULSCAL ADJ VR2 A/D CLK 10bit A/D VRBS –2.0V S/H 2.5V VIN OFFSET ADJ OP VR1 AMP AGND × 2 Analog input VIN (CON1) 50Ω Latch 10 TTL → ECL A REX2 1.6kΩ REX3 2.7kΩ REX4 1.5kΩ S/H OUT S1 B VEE GND VCC (–5V) (+5V) 50Ω AGND AGND VEE 10bit D/A VRB VIN L VIN H AGND Analog input DIR.IN (CON2) 10 18Ω MCLK AGND CLK/N 10 VREFBS REF IN REFB A/D OUT S/H + A/D Evaluation Board Block Diagram – 13 – D/A OUT (CON3) CXA1843Q Connection and Setting for S/H + A/D Evaluation Board 1. Power supply voltage (CON6) Item Min. Typ. Max. Unit Typical current Unit Vcc +4.75 +5.0 +5.25 V 220 mA VEE –5.25 –5.0 –4.75 V –400 mA 2. Analog input (CON1, CON2) and offset adjustment (VR1) [VIN Input] (CON1) When the amplitude of an analog input signal supplied to the sample-and-hold is 1Vp-p and its input range is within 1.0V to –0.9V, the board is able to amplify its amplitude by two times using the operation amplifier. The S1 selector should be short-circuited at side A and opened at side B, and the analog input is added from CON1. In this case, offset adjustment is required at the VR1, so that the dynamic range of the analog input signal can be set to a value between 0V to –2V by monitoring the VIN pin. [DIR IN. Input] (CON2) When the input supplied to the sample-and-hold is a recurring signal (sine wave, etc.) without offset, it is added using the AC coupled input from CON2 by connecting a 10kΩ resistor to side A and a 0.1µF capacitor to side B of the S1 selector. In this case, offset adjustment is required at the VR1, so that the dynamic range of the analog input signal can be set to a value between 0V to –2V by monitoring the VIN pin. S1 setting Item Min. VIN input (CON1) –0.9 DIR. IN input (CON2) –2.0 Typ. 0 Max. Amplitude Unit A B 1.0 1.0 V short open 2.0 2.0 V 10kΩ 0.1µF (CON1 and CON2 are terminated to AGND at 50Ω on the board.) 3. Clock input (CON4) TTL compatible Use in the 30 to 70% CLK duty range (CON4 is terminated to DGND at 50Ω on the board.) 4. Digital output (CON5) TTL compatible C-MOS (ACT series) output – 14 – CXA1843Q 5. D/A out (CON3) and full-scale adjustment (VR2) The output waveforms of the D/A converter are output from CON3. When an oscilloscope or other such instrument is used for monitoring, a 50Ω terminating resistor is required. The full-scale output voltage must also be adjusted. And the output amplitude should also be adjusted to 1Vp-p by the VR2. Item D/A OUT Min. –1.0 Typ. Max. Unit 0 V 6. SW1 setting These are the switches for PS, ENABLE, MINV, and LINV of the A/D converter and the DAINV of the D/A converter. Normally all are used ON. 7. S2 setting This is the selection of the frequency division ratio for the clock which is supplied to the D/A converter. Normally, 1/1 is used but the ratios from 1/2 to 1/16 are also used for the envelope test or other tests. – 15 – CXA1843Q CXA1843Q + CXA1844Q PCB Timing Chart N N+1 Analog input (0 to –2V) N+2 CLK input (TTL) MCLK (TTL) T4 T3 SH CLK (internal) Sample Hold S H S H N SH Analog out (0 to –2V) N+1 TH T2 AD CLK (PECL) T1 N+2 TL Tpwl Tpwh tdmax AD Data out (TTL) tdmin N–2 N–1 N Latch CLK input (TTL) Latch Data out (TTL) N–3 N–2 N–1 CON5 Data out (TTL) N–4 N–3 N–2 DAC Data input (ECL) N–3 N–2 N–1 DAC CLK input (ECL) N–2 N–3 DAC Data OUT (0 to –1V) N–4 Item S/H CLK delay A/D CLK delay A/D CLK width A/D output data delay Symbol Min. Typ. Max. Unit T3 20 ns T4 33 ns T1 6 ns T2 20 ns tpwh 14 ns tpwl 13 ns td 4 – 16 – 18 ns CXA1843Q S/H + A/D Evaluation Board Parts List (No.) (Product Name) (Function) (No.) (Product Name) (Function) IC.1 CXA1843Q Sample Hold R1, 13, 38 FRD-25SR (0.25W) 51Ω IC.2 CXA1844Q 10bit ADC R21, 25 FRD-25SR (0.25W) 100Ω IC.3 CLC505 OP-AMP R2, 22 FRD-25SR (0.25W) 270Ω IC.4 CX20201A-1 DAC R3, 4 FRD-25SR (0.25W) 470Ω IC.5 74ACT34 Buffer R23 FRD-25SR (0.25W) 1kΩ IC.6 74ACT163 Counter R12 FRD-25SR (0.25W) 4.7kΩ IC.7 74ACT16821 Latch R5, 8, 15, 16, 18, 19 FRD-25SR (0.25W) 10kΩ IC.8, 9 MB767 ECL → TTL level translator R24 FRD-25SR (0.25W) 51kΩ D1, 3 TL431CP 3-pin shunt regulator R11 FRD-25SR (0.25W) 150kΩ D2 1S1555 Diode R9 SN14C2F 1.5kΩ P1 2SA1175 PNP transistor R14 SN14C2F 1.6kΩ SW.1 DSS-105 Switch R10 SN14C2F 2.7kΩ SMA connector R6, 7, 17, 20 Chip resistor CON.1 to 4 TMA5502-10 CON.5 FAP-2601-1201 Flat cable connector RN1 to 3 RGLD 4X621J 620Ω CON.6 TJ-563 Power supply connector C2, 9 to 17, 19, 23 to 32 Chip capacitor 0.1µF S1.3 JX-1 Short-pin VR1.2 RJ-6P 2kΩ volume resistor Tantalum capacitor 1µF (Voltage proof of 35V) C1 to 11 LS-2S Check pin C18 Ceramic capacitor 100pF L1 to 4 SF-T5-30-03 30µF 34 to 40, 42 to 60 C1, 6 to 8, 33, 41 C3 to 5, 20 to 22 33µF (Voltage proof of 35V) Precautions 1. The monitoring pins are designed to be easily grounded in order to minimize distortions occurring when monitoring waveforms on an oscilloscope. Waveform monitoring is facilitated by using the grounded tip (part No. 013-1185-00) made by Tektronix at the end of the probe. 2. VR1 and VR2 are optimally adjusted and set before the board is shipped. 3. REX2, REX3, REX4 (R14, R10, R9) on the board use metal-oxide resistor, and T2, T3, T4 are optimally adjusted and set within the range of 1MHz to 33MHz. – 17 – CXA1843Q S/H + A/D EVALUATION BOARD (Component Side) S/H + A/D EVALUATION BOARD (Solder Side) – 18 – R10 2.7k R9 1.5k 31 32 32 2 3 NC 1 CLK IN DVCC3 DVEE2 19 20 IC.1 4 5 AGND 18 NC 17 16 16 AVCC3 8 9 AGND C28 0.1µ C31 0.1µ C30 0.1µ C29 0.1µ C32 0.1µ S/H out P3 DVEE AVEE AVCC P1 D/A out AGND CON.3 AGND DGND 39 21 R21 100 NC NC 23 24 VREF AGND2 AVEE NC NC NC 19 22 AGND1 18 NC DGND 17 21 INV OUT 17 DVCC 47 2 D1 48 CLK C4 R37 620 NC 12 R36 620 DGND NC 11 R35 620 D10 10 R34 620 D9 9 R33 620 D8 8 R32 620 D7 7 R31 620 D6 6 R30 620 D5 5 R29 620 D4 4 R28 620 D3 3 R27 620 D2 2 R26 620 D1 1 1 14 13 CLKB 14 AGND 1 RN3 C49 0.1µ RN2 C50 0.1µ RN1 C51 0.1µ DGND DVEE 1 3 D2 D0 5 4 D3 6 GND1 D4 8 9 D6 7 10 D7 D5 11 GND1 12 D8 12 DGND 13 D9 13 DGND 46 14 DVCC D2 AVEE C3 45 15 16 48 44 43 IC.2 42 20 DVEE DGND CXA1844Q 18 19 SW1 41 DVEE 40 20 16 15 15 AGND 38 37 NC 36 37 36 VRFEB VREFBS 34 VRFE3 35 33 VRFE2 VRFE1 32 31 VREFTS 29 VRFET NC NC 28 30 22 DGND 27 DGND4 DGND3 23 FULL 25 C43 0.1µ SCALE ADJ 26 VR2 2K 27 C47 C41 1µ R23 1k 0.1µ 28 28 10 Vref AGND R1 21 C D3 A AVEE 8 NC AVEE2 9 12 AVEE3 SHOUT 11 13 REFOUT 14 7 C34 0.1µ C35 0.1µ C33 1µ C1 AGND VREFBS 17 AGND C26 0.1µ AGND AVCC AGND 24 25 24 R15R18 10k 10k R16R19 10k 10k DVCC MINV DAINV PS LINV ENABLE 26 25 VREFTS C36 0.1µ C2 DGND REFFB 15 6 CXA1843Q 21 22 1 C2 AVCC 0.1µ C23 C19 R2 R3 0.1µ 0.1µ C1 270 470 C6 1µ AVCC AVEE C 1µ D1 R5 AGND A Vref 10k AVCC AGND VR1 AGND 2K C15 C8 OFFSET 0.1µ 1µ VIN P1 AGND ADJ R8 AGND AGND 10k CON.1 VIN R12 7 15 R4 S1 2 47 4.7k R1 8 IC.3 A 51 6 3 4 R11 C18 AGND B 150k 100P C14 C7 R13 AGND 0.1µ 1µ 51 CON.2 AVEE AGND AGND AGND DIR.in DGND DGND 30 29 25 25 NC C13 0.1µ 26 C12 DVEE1 0.1µ 27 REX3 C9 0.1µ 28 REX4 DGND DVEE C11 DVCC DVCC 0.1µ C10 R7 0.1µ R6 DGND DVEE 23 DVCC2 DVCC1 24 CLK OUT VIN AVCC1 HGND DGND C25 0.1µ C17 DVCC R14 0.1µ DGND 1.6k C24 0.1µ C16 0.1µ 24 ADCLK P4 NC NC P2 VCC GND AVEE1 AVCC4 NC REX2 CGND REFIN NC MCLK GND L4 C6 DVCC2 (+5V) 7µH DVCC2 CON.6 C22 33µ DGND2 GND C8 DVCC (+5V) L1 L3 DVCC DVEE C21 7µH C4 7µH C11 33µ 33µ DGND DGND AVEE (–5V) C9 C10 AVCC (+5V) AGND DGND2 AVCC AVEE DGND C3 C20 33µ 33µ AGND AGND VEE DVEE2 (–5V) C5 L2 7µH DVEE2 C5 33µ DGND2 DVEE (–5V) C7 C42 0.1µ C27 0.1µ PS NC NC C46 0.1µ NC C37 ENABLE CLK R24 51k LINV AVF NC 0.1µ MINV VINH VINL R17 DVEE C39 0.1µ C48 R20 C40 0.1µ R25 100 C38 0.1µ CX20201A-1 DGND1 DVCC2 C45 0.1µ DVCC1 UNDER 0.1µ AVCC DGND2 AVEE NC GND1 GND1 OVER GND1 C44 0.1µ OVER DGND DGND DGND MSB C8 C7 C6 C5 C4 C3 C2 C1 LSB MSB D8 D7 D6 D5 D4 D3 D2 D1 1 74ACT34 IC.5 1 2 3 4 5 55 9 2 54 12 53 4 52 5 18 3 51 6 16 MB767 4 50 8 6 5 9 8 7 12 9 16 15 1 12 11 11 10 10 1 IC.8 11 18 3 2 19 13 14 43 44 41 42 6 5 4 3 1 11 20 20 DGND2 10 45 46 12 10 19 13 12 7 9 14 8 15 20 6 DGND2 MB767 4 IC.7 5 16 18 37 35 36 DVCC2 38 DGND2 17 DGND2 17 8 9 DGND2 39 DVCC2 16 8 40 ACT1682 1 15 9 DGND2 7 74ACT163 IC.6 DGND2 2 14 13 1/1 1/2 1/4 1/8 1/16 S2 DGND2 47 14 13 DGND2 7 49 1 16 DGND2 DVCC2 48 14 DVCC2 15 DGND2 17 14 1 DGND2 13 DVCC2 DGND2 3 2 19 11 DGND2 10 1 20 20 CLK 1 LSB 56 8 CLK DGND2 CON.4 6 DGND2 1 56 8 7 7 DGND2 GND IN2 OUT2 IN1 5A GND GND 4A 1D1 5Y 1D2 1Q2 IN3 OUT3 OUT1 C52 IN4 OUT4 1Q1 6Y 1D3 1Q3 S DVEE2 UNDER 3A 3Y VCC GND C53 0.1µ 4Y 2A 2Y IN5 OUT5 DGND2 VEE VCC IN6 1OE_ 1CLK 1A 1Y VCC C54 0.1µ 1D5 1Q5 1D6 6A 1D4 1Q4 0.1µ C59 VCC 0.1µ 1D7 A OUT A IN 1D9 1Q9 IN2 OUT2 1Q6 OUT6 GND GND C OUT B IN OUT1 DVCC2 IN7 OUT7 1Q7 IN8 OUT8 EN T C56 0.1µ VCC CLEAR RCarry CLK 1D8 1Q8 IN1 B OUT C IN 2D1 R38 51 1Q10 1D10 IN3 OUT3 2Q1 IN4 OUT4 VCC D OUT S 21 11 10 10 IC.9 11 DGND2 26 25 24 23 DGND2 22 31 32 DGND2 33 34 2D7 D IN 2D2 2Q2 C57 VEE DVEE2 2D8 2Q8 LOAD VCC GND 30 29 28 28 29 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 DVCC2 DGND DGND DGND DVCC CON.5 DGND CLK DGND2 LSB D1 D2 D3 D4 D5 D6 D7 D8 MSB DGND2 27 2Q10 2D10 EN P 2D3 2Q3 0.1µ 2D4 IN5 OUT5 C58 0.1µ 2OE_ 2CLK GND GND GND 2D5 2Q4 IN6 OUT6 GND GND 2Q7 2D6 VCC 0.1µ 2Q5 IN7 OUT7 2D9 2Q9 DVCC2 2Q6 C59 IN8 OUT8 CLK C60 0.1µ – 19 – DGND2 S/H + A/D Evaluation Board CXA1843Q CXA1843Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-32P-L01 LEAD TREATMENT EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE – 20 – 0.50 8