CXA1852N Quadrature Modulator for 900 MHz-Band Mobile Communications For the availability of this product, please contact the sales office. Description The CXA1852N is an IC package that combines a π/2 phase shifter with a quadrature modulator. This is suitable for 900 MHz digital cordless telephone (CT2) and digital cellular. Features • Quadrature modulator IC has a built-in π/2 phase shifter. • Local frequency = 300.1 MHz (max.); I&Q = 36 kHz (max.) • Small phase error • Operating voltage range: 2.7 to 5 V • Power saving function • 20-pin SSOP package used for set size reduction Applications • CT2 digital cordless telephone • Digital cellular 20 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 6 V • Operating temperature Topr –20 to +70 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 530∗ mW ∗When mounted on a 50 × 50 × 1.6 mm copperfoiled glass epoxy board Recommended Operating Conditions • Supply voltage VCC 2.7±5.0 Structure Bipolar silicon monolithic IC V GND NC GND Ib BIAS I BIAS GND Ib I P/S VCC Block Diagram and Pin Configuration 20 19 18 17 16 15 14 13 12 11 REGULATOR LPF ADDER -AMP F/F MIXER 1 2 3 4 5 6 7 8 9 10 LO IN LO b GND Qb BIAS Q BIAS GND Qb Q GND IF OUT AMP LPF Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E93517A5Y-TE CXA1852N Pin Description Pin No. 1 Symbol LOCAL IN Typical pin voltage (V) Equivalent circuit Description 0 1 2 LOCAL IN 3 GND 4 Q-BIAS 2 Local input pin. The internal resistor provides 50 Ω matching. Bias pin for the local input amplifier. Ground this pin via a capacitor. ∗2.0 0 ∗0.175 Local leak level adjustment pins. Normally ground these pins via 1 kΩ resistors. 5 Q-BIAS ∗0.175 5 6 7 GND Q-INPU 4 0 Q signal input pin. The input impedance is 500 kΩ or more. (Only DC signals can be normally input at the VCC/2 DC Bias.) Q signal input pin. The input impedance is 500kΩ or more. (Signals of up to 1 Vp-p can be input at the VCC/2 DC Bias.) ∗1.85 V to 0.85 V 7 8 Q-INPUT 9 GND 10 IF OUTPUT ∗1.85 V to 8 0.85 V 0 ∗1.4 10 —2— IF output pin. (An output impedance of 50 Ω is provided by the emitter follower.) CXA1852N Pin No. Symbol 11 VCC 12 POWER SAVE Typical pin voltage (V) Equivalent circuit Description 5.5 to 2.7 Power supply pin. Power saving control pin. OFF when VP/S≤1.0 V; ON when VP/S≥1.8 V 0 to 5.5 12 I signal input pin. The input impedance is 500 kΩ or more. (Signals of up to 1 Vp-p can be input at the VCC/2 DC Bias.) I signal input pin. The input impedance is 500 kΩ or more (Only DC signals can be normally input at the VCC/2 DC Bias.) ∗0.85 13 I-INPUT to 1.85 13 ∗0.85 14 I-INPUT 15 GND 16 I-BIAS 14 to 1.85 0 ∗0.175 Local leak level adjustment pin. Normally ground this pin via a 1 kΩ resistor. 17 I-BIAS ∗0.175 16 18 GND 0 19 N.C — 20 GND 0 17 —3— CXA1852N Electrical Characteristics Item Current consumption Standby current consumption IF output power Lo carrier leak Lo leak level Image rejection (side-band leak) I/Q input impedance Power saving response time Rise Fall Power saving control voltage Lo input level (Ta=25 °C, VCC=2.7 V, ZL=ZS=50 Ω)∗ Min. Typ. Max. Unit Symbol Conditions 10 15.0 22 mA ICC For no signal input 330 480 µA ICC (PS) PS –15 –11 –7.0 dBm Pout 50 Ω load, f=fLO/2+fI/Q dBc ISO (Lo) fI/Q=36 kHz, 1 Vp-p, fout=fLO/2 26 35.0 –49.0 –37 dBm PLO I/Q=VCC/2, fout=fLO/2 28.5 37.5 dBc ImR fout=fLO/2-fI/Q 500 kΩ ZI/Q 1.0 5.0 µs TP/S (RISE) 1.0 3.0 µs TP/S (DOWN) 1.8 5.5 V VP/S (ON) 1.0 V VP/S (OFF) –17 –7 dBm Loin Design Reference Values Item I/Q third-order intermodulation distortion Lo input VSWR IF output VSWR ∗ fLO=300.1 MHz Pin=–10 dBm (Ta=25 °C, VCC=2.7 V, ZL=ZS=50 Ω)∗ Conditions Typ. Unit Symbol IM3I/Q fout=fLO/2-3fI/Qf fI/Q=36 kHz 1 Vp-p DC=VCC/2 —4— 37.3 dBc 1.1 1.2 X:1 X:1 CXA1852N 19 18 I signal 0.033µ 1kΩ 16 15 14 13 12 11 REGULATOR LPF ADDER -AMP F/F MIXER AMP LPF Signal Lo I signal Q signal VCC=VP/S VI=VIb=VQ=VQb Frequency 300.1 MHz 36 kHz 35 kHz Input level –10 dBm 1 Vp-p 1 Vp-p Q signal 10 IF OUT 9 GND 8 Q Qb 7 0.033µ GND 6 1kΩ 30p 5 1kΩ Q BIAS GND Qb BIAS 4 50Ω LO SG 3 LO b 1000p 2 LO IN 1 1000p Remarks I/O phase difference = 90 °C DC for measuring the local leak 2.7 to 5.5 V 0.5 × VCC —5— 5µ VCC P/S I Ib GND 1kΩ I BIAS 17 0.01µ 2000p 20 Ib BIAS GND NC GND 1/2VCC Electrical Characteristics Test Circuit —6— LNA TX GCA SW 1 to 10mW 864 to 868.2MHz RX F/F ×5 PLL RSSI FM DEMOD Q I CXA 1744R (IF A MP) 300.1MHz 27.87MHz 139.35MHz 10.7MHz CXA 1852N (QUA DRA TURE MODULA TOR) 150.05MHz CXA 1851N (UP/DOWN CONV ERTER) ∑ 1014 to 1018.2MHz PLL 150.05MHz Digital cordless telephone chip set (CXA1744R/CXA1851N/CXA1852N) Block Diagram FREE CH DETECTION RSSI BIT STREAM CXA1852N CXA1852N Modulation spectrum (VCC=2.7V, S.P.A. measurement) -5 PI/Q PIm PLO - 45 LoL ImR - 25 I/Q 3rd order Pout - 65 - 85 - 105 fLO vs. Pout, PLO, PIm, PI/Q characteristics (VCC=2.7V) 0 AA Pout PLO PIm PI/Q - 20 AAAA AAAAAA AA - 30 - 40 - 50 - 60 - 70 - 80 10 50 100 fLO-Input frequency (MHz) A Pout PLO PIm PI/Q - 10 - 20 Output level (dBm) - 10 Output level (dBm) fLO vs. Pout , PLO ,PIm , PI/Q characteristics (VCC=5.5V) 0 - 30 - 40 - 50 - 60 - 70 - 80 10 500 AAAAA AAAAA AAAAA AA VCC vs. ICC characteristics 50 100 fLO-Input frequency (MHz) VCC vs. Pout, PIm, PI/Q characteristics No signal input LO: fLO=300.1MHz Pin=-10dBm Ta=80°C Ta=25°C Ta=-30°C P/S=VCC 40 Pout PIm PI/Q 3rd-order distortion 0 - 10 30 Output level (dBm) ICC-Current consumption (mA) 500 20 10 AAAAAAAA AAAAAAAA AAAAAAAA - 30 - 40 - 50 - 60 Recommended operating range 0 2.0 - 20 3.0 5.0 4.0 VCC-Supply voltage (V) - 70 - 80 2.7 6.0 —7— 3 3.5 4 4.5 VCC-Supply voltage (V) 5 5.5 CXA1852N Ta vs. Pout, PLO, PIm, PI/Q characteristics (VCC=2.7V) AA 0 - 10 Pout PLO PIm PI/Q 3rd-order distortion 30 Output level (dBm) - 20 AAAAAAAA AAAAAAAA - 30 - 40 - 50 PLO - 60 ICC-Current consumption (mA) fLO=300.1MHz - 10dBm VP/S vs. ICC characteristics I=Ib=Q=Qb=GND VCC=5.5V 20 VCC=2.7V 10 250µ 200µ 100µ 50µ - 70 - 80 - 30 - 20 - 10 0 4 1 1.2 1.41.6 2 3 P/S pin potential (V) 10 20 30 40 50 60 70 80 Ta (°C) —8— 5 6 CXA1852N Notes on Operation (1) Electrostatic sensitive diveces because of the high-frequency process . (2) Earth pattern should be as wide as possible, and do not increase ground impedance to prevent from the parasitic oscillation. (3) Wire the GND pin as short as possible. (4) Connect a by-pass capacitor to the VCC pin. —9— CXA1852N Unit : mm 20PIN SSOP (PLASTIC) 0.65 A 10 + 0.10 0.22 – 0.05 0.10 M 0.1 ± 0.1 0.5 ± 0.2 1 6.4 ± 0.2 4.4 ± 0.1 11 1.8 MAX 20 + 0.10 0.15 – 0.05 1.0 ± 0.1 7.0 MAX 1.5 ± 0.1 Package Outline 0° to 10° 0.575 MAX 0.15 DETAIL A PACKAGE STRUCTURE MOLDING COMPOUND EPOXY / PHENOL RESIN SOLDER PLATING SONY CODE SSOP-20P-L072 LEAD TREATMENT EIAJ CODE SSOP020-P-0225-BN LEAD MATERIAL COPPER ALLOY PACKAGE WEIGHT 0.1g JEDEC CODE —10—