CXA1946CR Electronic Volume For the availability of this product, please contact the sales office. Description The CXA1946CR is a serial control electronic volume IC designed for use in audio systems. 48 pin LQFP (Plastic) Features • Loudness • Volume control (0dB to –87dB in 1dB step, –∞dB) • Balance • Tone control (15 steps, 2 bands, –16dB to +16dB) • Fader (2dB-step to –20dB, –25dB, –35dB, –45dB, –60dB, –∞dB) • Input selector (4 channels) • Gain can be set for each input channel (common for channels 3 and 4) • Serial data control (DATA, CLK, CE) • Single 8V power supply • Zero-cross detection circuit (with timer) • Power-off mute • Volume control and tone control input/output pins are separate. Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation VCC Topr Tstg PD Operating Conditions Supply voltage VCC LQFP 13 –40 to +85 –65 to +150 180 6 to 12 V °C °C mW (Ta = 85°C) V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97516A7Y CXA1946CR GAIN134 LDLC1 LDHC1 INAO1 VRIN1 VOUT1 TIN1 TCHC1 TCLC11 TCLC12 TCO1 FDIN1 Block Diagram and Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 GAIN12 37 24 FNTO1 LOUD GAIN11 38 8dB STEP VOLUME 1dB STEP VOLUME IN14 39 FADER TONE 23 REO1 22 CE VCTBUFF INPUT SW VCTBUFF IN13 40 IN12 41 21 CLK VCTBUFF 20 DGND LATCH LATCH CONTROL IN11 42 100k 19 GND 100k 18 VCC ZCDET IN21 43 INPUT SW SHIFT REGISTER IN22 44 IN23 45 17 VCT 16 DATA VCTBUFF VCTBUFF IN24 46 15 TIMER VCTBUFF GAIN21 47 LOUD VOLUME 1dB STEP VOLUME 8dB STEP TONE FADER 14 REO2 13 FNTO2 LDLC2 LDHC2 INAO2 VRIN2 VOUT2 –2– 7 8 9 10 11 12 FDIN2 6 TCO2 5 TCLC22 4 TCLC21 3 TCHC2 2 TIN2 1 GAIN234 GAIN22 48 CXA1946CR Pin Description Pin No. Symbol I/O resistance Pin voltage Description Equivalent circuit VCC 1 36 GAIN234 GAIN134 ~ –∞ VCT 1 Sets gain for IN3 and IN4. 36 GND VCC 2 35 LDLC2 LDLC1 6.18kΩ VCT Sets loudness low cut-off frequency. 2 35 GND VCC 3 34 LDHC2 LDHC1 8.92kΩ VCT Sets loudness high cut-off frequency. 3 34 GND VCC 4 33 INAO2 INAO1 — VCT 4 Input selector output 33 GND –3– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Description Equivalent circuit VCC 5 5 32 VRIN2 VRIN1 9.5kΩ VCT 32 Volume input GND VCC 6 31 VOUT2 VOUT1 — VCT Volume output 6 31 GND VCC 7 30 TIN2 TIN1 19kΩ VCT 7 Tone input 30 GND VCC 8 29 TCHC2 TCHC1 5kΩ VCT 8 Sets tone high frequency. 29 GND –4– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Description Equivalent circuit VCC 9 28 TCLC21 TCLC11 8kΩ VCT Sets tone low frequency. 9 28 GND VCC 10 27 TCLC22 TCLC12 8kΩ VCT Sets tone low frequency. 10 27 GND VCC 11 26 TCO2 TCO1 — VCT 11 Tone control output 26 GND VCC 12 25 FDIN2 FDIN1 24kΩ VCT 12 Fader input 25 GND –5– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Description Equivalent circuit VCC 13 24 FNTO2 FNTO1 — VCT 13 Front output 24 GND VCC 14 23 REO2 REO1 — VCT 14 Rear output 23 GND VCC 15 TIMER — — 15 Sets timer. GND VCC 16 DATA ~ –∞ — Serial data input 16 GND –6– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Description Equivalent circuit 17 VCT — VCT Center electric potential 18 VCC VCC + power supply 19 GND GND GND 20 DGND — Digital GND VCC 21 CLK ~ –∞ — Serial clock input 21 GND VCC 22 CE ~ –∞ — Latch enable input 22 GND VCC 37 48 GAIN12 GAIN22 ~ –∞ VCT 37 Sets gain for IN2. 48 GND –7– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Description Equivalent circuit VCC 38 47 GAIN11 GAIN21 ~ –∞ 38 Sets gain for IN1. 47 GND 39 40 41 42 43 44 45 46 IN14 IN13 IN12 IN11 IN21 IN22 IN23 IN24 VCC 50kΩ VCT 39 43 Signal input 40 44 41 45 42 46 GND –8– CXA1946CR Data Format (a) Data allocation FAST BIT LAST BIT D1 D2 NOP D3 D4 ISW D5 LOUD D6 D7 D8 D9 VRC1 D10 D11 D12 VRF1 D13 D14 D15 D16 VRC2 D17 D18 D19 VRF2 D20 D21 D22 D23 TONE BASS D24 D25 D26 D27 TONE TREBLE D28 D29 D30 D31 FADER D32 FADER SELECT MSB LSB –9– CXA1946CR (b) Setting table • NOP Setting value D1 D2 — 0 0 Setting value D3 D4 IN14/IN24 IN13/IN23 IN12/IN22 IN11/IN21 1 1 0 0 1 0 1 0 • ISW • LOUD Setting value ON OFF D5 1 0 • VRC1/VRC2 Setting value 0 –8 –16 –24 –32 –40 –48 –56 –64 –72 –80 –∞ –∞ D6/D13 D7/D14 D8/D15 D9/D16 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 D10/D17 D11/D18 D12/D19 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 • VRF1/VRF2 Setting value 0 –1 –2 –3 –4 –5 –6 –7 – 10 – CXA1946CR • TONE BASS/TREBLE Setting value D20/D24 D21/D25 D22/D26 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 D28 D29 D30 D31 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 14 12 10 8 6 4 2 0 • BOOST/CUT Setting value D23/D27 1 0 BOOST CUT • FADER Setting value –∞ –60 –45 –35 –25 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 • FADER SELECT Setting value D32 Attenuation of front signal Attenuation of rear signal 1 0 • RESET Reset is performed automatically when power is first supplied to the IC; there is no reset pin. The following table shows the respective statuses of various settings after a reset has been performed. However, from the time when power is first supplied until the first data transfer, keep CE high by pulling it up to Vcc, etc. MODE INPUT VRC1 VRF1 VRC2 VRF2 LOUD TONE BASS TONE TREBLE FADER Setting value 1 –∞ –7dB –∞ –7dB OFF 0dB 0dB 0dB, REAR – 11 – CXA1946CR Electrical Characteristics Item (Unless otherwise specified, Vcc = 8V, Ta = 25°C) Symbol Measurement conditions Min. Typ. Max. Unit 20 25 mA Current consumption ICC No signal — Total harmonic distortion THD 1kHz, 5dBm output — Output noise voltage Vn input shorted, A weight — 7 10 µVrms Maximum output voltage Vom 1kHz 8 — — dBm Separation CS 1kHz 72 90 — dB Volume maximum attenuation ATTm 1kHz 85 90 — dB Low Glb 100Hz, VRC = –16dB 7 8 9 dB High Glh 10kHz, VRC = –16dB 5 6 7 dB Loudness 0.005 0.01 % Bass max. boost gain Gbb 14 16 18 dB Bass max. cut gain Gbc 14 16 18 dB Treble max. boost gain Gtb 14 16 18 dB Treble max. cut gain Gtc 14 16 18 dB 0 — 1.5 V 3 — 6 V 1 — VCC–1 V Input voltage Input voltage range Low Vsl High Vsh Vin DATA, CLK, CE IN11 to 14, IN21 to 24, VRIN1, VRIN2, TIN1, TIN2, FDIN1, FDIN2 – 12 – CXA1946CR Electrical Characteristics Measurement Circuit 0.39µ 10µ 26 B S5-1 VCT-50mV S1 1k 1k 1k 220p FDIN1 TCLC12 ON 25 TCO1 27 OP AMP OFF V7 AC A 28 29 TCHC1 30 TIN1 31 B 10µ TCLC11 A S3 VOUT1 32 33 34 LDLC1 GAIN134 37 GAIN12 35 VRIN1 36 B A S2 INAO1 10k 0.0022µ 0.047µ 10k LDHC1 10k 0.0027µ V6 AC 10µ V5 AC FNTO1 24 10k REO1 23 38 GAIN11 VCC 3 to 6V VCC 18 VCT 17 OF S6 F ON 1k B 0.01µ TIMER 15 S4 10k INAO2 VRIN2 VOUT2 TIN2 TCHC2 TCLC21 TCLC22 TCO2 FDIN2 FNTO2 13 1 2 3 4 5 6 7 8 9 10 11 12 10k 10µ – 13 – 0.39µ 10µ 0.0027µ S5-2 A B V8 10µ AC A 10k REO2 14 47 GAIN21 48 GAIN22 V1 DATA 16 0.0022µ V24 AC GND 19 LDHC2 V23 AC DGND 20 LDLC2 V22 AC V2 1k 0.047µ V21 AC 1k CLK 21 GAIN234 V11 AC V3 CE 22 10k V12 AC 10k V13 AC 10k B S14 A 39 IN14 B S1310k 40 IN13 A B S1210k 41 IN12 A B S1110k A 42 IN11 B S2110k A 43 IN21 B S2210k A 44 IN22 B S2310k A 45 IN23 B S2410k A 46 IN24 10k 10k V14 AC VEE 3 to 6V CXA1946CR Application Circuit 1 0.047µ 0.0027µ 0.0022µ 0.39µ 35 34 33 32 31 30 29 28 27 26 25 LDLC1 LDHC1 INAO1 VRIN1 VOUT1 TIN1 TCHC1 TCLC11 TCLC12 TCO1 FDIN1 GAIN134 37 GAIN12 10µ 10µ 10µ 36 FNTO1 24 REO1 23 38 GAIN11 39 IN14 CE 22 40 IN13 CLK 21 41 IN12 DGND 20 42 IN11 GND 19 43 IN21 VCC 18 44 IN22 VCT 17 45 IN23 DATA 16 46 IN24 TIMER 15 33µ 10µ 0.01µ 47 GAIN21 TCLC21 TCLC22 TCO2 5 6 7 8 9 10 11 10µ 0.047µ FDIN2 TCHC2 4 TIN2 3 VOUT2 INAO2 2 FNTO2 VRIN2 LDHC2 1 LDLC2 GAIN234 48 GAIN22 REO2 14 13 12 10µ 0.0022µ 0.0027µ 10µ 0.39µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – CXA1946CR 0.0027µ 34 33 32 31 30 29 28 10µ 27 LDHC1 INAO1 VRIN1 VOUT1 TIN1 TCHC1 TCLC11 TCLC12 GAIN134 37 GAIN12 10µ 26 25 FDIN1 35 10µ 36 0.39µ LDLC1 0.0022µ TCO1 0.047µ Application Circuit 2 FNTO1 24 REO1 23 38 GAIN11 39 IN14 CE 22 40 IN13 CLK 21 41 IN12 DGND 20 42 IN11 GND 19 43 IN21 VCC 18 44 IN22 VCT 17 45 IN23 DATA 16 46 IN24 TIMER 15 33µ 10µ 0.01µ 47 GAIN21 LDHC2 INAO2 VRIN2 VOUT2 TIN2 TCHC2 TCLC21 TCLC22 TCO2 FDIN2 2 3 4 5 6 7 8 9 10 11 12 0.0027µ 0.047µ 1 FNTO2 LDLC2 GAIN234 48 GAIN22 REO2 14 10µ 0.0022µ 10µ 0.39µ 13 10µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 15 – CXA1946CR Tone control characteristics 20 16 +16dB 12 Response [dB] 8 4 0 0dB –4 –8 –12 –16 –20 10 –16dB 100 1k 10k 100k Frequency [Hz] Loudness characteristics 0 VRC = 0dB –5 Response [dB] VRC = –8dB –10 VRC = –16dB –15 VRC = –24dB –20 –25 10 100 1k Frequency [Hz] – 16 – 10k 100k CXA1946CR Description of Operation The CXA1946CR is a serial control electronic volume IC designed for use in audio systems. The internal circuit of the IC consists of the following blocks: 1. 2. 3. 4. 5. 6. 7. 8. 9. Input selector Volume Loudness Tone control Fader VCT buffer Serial data I/O Zero-cross detector (with timer) Power-off mute The operation of each block and notes on their use are described below. Note that when the circuits for channels 1 and 2 are identical, the suffix “X” is added to pin names and device names in order to distinguish between the two channels. 1. Input selector There are two channels (stereo), each with four systems of input pins; the input selector selects one of those input systems. The gain between the input pins and the output pin of the input selector can be set independently for each input system, except the gain for inputs 3 and 4 is common. Determine the gain for each system through the settings of the feedback circuit constants as shown in Figs. 1 and 2. When each input gain is set to × 1, short INAOX and GAIN × 1,GAIN × 2,GAIN × 34. The input impedance is 50kΩ (typ.) for each input. The output impedance for INAO1 and INAO2 is low impedance (roughly 0Ω). The gain is not affected by the load impedance. VCT GAINX2 GAINX1 GAINX34 INX4 50k INX3 50k INX2 50k INX1 50k Fig. 1. Input Selector (1) – 17 – INAOX CXA1946CR VCT GAINX2 GAINX1 GAINX34 INAOX INX4 50k INX3 50k INX2 50k INX1 50k Fig. 2. Input Selector (2) 2. Volume The volume circuit consists of two sections, an 8dB/step section and a 1dB/step section, as shown in Fig. 3. This circuit also serves as a balance control because the volume for channel 1 and channel 2 can be set independently. To mute the output signal, send –∞dB data. The input impedance is 9.5kΩ (typ.) for VRIN1 and VRIN2. The output impedance for VOUT1 and VOUT2 is low impedance (roughly 0Ω). The volume step width and gain are not affected by the load impedance. 3. Loudness The configuration of the loudness circuit is shown in Fig. 3. CLDHCX and CLDLCX are connected externally, and the loudness frequency characteristics are determined by these constants. The relationships between CLDHCX/CLDLCX and the frequency characteristics are as follows: 1/fL = 2πCLDLCXR1 1/fH = 2πCLDHCXR2 The loudness characteristics are not affected by the load impedance of VOUT1 and VOUT2. Loudness is turned on and off by serial data bit D5. fH VRINX (input impedance 9.5kΩ) 20k CLDHCX 0.0022µ 20k R2 8.92k LDHCX 25.7k 4.98k Total 40k OFF fL Loudness frequency characteristics VOUTX ON LOUD R1 6.18k CLDLCX 0.047µ LDLCX Loudness Volume Fig. 3. Volume and Loudness – 18 – CXA1946CR 4. Tone control The configuration of the tone control circuit is shown in Fig. 4. CTCLCX2 and CTCHCX are connected externally, and the tone control frequency characteristics can be changed by changing these constants. The relationships between CTCLCX2/CTCHCX and the frequency characteristics are as follows: 1/fL = 2πCTCLCX2 (R3//R4) 1/fH = 2πCTCHCXR5 The maximum bass boost and cut can be made smaller than in the Application Circuit by connecting an external resistance to the TCLCX1 pin in series, or else connecting an external resistance to CTCLCX2 in parallel. (See Fig. 5.) Furthermore, the maximum treble boost and cut can be made smaller than in the Application Circuit by connecting an external resistance to CTCHCX in series. (See Fig. 6.) However, when these methods are used, variations in the absolute value of the CXA1946C internal resistance (±20% max.) and in the external resistance will cause variations in the tone control characteristics. Set these constants after studying all considerations carefully. Note that when the method illustrated in the Application Circuit is used, variations in the internal resistance of the CXA1946C have no effect on the tone control characteristics. The input impedance is 19kΩ (typ.) for TIN1 and TIN2. The output impedance for TCO1 and TCO2 is low impedance (roughly 0Ω). The tone step width and gain are not affected by the load impedance. CTCLCX2 0.39µ TCLCX1 TCLCX2 12k TCOX TINX input impedance 19kΩ R4 8k BASS ON 14.1k CUT 14.1k 12k OFF R3 8k ON OFF 10k 10k 10k fL 14.1k BOOST ON CUT OFF fH 10k R5 5k Tone control frequency characteristics ON TREBLE OFF TCHCX CTCHCX 0.0027µ Fig. 4. Tone Control – 19 – 14.1k BOOST CXA1946CR RexB CTCLCX2 CTCLCX2 RexA TCLCX1 TINX TCLCX1 TCLCX2 R4 8k TCLCX2 R4 8k R3 8k R3 8k (A) (B) Fig. 5. Method for Reducing Bass Boost/Cut 10k 10k 10k 10k R3 5k TCHCX RexC CTCHCX Fig. 6. Method for Reducing Treble Boost/Cut 5. Fader The configuration of the fader circuit is shown in Fig. 7. The fader operates by specifying the amount of attenuation for either the front or rear output signal and by specifying which output signal (front or rear) is to be attenuated. The input impedance is 24kΩ (typ.) for FDIN1 and FDIN2. The output impedance for FNTO1, FNTO2, REO1, and REO2 is low impedance (roughly 0Ω). The gain and fader step width are not affected by the load impedance. FDINX (input impedance 24kΩ) Center FNTOX ATT Center ATT Fig. 7. Fader – 20 – REOX CXA1946CR 6. VCT buffer The internal circuit for the VCT pin is shown in Fig. 8. This circuit generates the electric potential for the center between Vcc and GND (Vcc/2). The IC internal operation reference potential is equal to the output potential of VCT buffer. The impedance for the VCT pin (Pin 17) is high since it is connected to a bypass capacitor. Add an external buffer when using the electric potential of the VCT pin as the external reference potential for the CXA1946. VCC 100k VCT 10µ 100k Fig. 8. VCT Buffer 7. Serial data I/O The serial data has a 32-bit structure as indicated in the specifications. Data input is conducted using three inputs: DATA, CLK, and CE. DATA is shifted in the CXA1946C internal shift register at the rising edge of CLK. The data in the shift register is latched at the falling edge of CE. Refer to this specification for details on the timing. The CXA1946C does not have a reset (initialize) pin. The internal shift register and latch are reset automatically when power is first supplied to the IC. To execute a reset at other times, send the data (statuses after reset ) shown in the item "RESET" of this specification to the CXA1946C. 8. Zero-cross detector (with timer) Using the zero-cross detector, the internal latch data is overwritten the first time the input signal becomes roughly 0 after serial data is sent (after CE goes low). This operation reduces noise when overwriting data. Although there are usually no problems when a normal audio signal is input, in rare cases there may be nothing except a large-amplitude input signal of the high band, causing the slew rate to become abnormally high; the zero-cross detection signal is not output in such a case because the zero-cross detector response speed is too slow. Another rare situation would be that the zero-cross detection signal is output very infrequently because the input signal frequency is extremely low. In these types of instances, it is conceivable that the internal latch data will not be overwritten after data is sent, or that it will take much time until the data is overwritten. Therefore, to an external observer it will appear that the data is not being overwritten regardless of the fact that data is being sent. As a countermeasure, the IC is designed to permit the internal latch data to be forcibly overwritten if the zero-cross detection signal is not output within a certain waiting period after the data is sent (after CE goes low). This function is called the “timer.” If the zero-cross detection signal is output within a certain waiting period, the internal latch data is overwritten in synchronization with the zero-cross of the input signal. The waiting period mentioned above can be changed according to the value of the external capacitor connected to the TIMER pin. When the value of the capacitor is 0.01µF, the waiting period is approximately 500µs. 9. Power-off mute When Vcc goes below 5V, the output stage bias of the fader output pins FNTO1, FNTO2, REO1, and REO2 is turned off and the pins go to high impedance. This operation prevents popping noises caused by the output pin potential deviating from Vcc/2 when the power is turned off. – 21 – CXA1946CR Connections and Characteristics of Each Block In the Application Circuit, the signal path goes from the input selector to the volume (+loudness) to the tone control to the fader. The sequence of the blocks in the signal path can be changed because the I/O pins for each block are independent of each other. For example, it is possible to switch the sequence of the volume circuit and the tone control so that the signal path goes from the input selector to the tone control to the volume (+loudness) to the fader. When this connection method is used, the noise voltage in the fader output can be reduced in actual use because the noise and signal up to the tone control are attenuated by the volume. However, because the maximum output amplitude of the tone control circuit is limited by the supply voltage, care should be given to the setting of the input signal level. Although blocks in the Application Circuit are linked either by coupling capacitors or by direct connection, it is also possible to insert external circuits between blocks. In this case, the gain will change according to the input impedance of the following block and the impedance of the external circuit. In addition, the input impedance of each block can vary by ±20% due to the characteristics of the IC. Consequently, the overall gain also varies. Give careful consideration to the effects of this variation when setting the constants. The step widths (control characteristics) of the volume, tone control, and fader are not affected. Timing Chart CE DATA D1 D2 D30 D31 D32 Invalid CLK t1 tck tsu th t2 tL tL ≥ tT + 0.5µs (tT is the maximum value for the timer operation time) t1 ≥ 0.5µs t2 ≥ 0.5µs tck ≥ 1.0µs tsu ≥ 0.5µs th ≥ 0.5µs CE tce tce ≥ 4.0µs Timer Waiting Period Setting Chart (Vcc = 6 to 12V, operating temperature = –35°C to 85°C) TIMER pin capacitance C Waiting peroid Min. Typ. Max. C = 100pF 3µs 5µs 9µs C = 0.001µF 30µs 50µs 90µs C = 0.01µF 300µs 500µs 900µs C = 0.1µF 3ms 5ms 9ms C = 1µF 30ms 50ms 90ms C = 10µF 300ms 500ms 900ms – 22 – CXA1946CR Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 36 25 A 13 48 (0.22) 0.5 ± 0.2 (8.0) 24 37 12 1 + 0.05 0.127 – 0.02 0.5 ± 0.08 + 0.2 1.5 – 0.1 + 0.08 0.18 – 0.03 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN SOLDER PLATING SONY CODE LQFP-48P-L01 LEAD TREATMENT EIAJ CODE ∗QFP048-P-0707-A LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE – 23 –