SONY CXA2000Q

CXA2000Q
Y/C/RGB/D for PAL/NTSC Color TVs
For the availability of this product, please contact the sales office.
Description
The CXA2000Q is a bipolar IC which integrates the
luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC/PAL
system color TVs onto a single chip. This IC includes
deflection processing functions for wide-screen TVs,
and is also equipped with a SECAM decoder
interface, making it possible to construct a TV
system that supports multiple color systems.
64 pin QFP (Plastic)
Features
• I2C bus compatible
• Compatible with both PAL and NTSC systems
(also compatible with SECAM if a SECAM decoder is connected)
• Built-in deflection compensation circuit capable of supporting various wide modes
• Countdown system eliminates need for H and V oscillator frequency adjustment
• Automatic identification of 50/60Hz vertical frequency (forced control possible)
• Non-interlace display support (even/odd selectable)
• Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible)
• Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible)
• Non-adjusting Y/C block filter
• One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both
analog and digital inputs)
• Built-in AKB circuit
• Support for forcing YS1 off
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C, SGND, DGND = 0V)
• Supply voltage
SVCC1, 2, DVCC1, 2
–0.3 to 12
V
• Operating temperature
Topr
–20 to +65
°C
• Storage temperature
Tstg
–65 to +150
°C
• Allowable power dissipation
PD
1.7
W
(when mounted on 50mm × 50mm board)
• Voltages at each pin
–0.3 to SVCC1, SVCC2,
DVCC1, DVCC2 + 0.3 V
Operating Conditions
Supply voltage
SVCC1, 2
DVCC1, 2
9.0 ± 0.5
9.0 ± 0.5
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96103-ST
11 12 13 14
8
7
6
5
4
3
1
64
COL
CLP
61
fsc B-Y
COLOR
& AXIS
62
XTAL
fsc R-Y
60
VCO
DEM
AXIS
fsc
ID
YS
SW
43
IREF
HUE
HUE
PAL
ID
Y/C
MIX
YS1 OFF
INTER
-LACE
IREF
DEM
DIG
OSD
MIX
DCOL
γ
39
L2FIL
ABL
BRT
EHT H, V
HV
COMP
GB
DRV
BRT GB DRV
35 SAWOSC
34 VAGCSH
30 VTIM
10 SCPOUT
37 HD OUT
42 DGND
44 DVCC2
36 DVCC1
BLK
27 IKIN
26 BOUT
24 GOUT
22 ROUT
33 E-WOUT
AKB OFF
21 23 25
AKB
CUT
OFF
WIDE
Parabola
Gen.
GB CUT
VD+OUT
32 /VPROT
WIDE
Sawtooth
VD–OUT
Gen.
31 /VPROT
VLIN, SCORR
VPOSI, VOFF,
VSIZE
SCP BGR/BGF
H.DRIVE
28
PIC
PIC
D-COL γ
C MODE
Sand
Castle
PHASE
SHIFT
H POSI
AFC
Count Down
525/625
1/32
2fH
PHASE
DET
38
29
CLP
YS/YM
SW
INTERLACE
GATE
PHASE
DET.
32fH
VCO
41
40
15 16 17 18 19
GATE
50/60 ID
APCFIL
SGND2 9
PAL/
NTSC
KILLER
DET
D PIC
X358
SGND1 2
APC
COLOR SW
TOT
DC
TRAN
CLP
V FREQ
X443
SVCC2 20
ACC
DET
TOT
PRE/OVER
SHARP
NESS
DC
TRAN AGING D PIC
FSCOUT
SVCC1 59
TRAP F0
TRAP
DL
TRAP OFF
SUB COLOR
ACC
SUB
CONT
SUB CONT
DLSHARP
V SYNC
SEP
H SYNC
SEP
47
46
45
SECAMREF
CIN 57
VIDEO
SW
CV/YC
VM
–(B-Y) OUT
–(R-Y) OUT
YIN 55
S
SEP
1Vp-p
STATUS
SDA
VM OFF
BLHOLD
52
VSFIL
YRET
YOUT
CVIN 53
EXT SYNC IN
EXT
SYNC
SYNCOUT
SCL
6dB
DCTRAN
54
YM
49
YS2
50
R2IN
1Vp-p
–(R-Y) IN
YS1
AFCFIL
B2IN
G2IN
VSIN
–(B-Y) IN
R1IN
CERA
ABLFIL
HSIN
B1IN
G1IN
AFCPIN/
HOFF
ABLIN/
VCOMP
51
48
2Vp-p
RSH
56
BSH
–2–
GSH
Block Diagram
CXA2000Q
CXA2000Q
E-WOUT
VAGCSH
SAWOSC
DVCC1
HDOUT
AFCPIN/HOFF
L2FIL
AFCFIL
CERA
DGND
IREF
DVCC2
VSFIL
VSIN
HSIN
SYNCOUT
VM
SCL
SDA
Pin Configuration
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
BLHOLD 52
32 VD+OUT/VPROT
CVIN 53
31 VD–OUT/VPROT
30 VTIM
DCTRAN 54
29 ABLFIL
YIN 55
28 ABLIN/VCOMP
EXT SYNC IN 56
27 IKIN
CIN 57
26 BOUT
TEST 58
25 BSH
SVCC1 59
APCFIL 60
24 GOUT
X443 61
23 GSH
X358 62
22 ROUT
21 RSH
NC 63
20 SVCC2
–3–
–(R-Y) OUT
–(B-Y) OUT
YOUT
YRET
–(R-Y) IN
–(B-Y) IN
SGND2
B2IN
SGND1
10 11 12 13 14 15 16 17 18 19
G2IN
9
R2IN
8
YM
7
YS2
6
B1IN
5
G1IN
4
R1IN
3
YS1
2
SCPOUT
1
SECAMREF
FSCOUT 64
CXA2000Q
Pin Description
Pin
No.
Symbol
Equivalent circuit
6k
1
SECAMREF
Description
20p
1
7.2V
SECAM decoder interface. This pin
serves as both a 4.43MHz output and as
a SECAM identification input/output pin.
250µA
2
SGND1
GND for Y/C block.
—
200µA
3
4
–(R-Y) OUT
–(B-Y) OUT
3
4
Color difference signal outputs. Go to
high impedance when the SECAM
system is detected.
Standard output levels for 75% CB:
B-Y: 0.665Vp-p
R-Y: 0.525Vp-p
500
5
YOUT
Luminance signal output.
Black level is 3.5VDC.
Standard output level for 100 IRE input:
1Vp-p
5
30k
400µA
6
YRET
Luminance signal input.
Clamped to 4.8V at the burst timing.
Standard input level for 100 IRE input:
1Vp-p
6
1.5k
70k
7
8
–(R-Y) IN
–(B-Y) IN
7
8
1.5k
70k
9
SGND2
Color difference signal inputs.
Clamped to 5.5V at the burst timing.
Standard input levels for 75% CB:
B-Y: 1.33Vp-p
R-Y: 1.05Vp-p
GND for the RGB block.
–4–
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
1k
10
SCPOUT
Sand castle pulse output. The 0 to 5V
BGP pulse, the phase of which is
controlled through the bus, is
superimposed with the 0 to 2V H and
VBLK pulse for output.
10
10k
1k
YSSW control input.
When YS is high, the RGB1 block signal
is selected; when YS is low, the Y/C block
is selected. This function can be disabled
by the YS1OFF setting for the I2C bus.
VILMAX = 0.4V
VIHMIN = 1.0V
100µA
11
YS1
11
40k
200
12
13
14
R1IN
G1IN
B1IN
12
13
14
30k
100µA
15
YS2
15
40k
Analog R, G and B signal inputs.
Input a 0.7Vp-p (no sync, 100 IRE) signal
via a capacitor.
The signal is clamped to 5.7V at the burst
timing of the signal input to the HSIN
input pin (Pin 47).
YS/YMSW YS control input.
When YS is high, the RGB2 block signal
is selected; when YS is low, the YSSW
output signal is selected.
VILMAX = 0.4V
VIHMIN = 1.0V
100µA
16
YS/YMSW YM control input.
When YM is high, the YSSW output
signal is attenuated by 9.6dB.
VILMAX = 0.4V
VIHMIN = 1.0V
YM
16
40k
–5–
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
100µA
200
17
18
19
R2IN
G2IN
B2IN
17
18
19
30k
20
SVCC2
Power supply for RGB block.
200
21
23
25
RSH
GSH
BSH
Analog/digital (dual-purpose) RGB signal
inputs.
The input signals are input via capacitors.
When using analog input, input a 0.7Vp-p
signal (no sync, 100 IRE); when using
digital input, input a signal of at least
1.5Vp-p (Vth = 1.2V).
The display level is 67 IRE. When using
digital input, digital input is selected
regardless of the YS setting.
In addition, the VM output is turned off.
These pins are clamped to 5.7V at the
burst timing of the signal input to the
sync input pin (Pin 47).
21
23
25
Sample-and-hold for R, G and B AKB.
Connect to GND via a capacitor.
When not using AKB (manual CUTOFF
mode), R, G and B cut-off voltage can be
controlled by applying a control voltage to
each pin. The control voltage is 4.5 ± 1V.
200
22
24
26
ROUT
GOUT
BOUT
22
24
26
12k
1.1mA
1k
27
IKIN
27
50µA
–6–
R, G and B signal outputs.
2.5Vp-p is output during 100% white
input.
Input the signal converted from the CRT
beam current (cathode current Ik) to a
voltage via a capacitor. The V blanking
part is clamped to 2.7V at the V retrace
timing.
The input for this pin is the reference
pulse return, and the loop operates so
that the Rch is 1Vp-p and the G and Bch
are 0.81Vp-p. The G and Bch can be
varied by ±0.5V by the bus CUTOFF
control. When not using AKB, this pin
should be open.
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
ABL control signal input and VSAW high
voltage fluctuation compensation signal
input.
High voltage compensation has linear
control characteristics for the pin voltage
range of about 8V to 1V. The control
characteristics can be varied through
EHT-V control of the bus. ABL begins to
have effect below a threshold voltage of
about 1.2V.
ABL functions as PIC/BRT-ABL (average
value type).
1.5V
28
ABLIN/VCOMP
28
147
100k
29
ABLFIL
29
1.2k
1k
30
VTIM
30
10k
1k
700
31
VD–OUT/VPROT
30k
31
24k
400µA
Connect a capacitor to form the LPF of
the ABL control signal.
V timing pulse output.
Outputs the timing pulse from V sync
identification to the end of V blanking.
Pulses are positive polarity from 1 to 6V.
During zoom mode, the V blanking pulse
which has been expanded before and
after the V sync is superimposed and
output as the 1 to 3V pulse.
V sawtooth wave output and V protect
signal input.
When a large current (3mA) is drawn
from this pin, the RGB outputs are all
blanked and "1" is output to the status
register VNG.
700
32
VD+OUT/VPROT
30k
32
24k
400µA
–7–
Serves as both a V sawtooth wave output
with the reverse polarity of VD–OUT,
and a Vprotect signal input. The Vprotect
function can even be applied to this pin.
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
1.4k
33
E-WOUT
15k
V parabola wave output.
33
78k
800µA
34
VAGCSH
Sample-and-hold for AGC which
maintains the V sawtooth wave at a
constant amplitude.
Connect to GND via a capacitor.
34
1.2k
35
SAWOSC
Connect a capacitor to generate the V
sawtooth wave. For the capacitor, use an
MPS (metalized polyester capacitor), etc.,
with a small tan δ.
300
35
100
36
DVCC1
37
HD OUT
Power supply for the V deflection block.
H drive signal output.
This signal is output with the open
collector.
37
147
20k
38
AFCPIN/HOFF
147
10k
38
10k
68k
–8–
4.2V
H deflection pulse input for H AFC.
Input an about 5Vp-p pulse via a
capacitor. Set the pulse width to 10 to
12µs. This pin is also used as the holddown signal input for the HD output, and
if this pin is 1V or less for a 7V cycle or
longer, the hold-down function operates
and the HD output is held to 9VDC. In
addition, the RGB outputs are all blanked.
Outputs "1" to the status register XRAY.
CXA2000Q
Pin
No.
39
Symbol
Equivalent circuit
L2FIL
Description
Filter for H AFC.
Connect to GND via a capacitor.
The H phase can also be controlled from
this pin by leading current in and out of
this capacitor.
As the pin voltage rises, the picture shifts
to the left; as the pin voltage drops, the
picture shifts to the right.
39
100
40
AFCFIL
1.2k
CR connection for the AFC lag-lead filter.
40
46k
10k
41
CERA
Connect the 32 × FH VCO ceramic
oscillator.
41
400µA
42
GND for the deflection block.
DGND
43
IREF
44
DVCC2
45
VSFIL
20k
147
43
Internal reference current setting.
Connect to GND via a resistor with an
error of less than 1% (such as a metal
film resistor).
Power supply for the H deflection block.
1k
45
–9–
Filter for V sync separation.
Connect to GND via a capacitor.
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
15k
46
VSIN
4.1V
Sync signal input for V sync separation.
Input a 2Vp-p Y signal (or a 0.6Vp-p
sync signal).
3.2V
Sync signal input for H sync separation.
Input a 2Vp-p Y signal (or a 0.6Vp-p sync
signal).
147
46
20µA
14k
47
HSIN
147
47
10µA
1.2k
48
SYNCOUT
40k
147
48
240µA
500
1.2k
49
VM
30k
147
49
400µA
Sync signal output for VSIN and HSIN.
The output can be selected from the
internal sync signals (Pin 53 or Pin 55) or
the external sync signal (Pin 56) by the
I2C bus.
Output signal level: 2Vp-p
(0.6Vp-p sync only)
Input/output gain: 6dB
Outputs the differential waveform of the
VM (Velocity Modulation) Y signal.
(6.6VDC, 1.1Vp-p)
The signal advanced for 200ns from
YOUT is output. The delay time versus
YIN is determined by the DL setting of
the I2C bus. This output can be turned off
through the I2C bus.
This output can also be turned off by
YS1, YM, and YS2.
4k
I2C bus protocol SCL (Serial Clock) input.
VILMAX = 1.5V
VIHMIN = 3.5V
50
50
SCL
– 10 –
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
4k
I2C bus protocol SDA (Serial Data) I/O.
VILMAX = 1.5V
VIHMIN = 3.5V
VOLMAX = 0.4V
51
51
SDA
9µA
4.6V
20k
4k
52
BLHOLD
52
20k
1.2k
4.6V
53
CVIN
53
1µA
Capacitor connection for black peak hold
of the dynamic picture (black expansion).
Composite video signal input.
Input the 1Vp-p (100% white including
sync) CV signal via a capacitor. The
sync level of the input signal is
clamped to 3.8V.
In addition, this pin detects input video
signal HSYNC, and outputs the status
via the status register CVSYNC.
2V
54
1.2k
4k
DCTRAN
54
Connect a capacitor that determines the
DC transmission ratio to GND.
2k
4.6V
55
YIN
55
1µA
– 11 –
Y signal input.
Input a 1Vp-p (100% white including
sync) Y signal via a capacitor. The
sync level of the input signal is
clamped to 3.8V.
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
4.6V
56
EXT SYNC IN
External sync signal input.
Input a 0.3Vp-p sync signal (or a 1Vp-p
CV signal or Y signal) via a capacitor.
The sync level of the input signal is
clamped to 3.8V.
56
1µA
57
CIN
30k
57
5.2V
50k
Chroma signal input.
Input a C signal with a burst level of
300mVp-p via a capacitor. Input signal is
biased to 4.5V internally.
1k
58
TEST
Test pin.
Outputs a 0 to 3V V-SYNC SEP with
positive polarity. If not used, leave this
pin open.
58
15k
59
SVCC1
Power supply for Y/C block.
4.6V
60
CR connection for the chroma APC laglead filter.
1.2k
APCFIL
60
1.2k
4k
61
X443
Connect a 4.433619MHz crystal oscillator.
61
500
200µA
– 12 –
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
4k
62
X358
Connect a 3.579545MHz crystal oscillator.
62
500
200µA
63
Not connected.
Normally connected to GND to prevent
interference with other pins.
NC
1.2k
64
FSCOUT
Subcarrier output.
Output level: 5.2VDC, 0.4Vp-p
64
147
280µA
– 13 –
DICC
Sync block current
consumption
2
HDw
VBLKh
VBGPh
VSp-p
VSdc
SCP
BLK output pulse width
SCP
BGP output pulse width
VDRIVE output
amplitude
VDRIVE output center
potential
6
7
8
9
4
HD output pulse width
∆fHR
Horizontal sync pull-in
range
5
fHFR
Horizontal free-running
frequency
3
Sync deflection block items
SICC
Symbol
Signal block current
consumption
Item
1
No.
– 14 –
10
SCP
Measure the pulse width for the section
where the BGP output is high.
SYNCIN: composite sync
10
SCP
Measure the pulse width for the
section where the BLK output is high.
31, 32
31, 32
37
—
37
36, 44
20, 59
Measurement pins
SYNCIN: composite sync
SYNCIN: composite sync
AFC MODE = 0h
VCC = 9.0V,
Bus data = center
VCC = 9.0V,
Bus data = center
Measurement conditions
VDRIVE+
10.79ms VSdc
46: VSIN in
VSp-p
Measure the VDRIVE output Vp-p.
VBLKh
24.5
Measure the pulse width for the section
where the HDRIVE output is high.
2.9
0.9
2.5
11.6
–400
Confirm that I2C status register
HLOCK is 1 (the pull-in range
when fH is shifted from
15.734kHz).
VBGPh
15.55
30
42
Min.
HDRIVE output frequency
Measure the pin inflow current.
Measure the pin inflow current.
Measurement contents
Electrical Characteristics
Setting conditions
• Ta = 25°C, SVCC1, 2 = DVCC1, 2 = 9V, SGND1, 2 = DGND = 0V
• Measures the following after setting the I2C bus register as shown in "I2C Bus Register Initial Settings".
3.0
1.0
2.9
12.1
25.5
—
15.734
48
65
Typ.
3.1
1.1
3.3
12.6
26.5
400
15.90
65
86
Max.
V
V
µs
µs
µs
Hz
kHz
mA
mA
Unit
CXA2000Q
– 15 –
C-Trap3.58
R, G and B output
linearity
C-TRAP attenuation
13
14
(3.58MHz)
Lin
R, G and B output
amplitude
12
VRout1
VEWdc
EWDRIVE output
center potential
11
Signal block items
VEWp-p
Symbol
EWDRIVE output
amplitude
Item
10
No.
TRAPOFF = 0/1
TRAP-F0 = 7h
CVIN:
fsc, 50 IRE
CVIN:
CVIN:
100 IRE
50 IRE
0.7Vp-p
/100 IRE
SYNCIN: composite sync
Measurement conditions
22
22, 24, 26
22, 24, 26
33
33
Measurement pins
VEW dc
V1
Lin =
V1
× 100
V2 × 2
f = 3.58MHz
Input fsc to CVIN.
Ratio of the fsc component of the
Yout amplitude when CTRAP = 1
against the Yout amplitude when
CTRAP = 0.
V2
Output amplitude when a video
signal with an amplitude of
0.7Vp-p/100 IRE is input.
10.79ms
46: VSIN in
VEWp-p
Measure the EWDRIVE output
Vp-p.
Measurement contents
—
96
2.25
3.8
0.42
Min.
–30
100
2.5
3.95
0.52
Typ.
—
104
2.85
4.1
0.62
Max.
dB
%
V
V
V
Unit
CXA2000Q
Symbol
C-Trap4.43
Vvm
Vr-y
Vb-y
Vcolr-y
Vcolb-y
Item
C-TRAP attenuation
(4.43MHz)
VM output
Color difference
–(R-Y) output
Color difference
–(B-Y) output
Color gain
–(R-Y)
Color gain
–(B-Y)
No.
15
16
17
– 16 –
18
19
20
PAL input: COLOR = 1Fh
–(B-Y) IN: 665mVp-p
PAL input: COLOR = 1Fh
–(R-Y) IN: 525mVp-p
SUB-COLOR = 7h
450mVp-p
fsc + 0°, fsc + 180°
CIN
4.43MHz PAL input
burst fsc 300mVp-p
640mVp-p fsc + 90°
CVIN: 3MHz, 50 IRE
VMOFF = 0
TRAPOFF = 0/1
TRAP-F0 = 7h
CVIN:
fsc, 50 IRE
Measurement conditions
24
22
4
3
49
22
Measurement pins
BOUT
ROUT
–(B-Y)
OUT
–(R-Y)
OUT
Vvm
f = 3MHz
Vr-y
50 IRE
Vb-y
Vcolb-y
Vcolr-y
f = 4.43MHz
Input fsc to CVIN.
Ratio of the fsc component of the
Yout amplitude when CTRAP = 1
against the Yout amplitude when
CTRAP = 0.
Measurement contents
1.1
1.4
570
440
0.75
—
Min.
1.3
1.6
640
510
0.95
–30
Typ.
1.5
1.8
710
570
1.15
—
Max.
V
V
mV
mV
V
dB
Unit
CXA2000Q
∆GYM
VLR1out
VLG1out
VLB1out
R output amplitude
during linear R1 input
G output amplitude
during linear G1 input
B output amplitude
during linear B1 input
27
28
29
∆GdcolB
Dynamic color
operation B output
25
YM gain
∆GdcolR
Dynamic color
operation R output
24
26
∆fAPC
APC pull-in range
23
– 17 –
YS1: 1V
RGB1IN: 0.7Vp-p
YS1: 1V
RGB1IN: 0.7Vp-p
YS1: 1V
RGB1IN: 0.7Vp-p
D-COL = 0/1
CVIN: 100 IRE
CVIN: Burst only
KP
Killer point
22
HUE = 1Fh, SUB – HUE = 7h
Measurement conditions
φoffset
Symbol
Hue center offset
Item
21
No.
26
24
22
22, 24, 26
24
22
—
R, G, B
out
RGB1
IN
VLB1out = Vout
VLG1out = Vout
VLR1out = Vout
Output amplitude ratio when the
R, G and BOUT YM = 1 and 0
∆GdcolR =
Vp-p (DCOL = 1)
× 100
Vp-p (DCOL = 0)
Vp-p (DCOL = 1)
∆GdcolB =
× 100
Vp-p (DCOL = 0)
Vp-p
ROUT, BOUT
1.85
1.85
1.85
–10.6
102
94
–400
—
—
Min.
–8
Confirm that the burst frequency
is pulled in at 3.58MHz ±400Hz.
Measurement contents
—
Measurement pins
2.05
2.05
2.05
–9.6
104
96
2.25
2.25
2.25
–8.6
106
98
400
V
V
V
dB
%
%
Hz
dB
—
–35
—
deg
Unit
8
Max.
0
Typ.
CXA2000Q
– 18 –
VDGout
VDBout
G output amplitude
during digital G2
input
B output amplitude
during digital B2
input
IK level R
IK level G
IK level B
34
35
36
37
38
VIKB
VIKG
VIKR
VDRout
VLB2out
B output amplitude
during linear B2
input
32
R output amplitude
during digital R2
input
VLG2out
G output amplitude
during linear G2
input
31
33
VLR2out
R output amplitude
during linear R2
input
30
Symbol
Item
No.
SYNCIN: composite sync
GCUTOFF = 0h
BCUTOFF = 0h
RGB2IN: 1.5Vp-p
RGB2IN: 1.5Vp-p
RGB2IN: 1.5Vp-p
YS2: 1V
RGB2IN: 0.7Vp-p
YS2: 1V
RGB2IN: 0.7Vp-p
YS2: 1V
RGB2IN: 0.7Vp-p
Measurement conditions
27
27
27
26
24
22
26
24
22
Measurement pins
R, G, B
out
RGB2
IN
R, G, B
out
RGB2
IN
VIKG
VIKR VIKB
VDBout = Vout
VDGout = Vout
VDRout = Vout
VLB2out = Vout
VLG2out = Vout
VLR2out = Vout
Measurement contents
0.22
0.22
0.85
58
58
58
1.85
1.85
1.85
Min.
V
V
0.5
0.35
0.5
V
1.15
1.00
0.35
IRE
IRE
IRE
V
V
V
Unit
75
75
75
2.25
2.25
2.25
Max.
67
67
67
2.05
2.05
2.05
Typ.
CXA2000Q
+9V
10µ
47µ
15k
3
–(R-Y) OUT
4
0.1µ
–(B-Y) IN
0.1µ
8
9
SGND2
–(R-Y) IN –(B-Y) IN
0.1µ
7
6
5
Y OUT
–(R-Y) OUT
–(B-Y) OUT
2
1
SECAMREF
120µ
63 NC
62 X358
61 X443
60 APCFIL
59 SVCC1
58 TEST
57 CIN
56 EXT SYNC IN
55 YIN
54 DCTRAN
FSC OUT
64
FSC OUT
15p 3.58MHz 1.5k
15p 4.43MHz 470
0.47µ
470p
10µ
TEST
0.01µ
C IN
EXT SYNC IN10µ
Y IN
0.47µ
10µ
53 CVIN
SECAMREF
CV IN
SCPOUT
SCP OUT
10
R1IN
12
220
YS1
11
YS1
G1IN
0.01µ
0.01µ
RGB1IN
13
14
0.01µ
220
220
YM
16
YS2
E/W
0.1µ 0.1µ
100
47µ (MPS)
35
36
33
34
+9V
15
SDA
SGND1
10µ
SCL
52 BLHOLD
37
38
39
40
41
42
43
44
45
46
47
48
49
47µ
2.7k
VM
8.2k 0.01µ 4700p 0.01µ 0.01µ
SYNCOUT
4700p 0.47µ 0.01µ
270
HSIN
3.3k
VSIN
50
220
500k
HP GEN.
+9V
VSFIL
10k
10k
1µ
DVCC2
51
220
1µ
560
330k
100
+9V
HOFF
IREF
100p
1k
17
RGB2IN
18
19
SVCC2 20
RSH 21
ROUT 22
GSH 23
GOUT 24
BSH 25
BOUT 26
IKIN 27
ABLIN/VCOMP 28
ABLFIL 29
VTIM 30
820
1µ
VTIM
VDRV–
0.1µ
100
0.1µ
100
0.1µ
100
20k
20k
0.01µ
47µ
R OUT
G OUT
0.001µ B OUT
9V
10µ
100
100
VD+OUT/VPROT
100
VDRV+
32
VD–OUT/VPROT 31
0.01µ
VM
DGND
–(B-Y) OUT
E-WOUT
SCL
CERA
YOUT
AFCFIL
YRET
L2FIL
B1IN
AFCPIN/HOFF
YS2
SAWOSC
R2IN
VAGCSH
G2IN
HDOUT
–(R-Y) IN
DVCC1
YM
– 19 –
B2IN
SDA
0.01µ
+9V
VPROT
51k
+9V
IK IN
10k
Signal sources
Characteristics.
0.01µ
+9V
CXA2000Q
Electrical Characteristics Measurement Circuit
are all GND unless otherwise specified in the Measurement conditions column of Electrical
from HDOUT
5V
9V
1k
1k
47µ
1
2000p
2
10k
3
TC4538BP
9
10
11
12
13
14
15
16
2000p
10k
VDD
to AFCPIN
2T1
1T1
2T2
1T2
2CD
1CD
2A
4
5
6
1Q
2B
7
1Q
2Q
8
VSS
2Q
1A
– 20 –
1B
HP GEN.
AFCPIN
HDOUT
width12µs
delay 7µs
CXA2000Q
+9V
2.2µ
2.2µ
15p
63 NC
62 X358
61 X443
–(R-Y) OUT
3
4
–(B-Y) OUT
–(R-Y) IN
–(B-Y) IN
8
10
9
11
YS1
0.1µ
0.1µ
0.1µ
220
Color difference Sand castle YS1
pulse output input
outputs from
1H delay line
7
R1IN
12
G1IN
0.01µ
0.01µ
14
Analog RGB
inputs
13
220
YS2/YM
inputs
16
15
220
100
32
VTIM 30
18
19
10µ
0.1µ
100
0.1µ
100
0.1µ
100
0.001µ
1µ
10µ
1k
100
820
100
V protect
signal input
V timing
pulse output
Ik input
ABL/Vertical high
voltage fluctuation
compensation signal
input
10k
V sawtooth
wave outputs
0.01µ
47µ
+9V
RGB outputs
220
VD+OUT/VPROT
100
∗1: Metal film resistor recommended
∗2: MPS capacitor recommended
SVCC2 20
RSH 21
ROUT 22
GSH 23
GOUT 24
BSH 25
BOUT 26
IKIN 27
ABLIN/VCOMP 28
ABLFIL 29
Analog/digital
RGB inputs
17
R2IN
0.01µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
6
5
SECAM reference Color difference
input/output for
outputs for 1H
SECAM IC
delay line
2
1
60 APCFIL
FSC OUT 64
1.5k
58 TEST
57 CIN
56 EXT SYNC IN
55 YIN
59 SVCC1
15k
15p
510
3.579545MHz
4.433619MHz
47µ
0.01µ
0.47µ
0.47µ
470p
C signal input
External sync
signal input
Y signal input
SECAMREF
0.47µ
54 DCTRAN
SGND1
2.2µ
YS2
53 CVIN
YM
VD–OUT/VPROT 31
SDA
G2IN
CV signal input
SCL
0.01µ
52 BLHOLD
VM
0.01µ
4.7µ
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
47µ
SYNCOUT
0.01µ
HSIN
∗2
0.1µ 0.1µ
V parabola wave output
VSIN
5.6k 0.01µ 4700p
+9V
VSFIL
0.1µ
2.7k
100
DVCC2
50
470
0.1µ
IREF
47µ 0.01µ
∗1
10k 500k
2.2µ
10k
DGND
0.47µ
1µ
330k
Hold-down input HP output HD output
CERA
220
3.3k
100
470
2.2k
+9V
AFCFIL
51
220
+9V
L2FIL
220
BUS
VM
input/output output
100p
I2C
0.0047µ
AFCPIN/HOFF
YOUT
HDOUT
YRET
DVCC1
SGND2
SAWOSC
SCPOUT
VAGCSH
B1IN
E-WOUT
B2IN
– 21 –
0.01µ
Application Circuit
CXA2000Q
CXA2000Q
Electrical Characteristics Measurement Conditions "I2C Bus Register Initial Settings"
Register
name
No. of Initial
setting
bits
Register
name
Description
No. of Initial
setting
bits
Description
Maximum value
V FREQ
2
0h
1h
TRAP off
V-POSITION
6
1Fh
1
1h
VM off
AFC-MODE
2
1h
Low gain
HUE
6
1Fh
Center value
S-CORR
4
0h
Minimum value
DCTRAN
1
0h
DCTRAN off
V-LIN
4
7h
Center value
D-PIC
1
0h
DPIC off
H-SIZE
6
1Fh
Center value
COLOR
6
1Fh
Center value
REF-POSI
2
3h
TOT
1
0h
TOT off
PIN-COMP
6
1Fh
BRIGHT
6
1Fh
Center value
VBLKW
2
0h
Minimum value
D-COL
1
0h
DCOL off
H-POSITOPN
4
7h
Center value
SHARPNESS
4
7h
Center value
PIN-PHASE
4
7h
Center value
PRE-OVER
2
3h
Maximum value
AFC-BOW
4
7h
Center value
COLOR SW
2
0h
Automatic switching
AFC-ANGLE
4
7h
Center value
SUB-CONT
4
7h
Center value
SCP BGR
2
1h
Center value
TRAP F0
4
7h
Center value
SCP BGF
2
1h
Center value
SUB-COLOR
4
7h
Center value
XTAL
2
0h
Automatic switching
SUB-HUE
4
7h
Center value
EXT SYNC
1
0h
Internal sync
SUB-BRIGHT
6
1Fh
Center value
CV/YC
1
0h
CV input
GAMMA
2
0h
Minimum value
V-ASPECT
6
0h
Minimum value
G-DRIVE
6
2Ah
Center value
ZOOM SW
1
0h
ZOOM SW off
AGING
1
0h
AGING off
HBLKSW
1
0h
HBLKSW off
B-DRIVE
6
2Ah
Center value
V-SCROLL
6
1Fh
Center value
INTERLACE
2
0h
Interlace
JMPSW
1
0h
JMPSW off
G-CUTOFF
4
0h
Minimum value
HSIZESW
1
0h
HSIZESW off
B-CUTOFF
4
0h
Minimum value
UP-VLIN
4
0h
Minimum value
RON
1
1h
R output on
LO-VLIN
4
0h
Minimum value
GON
1
1h
G output on
LEFT-BLK
4
7h
Center value
BON
1
1h
B output on
RIGHT-BLK
4
7h
Center value
PICON
1
1h
Picture mute off
EHT H
2
0h
EHT H off
VOFF
1
0h
VD output on
EHT V
2
0h
EHT V off
FHHI
1
0h
FH normal
CORNER-PIN
4
7h
Center value
CD-MODE
1
0h
Automatic switching
YS1OFF
1
0h
YS1 normal
AKBOFF
1
0h
AKB on
DL
3
3h
Center value
V-SIZE
6
1Fh
PICTURE
6
3Fh
TRAPOFF
1
VMOFF
Center value
– 22 –
Automatic switching
Center value
Maximum value
Center value
CXA2000Q
Definition of I2C Bus Registers
Slave Addresses
88h: Slave Receiver
89h: Slave Transmitter
Register Table
"∗": Undefined
Control Register
Sub Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
× × × 0 0 0 0 0 00 h
PICTURE
× × × 0 0 0 0 1 01 h
HUE
DC-TRAN
D-PIC
× × × 0 0 0 1 0 02 h
COLOR
TOT
∗
× × × 0 0 0 1 1 03 h
BRIGHT
D-COL
∗
TRAPOFF VMOFF
× × × 0 0 1 0 0 04 h
SHARPNESS
× × × 0 0 1 0 1 05 h
SUB-CONT
TRAP F0
× × × 0 0 1 1 0 06 h
SUB-COLOR
SUB-HUE
PRE-OVER
× × × 0 0 1 1 1 07 h
SUB-BRIGHT
× × × 0 1 0 0 0 08 h
G-DRIVE
× × × 0 1 0 0 1 09 h
B-DRIVE
× × × 0 1 0 1 0 0A h
× × × 0 1 0 1 1 0B h
GAMMA
AGING
GON
0
INTERLACE
B-CUTOFF
G-CUTOFF
RON
COLOR SW
BON
PICON
VOFF
FHHI
CD-MODE AKBOFF
× × × 0 1 1 0 0 0C h
V-SIZE
V-FREQ
× × × 0 1 1 0 1 0D h
V-POSITION
AFC-MODE
× × × 0 1 1 1 0 0E h
V-LIN
S-CORR
× × × 0 1 1 1 1 0F h
H-SIZE
REF-POSI
× × × 1 0 0 0 0 10 h
PIN-COMP
VBLKW
× × × 1 0 0 0 1 11 h
H-POSITION
PIN-PHASE
× × × 1 0 0 1 0 12 h
AFC-BOW
AFC-ANGLE
× × × 1 0 0 1 1 13 h
SCP BGR
SCP BGF
XTAL
EXT SYNC CV/YC
× × × 1 0 1 0 0 14 h
V-ASPECT
ZOOM SW HBLKSW
× × × 1 0 1 0 1 15 h
V-SCROLL
JMP SW HSIZESW
× × × 1 0 1 1 0 16 h
UP-VLIN
LO-VLIN
× × × 1 0 1 1 1 17 h
LEFT-BLK
RIGHT-BLK
× × × 1 1 0 0 0 18 h
× × × 1 1 0 0 1 19 h
EHT H
CORNER-PIN
EHT V
∗
∗
∗
∗
YS1 OFF
Bit7
Bit6
Bit5
Bit4
Bit3
H LOCK
IKR
VNG
XRAY
DL
Status Register
– 23 –
Bit2
COLOR SYS
Bit1
Bit0
CV SYNC
CXA2000Q
Description of Registers
Register name (No. of bits)
1. Video switch register
CV/YC
(1)
: CV input/YC input selector
0 = CV input selected
1 = YC input selected
EXT SYNC
(1)
: EXT SYNC selector switch
0 = Internal sync (CV or Y) selected
1 = EXT SYNC selected
2. Y signal block register
SUB-CONT
(4)
: Contrast gain control (Y gain control)
0h = –3.5dB
7h =
0dB
Fh = +2.5dB
TRAP-F0
(4)
: Chroma trap f0 fine adjustment (Y block chroma trap current control)
0h = High
7h = Center
Fh = Low
SHARPNESS (4)
: Sharpness gain control (Sharpness F0 3MHz)
0h = –6dB
7h = +2.5dB
Fh = +6.5dB
PRE-OVER
(2)
: Sharpness preshoot/overshoot ratio control
0h = 1:1
(PRE: OVER)
3h = 2:1
VM OFF
(1)
: Y signal output ON/OFF for VM
0 = ON
1 = OFF
TRAP OFF
(1)
: Y block chroma trap ON/OFF
0 = Trap ON
1 = Trap OFF
DL
(3)
: Y signal delay time control (80ns/step)
0h = Max.
7h = Min.
– 24 –
CXA2000Q
DC-TRAN
(1)
: Y DC transmission ratio selector switch
0 = 100%
1 = 81%
D-PIC
(1)
: Y black expansion ON/OFF switch
0 = OFF
1 = ON
Point of inflection: 30 IRE
3. C signal block register
TOT
(1)
: Chroma TOT filter band selector switch
0 = TOT — TRAP OFF
1 = TOT — TRAP ON (TRAP fo 2MHz)
COLOR
(6)
: Color gain control (Chroma gain control)
0h = Color OFF (–40dB or less)
1Fh = 0dB B output: 1.02Vp-p (I/O gain: +11dB, 0.285Vp-p input)
3Fh = +6dB
SUB-COLOR (4)
: Color gain control (ACC reference level control)
0h = –5dB
7h = 0dB
Fh = +3dB
HUE
(6)
: Hue control (Phase control for chroma demodulation axis when SUB-HUE is 7h)
Control not possible for a PAL system.
0h = +35° Flesh color appears red.
1Fh = 0°
3Fh = –35° Flesh color appears green.
SUB-HUE
(4)
: Hue control (Phase control for chroma demodulation axis when HUE is 1Fh)
B-Y axis adjustable to 0°.
Control not possible for a PAL system.
0h = +10°
7h = 0°
Fh = –10°
XTAL
(2)
: XTAL selection setting switch
0h = Automatic identification
1h = Force to XTAL1 (3.58MHz)
2h = Force to XTAL2 (4.43MHz)
COLOR SW
(2)
: Color system setting
0h = Automatic identification
1h = Force to PAL
2h = Force to NTSC
3h = Force to SECAM
– 25 –
CXA2000Q
4. RGB signal block register
PICTURE
(6)
: Picture gain control (RGB gain control)
0h = –14dB
3Fh = 0dB RGB output: 2.5Vp-p (I/O gain: +8dB, 1Vp-p input)
BRIGHT
(6)
: Bright control (RGB DC bias control)
0h = –440mV
1Fh =
0mV (–300mV for REF-P level)
3Fh = +450mV
SUB-BRIGHT (6)
: Bright control (RGB DC bias control)
0h = –440mV
1Fh =
0mV (–300mV for REF-P level)
3Fh = +450mV
G-DRIVE
(6)
: Gch drive gain adjustment (Gch gain control)
0h = G/R –4.5dB
2Ah = G/R
0dB (G/R 0dB)
3Fh = G/R +1.5dB
B-DRIVE
(6)
: Bch drive gain adjustment (Bch gain control)
0h = B/R –4.5dB
2Ah = B/R
0dB (B/R 0dB)
3Fh = B/R +1.5dB
G-CUTOFF
(4)
: Gch cut-off adjustment (Gch reference pulse value control of IKIN pin input)
0h = +34%
7h = +81% (G/R)
Fh = +135%
B-CUTOFF (4): Bch cut-off adjustment (Bch reference pulse value control of IKIN pin input)
0h = +34%
7h = +81% (B/R)
Fh = +135%
D-COL
(1)
: Dynamic color ON/OFF switch
0 = Dynamic color OFF
1 = Dynamic color ON (R, Bch level control)
GAMMA
(2)
: Gamma control (RGB gamma correction amount control)
0h = Gamma OFF
3h = Gamma peak 17 IRE (at input 40 IRE), +400mV (at 2.5Vp-p OUT)
– 26 –
CXA2000Q
REF-POSITION (2)
: Reference pulse timing setting
0h = From rising edge of V TIM: Rch 22H, Gch 23H, Bch 24H
1h = From rising edge of V TIM: Rch 20H, Gch 21H, Bch 22H
2h = From rising edge of V TIM: Rch 18H, Gch 19H, Bch 20H
3h = From rising edge of V TIM: Rch 16H, Gch 17H, Bch 18H
PIC-ON
(1)
: ON/OFF switch for RGB output with a reference pulse
(Set to OFF mode at power-on.)
0 = RGB output OFF (All blanked status)
1 = RGB output ON
R ON
(1)
: ON/OFF switch for Rch video output without a reference pulse
(Operates when PIC ON = 1, set to OFF mode at power-on.)
0 = Rch video output OFF (Blanked status, reference pulse only output)
1 = Rch video output ON
G ON
(1)
: ON/OFF switch for Gch video output without a reference pulse
(Operates when PIC ON = 1, set to OFF mode at power-on.)
0 = Gch video output OFF (Blanked status, reference pulse only output)
1 = Gch video output ON
B ON
(1)
: ON/OFF switch for Bch video output without a reference pulse
(Operates when PIC ON = 1, set to OFF mode at power-on.)
0 = Bch video output OFF (Blanked status, reference pulse only output)
1 = Bch video output ON
AKB OFF
(1)
: AKB ON/OFF switch (Set to ON mode at power-on.)
0 = AKB ON
1 = AKB OFF (IK CLAMP, IK S/H and reference pulse fixed to OFF)
R, G and B cut-off adjustment at AKB OFF performed by voltage applied to RSH,
GSH and BSH pins, respectively.
YS1 OFF
(1)
: YS1 forced OFF mode/YS1 normal mode
0 = YS1 normal mode
1 = YS1 forced OFF mode
– 27 –
CXA2000Q
5. Deflection block register
AFC-MODE
(2)
: AFC loop gain control (PLL between H SYNC and H VCO)
0h = H free run mode
1h = Small gain
2h = Medium gain
3h = Large gain
FH-HI
(1)
: H oscillator frequency fixation ON/OFF switch
(Set to ON mode at power-on.)
0 = H oscillator frequency fixation OFF AFC normal mode
1 = H oscillator frequency fixation ON Oscillator frequency fixed to maximum value
(approx. 16.2kHz).
V FREQ
(1)
: V frequency mode setting
0, 1h = Automatic identification
2h = Forced mode (50Hz)
3h = Forced mode (60Hz)
V OFF
(1)
: V sawtooth wave oscillation stop ON/OFF switch
(Set to OFF mode at power-on.)
0 = Oscillation stop OFF (V DRIVE– and V DRIVE+: normal output)
1 = Oscillation stop ON (V DRIVE– and V DRIVE+: DC output and DC value vary
according to V POSITION.)
CD-MODE
(1)
: V countdown system mode selector
(Set to automatic selection mode during power-on.)
0 = Non-standard signal mode, standard signal mode and no signal mode
automatically selected
1 = Fixed to non-standard signal mode
(V oscillator frequency is 55Hz during no signal mode "free run".)
VBLKW
(2)
: VBLK width control (Blanked pulses after reference pulse. Operates when
JMPSW = 1; blanked pulses after reference pulse fixed to 1H when JMPSW = 0.)
0h = 12H from Bch reference pulse
1h = 11H from Bch reference pulse
2h = 10H from Bch reference pulse
3h = 9H from Bch reference pulse
H-POSITION (4)
: Horizontal position adjustment (HAFC phase control)
0h = 1µs delay
Picture position shifts to right. (Picture delayed with respect to HD.)
7h = 0µs
Fh = 1µs advance
Picture position shifts to left. (Picture advanced with respect to HD.)
V-POSITION
: Vertical position adjustment (V SAW output DC bias control)
0h = –0.09V Picture position drops, V DRIVE+ output DC Down.
1Fh =
0V Center potential: DC 3V
3Fh = +0.09V Picture position rises, V DRIVE+ output DC Up.
(6)
– 28 –
CXA2000Q
V-SIZE
(6)
: Vertical amplitude adjustment (V SAW output gain control)
0h = –14% Vertical picture size decreases.
1Fh = 0% Amplitude: 1.23Vp-p, center potential: DC 3V when V-ASPECT is 2FH.
3Fh = +14% Vertical picture size increases.
V-LIN
(4)
: Vertical linearity adjustment (Gain control for V SAW secondary component)
0h = 115%
(Bottom/top of picture) Top of picture compressed; bottom of picture
expanded.
7h = 100%
(Bottom/top of picture)
Fh = 85%
(Bottom/top of picture) Top of picture expanded; bottom of picture
compressed.
S-CORR
(4)
: Vertical S correction amount adjustment (V SAW secondary component gain control)
0h = Secondary component amplitude by adding sawtooth and other signals = 0
Fh = Secondary component amplitude by adding sawtooth and other signals = Maximum
AFC-BOW
(4)
: Vertical line bow compensation amount adjustment (Phase control according to
HAFC parabola wave)
0h = Top and bottom of picture delayed 500ns with respect to picture center.
7h = 0 ns
Fh = Top and bottom of picture advanced 500ns with respect to picture center.
AFC-ANGLE
(4)
: Vertical line slope compensation amount adjustment (Phase control according to
HAFC V SAW)
0h = Top of picture delayed 500ns, bottom of picture advanced 500ns with respect to
picture center.
7h = 0 ns
Fh = Top of picture advanced 500ns, bottom of picture delayed 500ns with respect to
picture center.
PIN-COMP
(6)
: Horizontal pin distortion compensation amount adjustment (V parabola wave gain
control)
0h = 0.10Vp-p Horizontal size for top/bottom of picture increases. (Compensation
amount minimum)
1Fh = 0.58Vp-p Amplitude, center potential: DC 4V when V-ASPECT is 2Fh
3Fh = 1.06Vp-p Horizontal size for top/bottom of picture decreases. (Compensation
amount maximum)
H-SIZE
(6)
: Horizontal amplitude adjustment (V parabola wave DC bias control)
0h = –0.5V Horizontal picture size decreases, EW-DRIVE output DC Down.
1Fh =
0V Amplitude: 0.58Vp-p, center potential: DC 4 V when V-ASPECT is 2Fh
3Fh = +0.5V Horizontal picture size increases, EW-DRIVE output DC Up.
EHT-H
(2)
: Horizontal high-voltage fluctuation compensation amount setting (DC adjustment for
parabolic output)
0h =
0V (Compensation amount when 1V is applied to ABL IN versus 8V applied
to ABL IN)
3h = –0.1V (Compensation amount when 1V is applied to ABL IN versus 8V applied
to ABL IN)
EHT-V
(2)
: Vertical high-voltage fluctuation compensation amount setting (V SAW output gain control)
0h = 0% (Compensation amount when 1V is applied to ABL IN versus 8V applied to
ABL IN)
3h = –7% (Compensation amount when 1V is applied to ABL IN versus 8V applied to
ABL IN)
INTERLACE
(1)
: Interlace mode and non-interlace display selector switch
0,1h = Interlace mode
2h = Interlace mode; 1/2H shift applied to EVEN lines
3h = Interlace mode; 1/2H shift applied to ODD lines
– 29 –
CXA2000Q
PIN-PHASE
(4)
: Horizontal trapezoidal distortion compensation amount adjustment (V parabola wave
center timing control)
0h = 1.5ms advance Horizontal size for top of picture increases; horizontal size for
bottom of picture decreases.
7h = 0ms
8.9ms from 4VDC VTIM
Fh = 1.5ms delay
Horizontal size for top of picture decreases; horizontal size
for bottom of picture increases.
CORNER-PIN (4)
: Horizontal pin distortion compensation amount adjustment for top/bottom of picture
(V parabola wave top/bottom gain control)
0h = –0.2V
Horizontal size for top/bottom of picture decreases.
(compensation amount maximum)
7h = 0V
(0.7Vp-p 4:3 mode)
Fh = +0.2V
Horizontal size for top/bottom of picture increases.
(compensation amount minimum)
V-ASPECT
(6)
: Aspect ratio control. (Gain control for sawtooth wave)
0h = 75%
16:9 CRT full
2Fh = 100% 4:3 CRT full, amplitude: 1.23Vp-p
3Fh = 112%
ZOOM SW
(1)
: Zoom mode ON/OFF switch for 16:9 CRT (25% of video cut)
0 = Zoom OFF
Sawtooth wave amplitude: 1.23Vp-p
1 = Zoom ON
Sawtooth wave amplitude: 70%
HBLKSW
(1)
: HBLK width control ON/OFF switch during 4:3 software full display mode on a 16:9
CRT
0 = Control OFF HBLK pulse generated from HPIN.
1 = Control ON
HBLK pulse generated as pulse generated from HPIN or as
pulse generated from HVCO and width adjusted.
Width adjustment is performed by the LEFT-BLK and
RIGHT-BLK registers.
V-SCROLL
(6)
: Vertical picture scroll control during zoom mode on a 16:9 CRT
(DC component added to sawtooth wave AGC output to control ZOOMSW cut
timing.)
0h = –0.2V Scrolled toward top of screen by 32H and top of picture zoomed.
1Fh =
0V
3Fh = +0.2V Scrolled toward bottom of screen by 32H and bottom of picture zoomed.
JUMPSW
(1)
: Reference pulse jump mode ON/OFF switch (In addition to V-ASPECT control, sawtooth
wave gain control performed for 100% of VBLK interval and 67% of picture interval)
0 = Jump mode OFF
1 = Jump mode ON
On a 4:3 CRT, jump mode expands the sawtooth wave amplitude to 112% with VASPECT; on a 16:9 CRT, jump mode compresses the sawtooth wave amplitude to
75% with V-ASPECT. The V blanking width is expanded at both the top and bottom
of the picture. Blanking for the bottom of the picture starts 251H after VTIM, and
blanking for the top of the picture can be varied as the blanking width after the
reference pulse from the VBLKW register.
HSIZESW
(1)
: Lowers the E-W OUT DC level (during H-SIZE compression)
0 = Normal
1 = –1.35V
– 30 –
CXA2000Q
UP-VLIN
(4)
: Vertical linearity adjustment for top of picture (Secondary component gain control for
sawtooth wave added to sawtooth wave AGC output)
0h = 100%
(Bottom/top of picture)
Fh = 115%
(Bottom/top of picture) Top of picture compressed.
LO-VLIN
(4)
: Vertical linearity adjustment for bottom of picture (Tertiary component gain control
for sawtooth wave added to sawtooth wave AGC output)
0h = 100%
(Bottom/top of picture)
Fh = 85%
(Bottom/top of picture) Bottom of picture compressed.
LEFT-BLK
(4)
: HBLK width control for the left side of picture when HBLKSW = 1 (Phase control for
timing pulse generated from HVCO)
0h = +1.3µs
HBLK width maximum
7h =
0µs
Center HBLK: 13µs
Fh = –1.3µs HBLK width minimum
RIGHT-BLK
(4)
: HBLK width control for the right side of picture when HBLKSW = 1 (Phase control for
timing pulse generated from HVCO)
0h = +1.3µs
HBLK width maximum
7h =
0µs
Center HBLK: 13µs
Fh = –1.3µs HBLK width minimum
SCP BGR
(2)
: Controls the phase of the rising edge of the burst pulse in sand castle pulse output
(0.4µs/step)
0h = +0.4µs
1h = Center
3h = –0.8µs
SCP BGF
(2)
: Controls the phase of the falling edge of the burst pulse in sand castle pulse output
(0.4µs/step)
0h = +0.4µs
1h = Center
3h = –0.8µs
(1)
: White output aging mode ON/OFF switch
(Takes priority over RGB ON and PIC ON control. Set to OFF mode at power-on.)
0 = Aging mode OFF
1 = Aging mode ON (When there is no input signal, a 60 IRE flat signal is output
from the Y block)
6. Other
AGING
– 31 –
CXA2000Q
7. Status register
HLOCK
(1)
: Lock status between H SYNC and H VCO
0 = HVCO free run status
1 = Locked to H SYNC
IKR
(1)
: AKB operation status
0 = REF-P at Ik small and AKB loop unstable.
1 = REF-P at Ik sufficient and AKB loop stable.
VNG
(1)
: Signal input status to V PROT pin
0 = No V PROT input
1 = V PROT input (In this case, the RGB output is blanked.)
XRAY
(1)
: Signal input status to XRAY control pin (HOFF pin)
0 = No XRAY control input
1 = XRAY control input (In this case, the RGB output is blanked.)
COLOR SYS (3)
: Color system status
0h = —
1h = —
2h = NO STANDARD
3h = SECAM
4h = 3.58MHz NTSC
5h = 4.43MHz NTSC
6h = 3.58MHz PAL
7h = 4.43MHz PAL
CV SYNC
: CV input SYNC SEP result
When VIDEO is input to CVIN, "1" is returned when the SYNC level is 100mV or
more (standard: 300mV)
0 = No SYNC
1 = SYNC
(1)
– 32 –
CXA2000Q
Description of Operation
1. Power-on sequence
The CXA2000Q does not have an internal power-on sequence. Therefore, power-on sequence is all controlled
by the set microcomputer (I2C bus controller).
1) Power-on
The IC is reset and the RGB outputs are all blanked. Hdrive starts to oscillate, but oscillation is at the
maximum frequency (16kHz or more) and is not synchronized to the input signal. Output of vertical signal
VTIM starts, but Vdrive is DC output. Bus registers which are set by power-on reset are as follows.
AGING
RON
GON
BON
PICON
VOFF
VFREQ
FHHI
HSIZESW
CD-MODE
AKBOFF
= 0: All white output aging mode OFF
= 0: Rch video blanking ON
= 0: Gch video blanking ON
= 0: Bch video blanking ON
= 0: RGB all blanking ON
= 1: VDRIVE output stopped mode
= 0: Automatic identification mode (identification starts at 50Hz)
= 1: H oscillator maximum frequency mode
= 0: Normal
= 0: Automatic selection mode of the countdown mode
= 0: AKB mode
2) Bus register data transfer
The register setting sequence differs according to the set sequence. Register settings for the following
sequence are shown as an example.
Set sequence
Power-on
↓
Degauss
↓
VDRIVE oscillation
↓
AKB operation start
↓
AKB loop stable
↓
Video output
CXA2000Q register settings
Reset status in 1) above.
↓
Reset status in 1) above.
The CRT is degaussed in the completely darkened condition.
↓
The IC is set to the power-on initial settings. (See the following page.)
A sawtooth wave is output to VDRIVE and the IC waits for the vertical
deflection to stabilize. The HDRIVE oscillator frequency goes to the standard
frequency.
↓
PICON is set to 1 and a reference pulse is output from Rout, Gout and Bout.
Then, the IC waits for the cathode to warm up and the beam current to start
flowing.
↓
Status register IKR is monitored.
IKR = 0: No cathode current
IKR = 1: Cathode current
Note that the time until IKR returns to 1 differs according to the initial status
of the cathode.
↓
RON, GON and BON are set to 1 and the video signal is output from Rout,
Gout and Bout.
– 33 –
CXA2000Q
I2C bus power-on initial settings
The initial settings listed here for power-on when VDRIVE starts to oscillate are reference values; the actual
settings may be determined as needed according to the conditions under which the set is to be used.
Register Table
"∗" Undefined
Control Register
Sub Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
× × × 0 0 0 0 0 00 h
1
1
1
1
1
1
0
0
× × × 0 0 0 0 1 01 h
0
1
1
1
1
1
0
1
× × × 0 0 0 1 0 02 h
0
1
1
1
1
1
0
∗
× × × 0 0 0 1 1 03 h
0
1
1
1
1
1
1
∗
× × × 0 0 1 0 0 04 h
0
1
1
1
0
0
0
0
× × × 0 0 1 0 1 05 h
0
1
1
1
0
1
1
1
× × × 0 0 1 1 0 06 h
0
1
1
1
0
1
1
1
× × × 0 0 1 1 1 07 h
0
1
1
1
1
1
0
0
× × × 0 1 0 0 0 08 h
0
1
1
1
1
1
0
0
× × × 0 1 0 0 1 09 h
0
1
1
1
1
1
0
0
× × × 0 1 0 1 0 0A h
0
1
1
1
0
1
1
1
× × × 0 1 0 1 1 0B h
0
0
0
0
0
0
0
0
× × × 0 1 1 0 0 0C h
0
1
1
1
1
1
0
0
× × × 0 1 1 0 1 0D h
0
1
1
1
1
1
1
0
× × × 0 1 1 1 0 0E h
0
1
1
1
0
1
1
1
× × × 0 1 1 1 1 0F h
0
1
1
1
1
1
0
0
× × × 1 0 0 0 0 10 h
0
1
1
1
1
1
0
0
× × × 1 0 0 0 1 11 h
0
1
1
1
0
1
1
1
× × × 1 0 0 1 0 12 h
0
1
1
1
0
1
1
1
× × × 1 0 0 1 1 13 h
0
1
0
1
0
0
0
0
× × × 1 0 1 0 0 14 h
0
0
0
0
0
0
1
1
× × × 1 0 1 0 1 15 h
0
1
1
1
1
1
0
0
× × × 1 0 1 1 0 16 h
0
1
1
1
0
1
1
1
× × × 1 0 1 1 1 17 h
0
1
1
1
1
1
1
1
× × × 1 1 0 0 0 18 h
0
0
1
1
0
1
1
1
× × × 1 1 0 0 1 19 h
∗
∗
∗
∗
0
0
1
1
– 34 –
CXA2000Q
3) Power-on initial settings
The initial settings listed here for power-on when VDRIVE starts to oscillate are reference values; the actual
settings may be determined as needed according to the conditions under which the set is to be used.
PICTURE
= 3Fh
Max (User Control)
TRAP OFF
=0
Chroma Trap ON
VM OFF
=0
VM out ON
HUE
= 1Fh
Center (User Control)
DC-TRAN
=0
Y DC transmission ratio 100%
D-PIC
=1
Y black expansion ON
COLOR
= 1Fh
Center (User Control)
TOT
=0
Chroma low frequency increased
BRIGHT
= 1Fh
Center (User Control)
D-COL
=1
Dynamic Color ON
SHARPNESS = 7h
Center (User Control)
PRE-OVER
=0
Sharpness pre/over ratio 1:1
COLOR SW = 0
AUTO
SUB-CONT
= 7h
Center (Adjust)
TRAP F0
= 7h
Center (Adjust)
SUB-COLOR = 7h
Center (Adjust)
SUB-HUE
= 7h
Center (Adjust)
SUB-BRIGHT = 1Fh
Center (Adjust)
GAMMA
=0
Gamma OFF
G-DRIVE
= 1Fh
Center (Adjust)
AGING
=0
Aging Mode OFF
B-DRIVE
= 1Fh
Center (Adjust)
INTERLACE = 0
INTERLACE mode
G-CUTOFF
= 7h
Center (Adjust)
B-CUTOFF
= 7h
Center (Adjust)
RON
=0
Rch video output OFF
GON
=0
Gch video output OFF
BON
=0
Bch video output OFF
PICON
=0
RGB all blanked
VOFF
=0
Vdrive oscillation
FHHI
=0
Horizontal oscillator frequency standard
CD-MODE
=0
V countdown auto mode
AKBOFF
=0
AKB ON
V-SIZE
= 1Fh
Center (Adjust)
V-FREQ
=0
AUTO
V-POSITION = 1Fh
Center (Adjust)
AFC-MODE = 2
Center
S-CORR
= 7h
Center (Adjust)
V-LIN
= 7h
Center (Adjust)
H-SIZE
= 1Fh
Center (Adjust)
REF-POSI
=0
PIN-COMP
= 1Fh
Center (Adjust)
VBLKW
=0
– 35 –
CXA2000Q
(Power-on initial settings cont.)
H-POSITION
PIN-PHASE
AFC-BOW
AFC-ANGLE
SCP BGR
SCP BGF
XTAL
EXT SYNC
CV/YC
V-ASPECT
ZOOMSW
HBLKSW
V-SCROLL
JMPSW
HSIZE SW
UP-VLIN
LO-VLIN
LEFT-BLK
RIGHT-BLK
EHT-H
EHT-V
CORNERPIN
YS1 OFF
DL
= 7h
= 7h
= 7h
= 7h
=1
=1
=0
=0
=0
= 0h
=1
=1
= 1Fh
=0
=0
= 7h
= 7h
= Fh
= Fh
=0
=3
= 7h
=0
=3
Center (Adjust)
Center (Adjust)
Center (Adjust)
Center (Adjust)
Center
Center
AUTO
Internal SYNC
CV input
16:9 CRT Full Mode
16:9 CRT
Hblk width adjust ON
Center (User Control)
16:9 CRT Full Mode
Normal
16:9 CRT Full Mode
16:9 CRT Full Mode
Hblk width Min.
Hblk width Min.
Hdrive high-voltage compensation OFF
Vdrive high-voltage compensation amount maximum
Center (Adjust)
Normal
Normal (Adjust)
2. Various mode settings
The CXA2000Q contains bus registers for deflection compensation which can be set for various wide modes.
Wide mode setting registers can be used separately from registers for normal picture distortion adjustment,
and once deflection adjustment has been performed in full mode, wide mode settings can be made simply by
changing the corresponding register data.
• VDRIVE signal picture distortion adjustment registers
V-SIZE, V-POSITION, S-CORR, V-LIN
• E/WDRIVE signal picture distortion adjustment registers
H-SIZE, PIN-COMP, PIN-PHASE, CORNER-PIN
• Wide mode setting registers
V-ASPECT, ZOOMSW, HBLKSW, V-SCROLL, JMPSW, HSIZESW, UP-VLIN, LO-VLIN,
LEFT-BLK, RIGHT-BLK
– 36 –
CXA2000Q
Examples of various modes are listed below. These modes are described using 570 (NTSC: 480) lines as the
essential number of display scanning lines. Wide mode setting register data is also listed, but settings may
differ slightly due to IC variation. The standard setting data differs for 16:9 CRTs and 4:3 CRTs.
Register
V-ASPECT
V-SCROLL
ZOOMSW
UP-VLIN
LO-VLIN
JMPSW
HSIZESW
HBLKSW
LEFT-BLK
RIGHT-BLK
16:9 CRT
4:3 CRT
0h
1Fh
1
0h
0h
0
0
0
7h
7h
2Fh
1Fh
0
0h
0h
0
0
0
7
7h
1) 16:9 CRT full mode
This mode reproduces the full 570 (NTSC:480) lines on a 16:9 CRT. 4:3 images are reproduced by stretching
the picture to the left and right.
Normal images are compressed vertically, but 16:9 images can be reproduced in their original 16:9 aspect
ratio with a video source which compresses (squeezes) 16:9 images to 4:3 images. The register settings are
the 16:9 CRT standard values.
2) 16:9 CRT normal mode
In this mode, 4:3 images are reproduced without modification. A black border appears at the left and right of
the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The
CXA2000Q permits compression with a register (HSIZESW) that compresses the H size by 25%. Because
excessive current flows to the horizontal deflection coil in this case, adequate consideration must be given to
the allowable power dissipation, etc., of the horizontal deflection coil in the design of the set. In addition, this
concern can also be addressed through measures taken external to the IC, such as by switching the horizontal
deflection coil. Full mode should be used when using memory processing to add a black border to the video
signal.
H blanking of the image normally uses the flyback pulse input to AFCPIN (Pin 38). However, the blanking
width can be varied according to the control register setting when blanking is insufficient for the right and left
black borders.
The following three settings are added to the 16:9 CRT standard values for the register settings.
HBLKSW = 1
LEFT-BLK = Adjustment value
RIGHT-BLK = Adjustment value
The H angle of deflection also decreases, causing it to differ from the PIN compensation amount during H size
full status. Therefore, in addition to the wide mode registers, PIN-COMP must also be readjusted only for this
mode.
3) 16:9 CRT zoom mode
In this mode, 4:3 images are reproduced by enlarging the picture without other modification. The top and
bottom of normal 4:3 images are lost, but almost the entire picture can be reproduced for vista size video
software, etc. which already has black borders at the top and bottom. The enlargement ratio can be controlled
by the V-ASPECT register, and enlarging the picture by 33% compared to full mode allows zooming to be
performed for 4:3 images without distortion. In this case, the number of scanning lines is reduced to 430 lines
compared to 570 lines for full mode. The zooming position can be shifted vertically by the V-SCROLL register.
V blanking of the image normally begins from V sync and continues for 2H after the AKB reference pulse, and
the top and bottom parts are also blanked during this mode.
Adjust the following two registers with respect to the 16:9 CRT standard values for the register settings.
V-ASPECT = 2Fh
V-SCROLL = 1Fh or user control
– 37 –
CXA2000Q
4) 16:9 CRT subtitle-in mode
When CinemaScope size images which have black borders at the top and bottom of the picture are merely
enlarged with the zoom mode in 3) above, subtitles present in the black borders may be lost. Therefore, this
mode is used to super-compress only the subtitle part and reproduce it on the display.
Add the LO-VLIN adjustment to the zoom mode settings for the register settings.
V-ASPECT = 2Fh
V-SCROLL = 1Fh or user control
LO-VLIN = Adjustment value
The LO-VLIN register causes only the linearity at the bottom of the picture to deteriorate. Therefore, UP-VLIN
should also be adjusted if the top and bottom of the picture are to be made symmetrical. Since the picture is
compressed vertically, the number of scanning lines exceeds 430 lines.
5) 16:9 CRT V compression mode
This mode is used to reproduce two 4:3 video displays such as for PandP. The V size must be compressed to
67% in order to reproduce two displays on a 16:9 CRT without distortion using 480 scanning lines, and this can
be set by JMPSW. Compression is performed after the AKB reference pulse, so the reference pulse remains in
the overscan position. The V blanking width after the reference pulse becomes larger than normal and can be
varied by the VBLKW register. During this mode, the bottom V blanking width is also expanded to 3H wider
than normal so that the bottom of the picture is not overscanned.
16:9 CRT standard values are used with only the JMPSW setting changed for the register settings.
JMPSW = 1
6) 16:9 CRT wide zoom mode
This mode reproduces 4:3 video software naturally on wide displays by enlarging 4:3 images without other
modification and compressing the parts of the image which protrude from the picture into the top and bottom
parts of the picture. The display enlargement ratio is controlled by V-ASPECT, and the compression ratios at
the top and bottom of the picture are controlled by UP-VLIN and LO-VLIN.
Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings.
V-ASPECT = Adjustment value
UP-VLIN = Adjustment value
LO-VLIN = Adjustment value
7) 4:3 CRT normal mode
This is the standard mode for 4:3 CRTs.
The register settings are the 4:3 CRT standard values.
8) 4:3 CRT V compression mode
This mode is used to reproduce M-N converter output consisting of 16:9 images expanded to a 4:3 aspect ratio
and other squeezed signals without distortion on a 4:3 CRT. The V size must be compressed to 75% in order
to reproduce a 4:3 squeezed signal at a 16:9 aspect ratio without any distortion. Compressing the V size with
the JMPSW register used in mode 5) above, compresses the V size to 67%. Therefore, V-ASPECT is set to
enlarge the V size by 8%. AKB reference pulse handling and V blanking are the same as for mode 5) above.
4:3 CRT standard values are used with the V-ASPECT and JMPSW settings changed for the register settings.
V-ASPECT = 3Fh
JMPSW
=1
– 38 –
CXA2000Q
Mode Settings
Setting CRT SIZE SOFT SIZE
I2C BUS REGISTER
MODE NAME
1)-1
16:9
16:9
16:9 CRT full
V-ASPECT = 0h: V size 75%
1)-2
16:9
4:3
Wide full
V-ASPECT = 0h: V size 75%
16:9 CRT normal
V-ASPECT = 0h: V size 75%
HBLKSW = 1h: HBLK width adjustment ON
LEFT-BLK = Adjustable
RIGHT-BLK = Adjustable
PIN-COMP = Adjustable
(External support: H-DY H amplitude 75%)
16:9 CRT zoom
V-ASPECT = 2Fh: V size 100%
ZOOMSW = 1h: Zoom ON
V size limited at 75%
V-SCROLL = 0h: Zoom bottom of video image
1Fh: Zoom center of video image
3Fh: Zoom top of video image
Adjustable: Open to user
16:9 CRT with
subtitle area on
V-ASPECT = 2Fh: V size 100%
UP-VLIN
= Adjustable: Slightly compresses top of
video image
LO-VLIN
= Adjustable: Significantly compresses
bottom of video image
ZOOMSW
1h: V size limited at 75%
(V-SCROLL = Adjustable)
4:3
16:9 CRT V
compression
V-ASPECT = 0h: V size 75%
JMPSW
= 1h: Reference pulse skipping ON
V size compressed 67% after the reference pulse
(compressed to 50% total)
VBLKW
= Adjustable: VBLK width expanded at
top and bottom of video image
V-ASPECT = Adjustable: V size 90%
UP-VLIN
= Adjustable:
Compression of top and
LO-VLIN
= Adjustable:
bottom of video image
(S-CORR = Adjustable):
2)
3)
4)
5)
16:9
16:9
16:9
16:9
4:3
4:3
4:3
(16:9
+ subtitle
area)
6)
16:9
4:3
16:9 CRT wide
zoom
7)
4:3
4:3
4:3 CRT normal
V-ASPECT = 2Fh: V size 100%
4:3 CRT V
compression
V-ASPECT = 3Fh: V size 112%
JMPSW
= 1h: Reference pulse skipping ON
(compressed to 75% total)
VBLKW
= Adjustable: VBLK width expanded at
top and bottom of video image
8)
4:3
16:9
∗ The amount of picture distortion compensation in a vertical direction position of the CRT does not change in
response to the above modes; as a result, the initial values of each picture distortion register can be used as
is.
– 39 –
CXA2000Q
3. Signal processing
The CXA2000Q is comprised of sync signal processing, H deflection signal processing, V deflection signal
processing, and Y/C/RGB signal processing blocks, all of which are controlled by the I2C bus.
1) Sync signal processing
Pin 48 (SYNC OUT) outputs at 2Vp-p either the internal signal (CVIN/YIN) selected by the internal video
switch, or the external sync signal input from Pin 56 (EXT SYNC IN).
This selection is controlled by the I2C bus. The signal output from Pin 48 is buffered by a PNP Tr. and is then
input to HSIN (Pin 47) or VSIN (Pin 46) through a suitable filter.
The Y signals input to Pins 46 and 47 are sync separated by the horizontal and vertical sync separation
circuits. The resulting horizontal sync signal and the signal (FH = 15625Hz or 15734Hz) obtained by frequency
dividing the 32FH-VCO output using the ceramic oscillator (frequency 500kHz or 503.5kHz) by 32 are phasecompared, the AFC loop is constructed, and an H pulse synchronized with the H sync is generated inside the
IC. Adjustment of the H oscillator frequency is unnecessary. When the AFC is locked to the H sync, 1 is output
to the status register (HLOCK) and that can be used to detect the presence of the video signal.
The vertical sync signal is sent to the V countdown block where the most appropriate window processing is
performed to obtain V sync timing information which resets the counter. AKB and other V cycle timing are then
generated from this reset timing.
2) H deflection signal processing
The H pulse obtained through sync processing is phase-compared with the H deflection pulse input from Pin
38 to control the phase of the HDRIVE output and the horizontal position of the image projected on the CRT.
In addition, the compensation signal generated from the V sawtooth wave is superimposed, and the vertical
picture distortion is compensated.
The H deflection pulse is used to H blanking of the video signal. When the pulse input from Pin 38 has a
narrow width, the pulse generated by the IC can be added to the H deflection pulse and used as the H
blanking pulse (HBLKSW).
Pin 38 is normally pulse input, but if the pin voltage drops to the GND level, HDRIVE output stops and 1 is
output to the status register (XRAY). To release this status, turn the power off and then on again.
3) V deflection signal processing
The V sawtooth wave is generated at the cycle of the reset pulse output from the countdown system. After
performing wide deflection processing for this sawtooth wave, picture distortion adjustment is performed by the
VDRIVE and E/WDRIVE function circuits and the signal is output as the VDRIVE and E/WDRIVE signals.
4) Y signal processing
Either CVIN, input from Pin 53, or YIN, output from Pin 55, is selected by the video switch and then is passed
to the Y signal processing circuit as the Y signal. The input level is 1Vp-p.
The Y signal passes through the subcontrast control, the trap for eliminating the chroma signal, the delay line,
the sharpness control, the clamp and the black expansion circuits, and is then output to Pin 5 as YOUT. The
differential waveform of the Y signal, advanced for about 200ns from YOUT is output from Pin 49 as the VM
signal. The delay time is set by the bus register (DL).
When CVIN is selected, the trap is on; when YIN is selected, the trap is off.
The f0 of the internal filter is automatically adjusted within the IC. Because the f0 of the filter is not specified
when the color killer function is operating, turn the trap off if there are any difficulties. In addition, the f0 of the
trap will be affected slightly by variations among IC, so fine adjustment through the I2C bus (TRAP-F0) may be
required.
– 40 –
CXA2000Q
5) C signal processing
The CVBS signal or chroma signal (specified input level: burst level of 300mVp-p) selected by the video switch
passes through the ACC, TOT, chroma amplifier and demodulation circuits, becomes the R-Y and B-Y color
difference signals, and is inverted for output on Pins 3 and 4. The color difference signals are averaged
together by the external 1H delay line, and are input to Pins 7 and 8. Both color difference signals are clamped
together with the Y signal input to Pin 5. They are then combined with the G-Y signal in the color control and
axis control circuits. After Y/C mixing, the signals become the RGB signals.
If the burst level goes to –35dB or less with respect to the specified input level, the color killer operates.
In addition, the color system (PAL/NTSC) and the subcarrier frequency (4.43MHz/3.58MHz) are automatically
identified according to the input chroma signal, and the internal VCO, demodulation circuit, axis control circuit,
etc., are adjusted automatically.
Furthermore, SECAM signals can also be identified if an external SECAM decoder is connected to Pin 1. In
this case, Pins 3 and 4 and the SECAM decoder color difference output are linked together directly, and
automatically one side goes to high impedance, the other goes to low impedance according to the input
chroma signal, and then they are input to the external 1H delay line.
System identification can be set to automatic or forced mode by the I2C bus (XTAL and COLOR SW). The
color system is output to the status register (COLOR SYS).
6) RGB Signal processing
The RGB signals obtained from the Y/C block pass through the half-tone switch circuit (YM SW), the two
switch circuits for the external RGB signals (YS1, YS2 SW), the picture control, dynamic color, gamma
compensation, clamp, brightness control, drive adjustment, cut-off adjustment and auto cut-off circuits, and are
output to Pins 22, 24 and 26.
The RGB signals input to Pins 12, 13, 14, 17, 18, and 19 are 100 IRE, 100% white 0.7Vp-p signals, in
accordance with the standard for normal video signals. If signals of 1.5Vp-p or more are input to Pins 17, 18,
and 19, 67 IRE output is obtained (digital input).
The voltage applied to Pin 28 (ABLIN) is compared with the internal reference voltage, integrated by the
capacitor which is connected to Pin 29, and performs picture control and brightness control.
In order to adjust the white balance (black balance), this IC has a drive control function which adjusts the gain
between the RGB outputs and a cut-off control function which adjusts the DC level between the RGB outputs.
Both drive control and cut-off control are adjusted by the I2C bus, with the Rch fixed and the G and Bch
variable. An auto cut-off function (AKB) which forms a loop between the IC and CRT and performs adjustment
automatically has also been added. This function can compensate for changes in the CRT with time. Auto cutoff operation is as follows.
• R, G and B reference pulses for auto cut-off, shifted 1H each in the order mentioned, appear at the top of
the picture (actually, in the overscan portion). The reference pulse uses 1H in the V blanking interval, and
is output from each R, G and B output pin.
• The cathode current (Ik) of each R, G and B output is converted to a voltage and input to Pin 27.
• The voltage input to Pin 27 is compared with the reference voltage in the IC, and the current generated by
the resulting error voltage charges the capacitors connected to Pins 21, 23 and 25 for the reference pulse
interval and is held during all other interval.
• The loop functions to change the DC level of the R, G and B outputs in accordance with the capacitor pin
voltage so that the Pin 27 voltage matches the reference voltage in the IC.
The Rch for the reference voltage in the IC is fixed and the G and Bch are cut-off controlled by the I2C bus.
During G/B-CUTOFF center status, the loop functions so that the Rch for the reference pulse input to Pin 27 is
1Vp-p and the G and Bch are 0.81Vp-p.
The reference pulse timing can be varied by the I2C bus.
When AKB is not used, the IC can be set to manual cut-off mode with I2C bus settings. In this case, the DC
level of the R, G and B outputs can be varied by applying voltages independently to Pins 21, 23 and 25.
– 41 –
CXA2000Q
4. Notes on operation
Because the RGB signals and deflection signals output from the CXA2000Q are DC direct connected, the
board pattern must be designed consideration given to minimizing interference from around the power supply
and GND.
Do not separate the GND patterns for each pin; a solid earth is ideal. Locate the power supply side of the bypass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also,
locate the XTAL oscillator, ceramic oscillator and IREF resistor as near to the pin as possible, and do not wire
signal lines near this pin. Drive the Y, external Y/color difference and external RGB signals at a sufficiently low
impedance, as these signals are clamped when they are input using the capacitor connected to the input pin.
DC bias is applied to the chroma signal within the IC. Input the chroma signal with low impedance via an
external capacitor.
Use a resistor (such as a metal film resistor) with an error of less than 1% for the IREF pin.
Use a capacitor, such as an MPS (metalized polyester capacitor) with a small tan δ for SAWOSC.
When using a line frequency FH of 15625Hz for the main clock (PAL-B, G, etc.), Murata's Ceralock
CSB500F63 is recommended. This will yield a free-run frequency in the neighborhood of 15625Hz.
– 42 –
CXA2000Q
Curve Data
I2C bus data conforms to the "I2C Bus Register Initial Settings" of the Electrical Characteristics Measurement
Conditions (P. 22).
V-SIZE
V-POSITION
4.0
3.6
3.4
3.5
V [V]
V [V]
3.2
3.0
3.0
2.8
2.5
V-SIZE = 0
V-SIZE = 1F
V-SIZE = 3F
V-POSITION = 0
V-POSITION = 1F
V-POSITION = 3F
2.6
2.0
2.4
0
5
10
15
20
0
5
Time [ms]
15
20
V-LIN
3.6
3.6
3.4
3.4
3.2
3.2
V [V]
V [V]
S-CORR
3.0
2.8
3.0
2.8
S-CORR = 0
S-CORR = 7
S-CORR = F
2.6
V-LIN = 0
V-LIN = 7
V-LIN = F
2.6
2.4
2.4
0
5
10
15
20
0
5
Time [ms]
15
20
V-SCROLL
3.8
3.6
3.6
3.4
3.4
3.2
3.2
V [V]
3.8
3.0
3.0
2.8
2.8
2.6
2.6
V-ASPECT = 0
V-ASPECT = 1F
V-ASPECT = 3F
2.4
10
Time [ms]
V-ASPECT
V [V]
10
Time [ms]
V-SCROLL = 0
V-SCROLL = 1F
V-SCROLL = 3F
2.4
2.2
2.4
0
5
10
15
20
0
Time [ms]
5
10
Time [ms]
– 43 –
15
20
CXA2000Q
LO-VLIN
3.6
3.4
3.4
3.2
3.2
V [V]
V [V]
UP-VLIN
3.6
3.0
2.8
3.0
2.8
UP-VLIN = 0
UP-VLIN = 7
UP-VLIN = F
2.6
LO-VLIN = 0
LO-VLIN = 7
LO-VLIN = F
2.6
2.4
2.4
0
5
10
15
20
0
5
Time [ms]
10
15
20
Time [ms]
PIN-COMP
PIN-PHASE
4.2
4.1
4.0
4.0
3.9
3.8
V [V]
V [V]
3.8
3.6
3.7
3.6
3.4
3.5
PIN-COMP = 0
PIN-COMP = 1F
PIN-COMP = 3F
3.2
PIN-PHASE = 0
PIN-PHASE = 7
PIN-PHASE = F
3.4
3.0
3.3
0
5
10
15
20
0
5
Time [ms]
10
15
20
Time [ms]
CORNER-PIN
H-SIZE
4.2
4.8
4.0
4.4
V [V]
V [V]
3.8
4.0
3.6
3.6
3.4
CORNER-PIN = 0
CORNER-PIN = 7
CORNER-PIN = F
H-SIZE = 0
H-SIZE = 1F
H-SIZE = 3F
3.2
3.2
0
5
10
15
20
0
Time [ms]
5
10
Time [ms]
– 44 –
15
20
CXA2000Q
H-POSITION
TRAP OFF
5
5
0
4
3
Gain [dB]
Time [µs]
–5
SYNC
center
2
47 HSIN
38 AFCPIN
–15
–20
t [µsec]
1
–10
6µsec
3.58MHz
TRAP OFF = 0
4.43MHz
TRAP OFF = 0
TRAP OFF = 1
–25
12µsec
0
–30
0
2
6
4
10
8
12
14
16
1
0
3
2
DATA
5
4
6
Frequency [MHz]
SHARPNESS
DL
10
800
CVIN – YOUT delay time [ns]
700
Gain [dB]
5
0
–5
600
500
400
300
SHARPNESS = 0
SHARPNESS = 7
SHARPNESS = F
–10
200
0
2
6
4
10
8
12
0
1
2
Frequency [MHz]
3
5
4
6
7
8
DATA
PICTURE
COLOR
0
10
5
–5
Gain [dB]
Gain [dB]
0
–10
–5
–10
∗ COLOR OFF when DATA = 0
(–40dB or less)
–15
–15
–20
–20
0
10
20
30
40
50
60
70
0
DATA
10
20
30
40
DATA
– 45 –
50
60
70
CXA2000Q
SUB-COLOR
SUB-CONT
4
3
2
2
0
Gain [dB]
Gain [dB]
1
–2
0
–1
–2
–4
–3
–6
–4
0
2
4
6
8
10
12
14
16
0
2
4
6
Potential difference between Rch reference pulse level
and black level [Vp-p]
B-DRIVE, G-DRIVE
1
Gain [dB]
0
–1
–2
–3
–4
–5
10
20
30
40
14
16
50
60
70
BRIGHT
1
0.5
0
–0.5
–1.0
SUB-BRIGHT = 0
SUB-BRIGHT = 1F
SUB-BRIGHT = 3F
–1.5
0
10
20
30
DATA
40
50
60
70
DATA
GAMMA
SUB-BRIGHT
4.5
0.2
4.0
0
Rch output [V]
Potential difference between Rch reference pulse level
and black level [Vp-p]
12
DATA
2
0
10
8
DATA
–0.2
–0.4
–0.6
3.5
3.0
2.5
GAMMA = 0
GAMMA = 1
GAMMA = 2
GAMMA = 3
2.0
1.5
–0.8
0
10
20
30
40
50
60
0
70
20
40
60
80
CVIN input amplitude [IRE]
DATA
– 46 –
100
CXA2000Q
G-CUTOFF, B-CUTOFF
4.2
IKIN reference pulse voltage [V]
4.0
3.8
3.6
3.4
Gch, Bch
IK clamp level
Rch
3.2
3.0
2.8
2.6
0
2
4
6
8
10
12
14
16
DATA
AKB open loop characteristics
3.5
3.0
V [V]
2.5
2.0
1.5
1.0
Reference pulse voltage
(AKBOFF = 0)
RGBOUT black level voltage
(AKBOFF = 0, 1)
0.5
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Voltage applied to R, G and B sample-and-hold capacitance pins [V]
– 47 –
CXA2000Q
Package Outline
Unit: mm
64PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
51
0.15
20
1
1.0
+ 0.15
0.4 – 0.1
19
16.3
64
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
0.8 ± 0.2
32
+ 0.4
14.0 – 0.1
52
17.9 ± 0.4
33
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
QFP-64P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP064-P-1420-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.5g
JEDEC CODE
– 48 –