CXA2006Q Digital CCD Camera Head Amplifier Description The CXA2006Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver. 32 pin QFP (Plastic) Features • High sensitivity made possible by a high-gain AGC amplifier • Blanking function provided for the purpose of calibrating the CCD output signal black level • Regulator output pin provided for A/D converter reference voltage • Built-in GCA and AMP for amplifying video signals (chroma and line signals) from external sources • Built-in sample-and-hold circuits (for camera signals and for video signals) required by external A/D converters Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Conditions Supply voltage 14 –20 to +75 –65 to +150 VCC1, 2, 3 640 4.5 to 5 V °C °C mW V Applications Digital CCD cameras Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94X41B8X-PS CXA2006Q PIN 25 DIN 26 CLPDM GND1 SHD SHP VCC1 CCDLEVEL AGCCONT N.C. Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 16 AGCCLP 15 CLPOB 14 XRS 13 PBLK 12 OFFSET 11 VRT 10 VRB 9 VCC3 AGCCLP SH1 SH2 LPF AGC BLK CAMSH SH3 VCC2 27 COSCLP1 N.C. 28 LIN/CH 29 REF BOTTOM COSCLP2 LIN/CH SW LIN CLP AMP 30 VISH CENTER BIAS CH/CL DC 31 CENTER BIAS 32 LOUTCLP 3 4 –2– CH/CL PS 5 6 7 8 DRVOUT 2 LOUTCLP 1 PB/REC MODE SWITCHING CAM/VIDEO PBRFC DRV GCA GND3 RFCONT OFFSET SW VSHP GND2 C/V SW VI SW REF TOP CXA2006Q Pin Description Pin No. 1 Symbol (VCC1, 2, 3 = 4.75V) Pin voltage Equivalent circuit Description CAM /VIDEO Camera and video signal selector. 25µA 25µA 68k 2 1 VTH = 1.35V 3 Chroma signal and composite video signal selector. PB/REC 127 1.35V 2 High-band chroma signal and low-band chroma signal selector. 3 CH/CL 4 10k 4 27k 24k PS Power save mode. 16.25k Sampling 5 VSHP VTH = 1.32V 127 1.32V 5 2mA 10k Sample-and-hold pulse input for video. 6.25k 400µA Sampling 6 23 30 GND3 GND23 GND2 Ground. GND 100µA 200µA 66k 7 LOUTCLP 1.1k Approx. 2V 7 16k 4µA 1.27V 24k –3– 127 100k Capacitor connection for LOUTCLP which clamps the output minimum level in modes which pass the composite video signal. (Recommended value: 0.1µF) CXA2006Q Pin No. Symbol Pin voltage Equivalent circuit 100µA 8 • Camera mode (CAM) VRB – 200mV < black level < VRB + 300mV • Composite DRVOUT video mode (LIN) VRB + 100mV • Chroma mode (CH, CL) Center voltage = (VRT – VRB)/2 Description 4mA 8 127 DRVOUT 50 1.5mA Dynamic range = 2Vp-p 1.5mA 30k SW1 SW2 Mode 2.1V SW1 SW2 10p VCC3 VCC1 VCC2 0 0 CH, CL 0 1 CAM 1 0 LIN 1 1 — 0: Closed 1: Open OFFSET 9 20 27 Driver output for A/D converter capable of DC coupling. VCC Power supply. 2V regulator output. 13.75k 10 VRB Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 10 2.0V 2V 2k 10k 100µA 4V regulator output. 1.1k 3.75k 4V 11 3k 11 VRT 4.0V 20k 100µA –4– 100µA 100µA Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) CXA2006Q Pin No. Symbol Pin voltage Equivalent circuit 100µA 66k Description Controls the output offset during camera mode. 100µA 127 12 OFFSET 23k 0 to 3V 12 24k 1.1k 10k 25µA Camera signal preblanking pulse input. 25µA VTH = 1.35V 13 68k PBLK 127 13 1.35V VTH = 2.16V 14 10k 127 14 5p 100µA 200 Sampling 15 1.1k 10k 66k 15 CLPOB 1.45V 127 100µA Active: Low Camera signal sample-and-hold pulse input. 2.5mA 10.25k VTH = 1.45V Active when Low only during camera mode. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to 2V. 200 12.25k 2.16V XRS 27k 24k Active: Low When 0V: less than (VRB – 200mV) When 3.0V: greater than (VRB + 300mV) 10k –5– 29k Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier. CXA2006Q Pin No. Symbol Pin voltage Equivalent circuit Description 2k 1.1k AGC clamp capacitor. (Recommended value: 0.1µF) 16 16 AGCCLP Approx. 3V 127 50µA 2k 20µA 18 AGCCONT 0 to 3.0V AGC gain control. When 0V: 8dB (Minimum gain) When 3.0V: 38dB (Maximum gain) 4k 20k 38k 40µA 40µA 20µA 20µA 20µA 20µA 127 18 10k 200 19 DIN input CCD signal CCDLEVEL black level: approx. 2.7V Enables monitoring of the SHD output camera signal. 19 40µA 21 VTH = 2.38V Preset level sampleand-hold pulse input. 200 25k SHP 2.38V 127 21 25k 22 SHD 40µA 22 670µA 10k 200 Sampling –6– Data level sampleand-hold pulse input. CXA2006Q Pin No. Symbol Pin voltage Equivalent circuit 1.1k 1.1k VTH = 1.45V 24 Description 66k 127 24 CLPDM 1.45V 29k 85µA Clamp pulse used to clamp the dummy pixel portion of the input CCD signal. 85µA Active: Low 14k 25 26 PIN DIN 2k 90µA Black level: approx. 2.7V 127 CCD signal input. 25 26 200 36k 0.9µA 2k 1k 10k 127 29 29 LIN/CH Clamp potential during LIN mode: approx. 2.4V 2.1V LIN mode 200µA 100µA 2µA 10k During CH mode: approx. 2.7V 19k 100µA 2.7V 26k –7– CH mode Common input for the composite video signal (LIN) and high-band chroma signal (CH). CXA2006Q Pin No. Symbol Pin voltage Equivalent circuit Description 50µA 41k 50µA 31 RFCONT 0 to 3.0V 42k 127 31 50µA 0.86V 50µA 9k 10k Gain control for the low-band chroma signal (CL). When 0V: 3.5dB (Minimum gain) When 3.0V: 15.5dB (Maximum gain) 1k 127 32 7.3k 10k 100µA 32 PBRFC 100µA Low-band chroma signal (CL) input. Approx. 2.94V 46k 18k 41k –8– 10k CXA2006Q Electrical Characteristics Item Camera mode (Ta = 25°C, VCC1, 2 and 3 = 4.5V, VCC4 = OPEN) Symbol IDC LINE mode IDL Conditions Min. Typ. Max. Unit AGCCONT = 0V, open between VRT and VRB CAM/VIDEO = 3V, PB/REC = 0V, CH/CL = 0V, PS = 3V 31 46 60 Open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 0V, CH/CL = 0V, PS = 3V 19 27 36 Current consumption CH mode IDCH Open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 3V, CH/CL = 3V, PS = 3V 17 26 35 CL mode IPCL RFCONT = 0V, open between VRT and VRB CAM/VIDEO = 0V, PB/REC = 3V, CH/CL = 0V, PS = 3V 16 24 33 PS mode IDP PS = 0V 6 10 13 Maximum gain A CONT max. DIN = 1µs, 10mVp-p pulse AGCCONT = 3V 36 38 40 Minimum gain A CONT min. DIN = 1µs, 600mVp-p pulse AGCCONT = 0V — 8 10 A CON max. – A CON min. 28 30 32 1.9 2.1 2.5 AGC Range of AGC G gain variance Dynamic range maximum AGCmax. AGCCONT = 3V D CLPOUT output signal at saturation level Dynamic range minimum AGCmin. AGCCONT = 0V D CLPOUT output signal at saturation level 1.9 2.1 2.5 Offset high CAOF high VCC1, 2, 3 = 4.75V, OFFSET = 3V camera mode 560 660 — Offset low CAOF low VCC1, 2, 3 = 4.75V, OFFSET = 0V camera mode — –270 –200 VRT DC level VRTO VCC1, 2, 3 = 4.75V with a 400Ω load 3.97 4 4.03 VRB DC level VRBO VCC1, 2, 3 = 4.75V with a 400Ω load 1.9 2 2.1 VRT – VRB ∆VR VCC1, 2, 3 = 4.75V with a 400Ω load 1.9 2 2.1 Offset BLKOF BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V) –5 8.5 15 LIN mode gain LIN G LIN/CH = 3MHz, 500mVp-p, sine wave + offset voltage 8.5 9.5 10.5 CH mode gain CH G LIN/CH = 3MHz, 500mVp-p, sine wave 8.1 9.1 10.1 CL mode maximum gain RF RFCONT = 3V CONmax. 15kHz 80mVp-p sine wave 16 20.5 — CL mode minimum gain RF RFCONT = 0V CONmin. 15kHz 400mVp-p sine wave — 0.4 2 DRV REF BLK AMP GCA mA dB V –9– mV V mV dB CXA2006Q Electrical Characteristics Measurement Circuit 15 SH2 LPF 14 27 PL5 28 LIN/ CH C1 V1 0 to 4.75V 0.1µF GND2 12 LIN/CH SW LIN CLP AMP 30 VISH CH/CL DC 31 CENTER BIAS PBLK PL6 OFFSET V15 0 to 3V 32 9 MODE SWITCHING C2 0.047µF 1 2 L GND SW1 HL V7 3V GND SW2 HL V8 3V GND 6 5 4 3 VCC3 C9 4.7 µ SW6 VCC3 4.75V OFF ON C8 4.7µ LOUTCLP VSHP PBRFC VRT 11 R3 400 VRB 10 DRV GCA CH/CL AC V4 C/V SW OFFSET SW VI SW PS RFCONT 13 29 CENTER BIAS V2 0 to 3V REF TOP SW4 SW3 HL V9 3V GND R2 22 C5 0.1µ H V10 PL7 3V GND 8 7 DRVOUT ON REF BOTTOM COSCLP2 LOUTCLP SW5 PB/ REC AC V3 OFF GND GND R1 20k V13 3V GND C6 25p GND SW1 SW2 SW3 SW5 SW4 L L H H L L H L H L L L H H L L H L L H H OFF ON MODE CAM H LIN CL OFF CH L – 10 – GND XRS COSCLP1 CAM/ VIDEO GND GND GND PL4 BLK CAMSH SH3 N.C. GND CLPOB GND SH1 GND AGCCLP 26 C7 0.1µ GND SHP 16 AGCCLP GND VCC2 17 25 AGC VCC2 4.75V 18 GND DIN 19 20 GND C3 1µF V12 0 to 3V GND AC V5 PIN VCC1 4.75V PL3 21 22 GND GND3 GND GND GND C4 1µF SHD 23 24 GND N.C. PL2 GND1 CLPDM PL1 GND AGCCONT GND CCDLEVEL GND VCC1 GND POWER SAVE CXA2006Q Measurement Timing Chart 1H 2µs 1.5V PL4 (CLPOB) GND 1H 2µs 1.5V PL1 (CLPDM) GND 1.5V PL6 (PBLK) GND 1H V5 (DIN) Different for each test Equivalent to CCD signal black level V3 (CH) V4 (PBRFC) V1 + V3 (LIN) Different for each test PL2 (SHD) PL3 (SHP) PL5 (XRS) PL7 (VSHP) 2.5V GND – 11 – CXA2006Q Application Circuit V12 0 to 3V SHP VCC N.C. AGCCONT AGCCLP 26 SH1 15 SH2 LPF C7 0.1µ AGCCLP CLPOB BLK CAMSH SH3 14 27 XRS PBLK OFFSET 0 to 3V COSCLP1 N.C. 28 REF BOTTOM COSCLP2 REF TOP 13 LIN/CH LIN/CH 12 29 LIN/CH SW LIN CLP AMP 30 CENTER BIAS 9 MODE SWITCHING VCC 8 7 0.1µ 22 DRVOUT 6 5 4 3 VSHP 2 VCC3 LOUTCLP PS 1 VRB 4.7µF 32 0.047µF CAM/ VIDEO GND 10 4.7µF VRT DRV GCA CH/CL PBRFC CH/CL DC 31 PB/ REC PBRFC RFCONT 11 VISH CENTER BIAS 0 to 3V C/V SW OFFSET SW VI SW LOUTCLP GND2 GND3 GND 0.1µF GND CCDLEVEL VCC1 SHP 16 25 AGC VCC2 17 VRB VRT A/D A/D IN VSHP 3V GND GND 3V 3V GND GND 3V GND GND GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 12 – GND DIN 18 GND 1µF 19 20 GND CCD PIN 21 22 GND 23 24 1µF SHD GND1 CLPDM VCC GND SHD GND GND CLPDM GND CLPOB GND XRS GND PBLK GND CXA2006Q Description of Operation 1. Camera signal processing system Process the video signal processing pins as follows only in camera mode. <5> VSHP ... Connect to GND. <7> LOUTCLP ... Connect to GND. <29> LIN/CH ... Connect to GND. <31> RFCONT ... Connect to GND. <32> PBRFC ... Connect to GND via the capacitor (approx. 0.01µF). Operating conditions The camera signal processing system operates when PS is high, CAM/VIDEO is low, PB/REC is low and CH/CL is high, or when PS is high, CAM/VIDEO is high, PB/REC is low and CH/CL is low. Camera signal processing system timing chart (when VCC = 4.75V) Sig interval Idle transfer interval OPB interval Sig interval Precharge level CCD output Signal level SHP SHD SH1 output 2.7V [∗1] SH2 output [∗2] 2.7V SH3 output CLPDM (2µ dummy bit portion during the idle transfer interval) –N times AGC output SH3 output –SH2 output 2µs Basic black level 2.16V Black level [∗3] XRS CLPOB (2µ during the OPB interval) 2µs CAMSH output 2.16V PBLK (10µ during the idle transfer interval) 10µs BLK output CAMVISW output 2.16V [∗4] DRVOUT output [∗5] Approx. 2.65V when OFFSET = 3V Approx. 1.73V when OFFSET = 0V – 13 – CXA2006Q CDS: The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. CDSCLP: The CDSCLP stabilizes the input signal DC level, clamps (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and synchronizes the DC level ([∗1], [∗2]) of SH2 and SH3. AGC: The gain can be varied from 8 to 38dB by adjusting the AGCCONT voltage control VAGCCONT from 0 to 3V. LPF: A primary low-pass filter is installed for the purpose of eliminating unused bands and white noise and improving S/N. CAMSH: The CAMSH is used for camera signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. AGCCLP: The basic black level is set ([∗3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. The AGCCLP capacitance is connected to the AGCCLP pin. BLK: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential. ([∗4]) The signal is blanked when PBLK is low. C/VSW: When the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages are set so that the camera signal processing system operates, C/VSW conducts the BLK output (camera signal) into the DRV. In addition, when these voltages are set so that the video signal processing system operates, C/VSW conducts the VISH output (video signal) into the DRV. OFFSET SW: The OFFSET SW selects [OFFSET], [CH/CLDC] or [LOUTCLP] as the offset adjustment input pin of the DRV block and activates these pins by selecting the CAM/VIDEO, PB/REC, CH/CL and PS pin voltages. When the camera signal processing system is in camera mode, the OFFSET pin is conducted [OFFSET], allowing the camera signal offset to be adjusted. ([∗5]) When the video signal processing system is in LIN mode, the LOUTCLP pin is conducted [LOUTCLP], clamping the video composite signal at its sync level and offsetting the signal. In addition, CH/CL mode conducts the CH/CL DC [CH/CLDC], which gives center potential to the high-band chroma and low-band chroma signals of the video signal. DRV: DRV drives the external A/D. Camera and video (LIN, CH, CL modes) signals are input by switching C/VSW, and offset adjusted signals are output from DRVOUT pin. – 14 – CXA2006Q REFBOTTOM, REFTOP: REFBOTTOM and REFTOP are reference voltage source for the external A/D. They are connected to VRT and VRB of the A/D, and 2V and 4V are supplied. MODE SWITCHING: MODE SWITCHING is a mode selection block which selects camera signal system or video signal system operation by selecting high or low potentials for the CAM/VIDEO, PB/REC, CH/CL and PS pins. PS is the power save pin, and power save functions when this pin is low. 2. Video signal processing system Operating conditions The video signal processing system has three modes: LIN signal mode, CH signal mode and CL signal mode. The video signal processing system operates in LIN signal mode when PS is high, CAM/VIDEO is high, PB/REC is low and CH/CL is high, or when PS is high, CAM/VIDEO is low, PB/REC is low and CH/CL is low. The video signal processing system operates in CH signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high. The video signal processing system operates in CL signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is low, or when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high. Video signal processing system timing chart LIN mode LIN/CH input 2.4V AMP output 9.5dB 2.1V VISP DRVOUT output 2.1V – 15 – CXA2006Q LIN signal mode LINCLP: The video composite signal is input to LIN/CH pin. LINCLP expands the input dynamic range, and sync tip clamps the input signal at 2.4V to allow full input. The input level and frequency are respectively 571mVp-p (Max.) and DC is up to 7MHz. LINAMP: This is a fixed gain amplifier with a gain of 9.5dB. LIN/CHSW: LIN/CHSW switches between the LIN signal and CH (high-band chroma) signal. The signals are switched according to the mode selection. VISH: The VISH is used for video signal processing system. It is a sample-and-hold circuit which synchronizes the data read-in timing for the external A/D. VISW: VISW switches between the LIN, CH and CL low-band chroma signals for the video signal processing system. The signals are switched according to the mode selection. LOUTCLP: LOUTCLP is a clamp circuit which operates when the LIN signal is output to the DRV. The clamp potential is the sync portion, and is 2.1V. – 16 – CXA2006Q CH (high-band chroma) signal mode CENTER BIAS: The video high-band chroma signal is input to LIN/CH pin. CENTER BIAS expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 2.7V to allow full input. The input level and frequency are respectively 470mVp-p (Max.) and from 1 to 7MHz. CH/CL DC: CH/CL DC is a DC bias circuit which operates when the CH signal is output to the DRV. The DC bias potential is 3V. CH mode LIN/CH input 2.7V AMPOUT output 9.1dB 3V VISH 3V DRVOUT output – 17 – CXA2006Q CL (low-band chroma) signal mode CENTER BIAS: The video low-band chroma signal is input to PBRFC pin. CENTER BIAS expands the input dynamic range and sets a center DC bias so that the center potential of the SIN signal is 2.94V to allow full input. The input level and frequency are respectively 1490mVp-p (Max.) and DC is up to 1.5MHz. GCA: The GCA amplifier controls the gain of the CL signal input to PBRFC. The gain can be varied from 0.4 to 20.5dB by adjusting the RFCONT voltage from 0 to 3V. CH/CL DC: CH/CL DC is a DC bias circuit which operates when the CL signal is output to the DRV. The DC bias potential is 3V. CL mode 2.94V PBREC input GCAOUT output 0.4 to 20.5dB 3V VISH 3V DRVOUT output – 18 – CXA2006Q Example of Representative Characteristics CAM mode AGCCONT control supply voltage characteristics VAGCCONT vs. Gain 40 VCC = 4.5V Gain [dB] 30 VCC = 5.0V 20 10 0 0.0 1.0 2.0 3.0 VAGCCONT [V] CAM mode OFFSET control supply voltage characteristics VOFFSET vs. OFFSET VCC = 4.5V VCC = 4.75V VCC = 5.0V 700 600 500 OFFSET [mV] 400 300 200 100 0 –100 –200 –300 0.0 1.0 2.0 3.0 VOFFSET [V] CL mode RFGCA gain control supply voltage characteristics VRFCONT vs. Gain 26 Gain [dB] 20 VCC = 4.5V 10 VCC = 5.0V 0 0.0 1.0 2.0 VRFCONT [V] – 19 – 3.0 CXA2006Q CAM mode AGCCONT control temperature characteristics (VCC = 4.75V) AGCCONT vs. Gain –20°C 27°C 75°C 40 Gain [dB] 30 20 10 VCC = 4.75V 0 0.0 1.0 2.0 3.0 AGCCONT [V] CAM mode OFFSET control temperature characteristics VOFFSET vs. OFFSET 75°C 27°C –20°C 700 600 500 OFFSET [mV] 400 300 200 100 0 –100 VCC = 4.75V –200 –300 0.0 1.0 2.0 3.0 VOFFSET [V] CL mode RFGCA gain control temperature characteristics VRFCONT vs. Gain 22 –20°C 20 27°C Gain [dB] 75°C 10 VCC = 4.75V 0 –1 0.0 1.0 2.0 VRFCONT [V] – 20 – 3.0 CXA2006Q CAM mode maximum signal amplitude temperature characteristics CH mode AMP gain temperature characteristics Ta vs. Gain (CH mode) Ta vs. VOUT (camera mode) 11 2.50 2.40 minGain (in = 0.4Vp-p) 2.30 10 Gain [dB] VOUT [Vp-p] 2.20 2.10 2.00 1.90 9 1.80 1.70 VCC = 4.75V 1.60 1.50 –20 0 40 20 VCC = 4.75V 8 –20 60 0 20 60 40 Ta [°C] Ta [°C] CL mode maximum signal amplitude temperature characteristics LIN mode AMP gain temperature characteristics Ta vs. VOUT (CL mode) Ta vs. Gain (CL mode) 11 3.50 3.40 3.30 10 3.10 Gain [dB] VOUT [Vp-p] 3.20 maxGain 3.00 2.90 9 2.80 2.70 VCC = 4.75V VCC = 4.75V 2.60 2.50 –20 0 40 20 8 –20 60 0 40 20 Ta [°C] Ta [°C] – 21 – 60 CXA2006Q VRT, VRB and output DC (CAM, LIN, CH and CL modes) temperature characteristics CH mode 2nd/3rd harmonic distortion temperature characteristics Ta vs. VRT, VRB, DCOUT Ta vs. 2nd /3rd harmonic distortion –30 4.00 VRT, VRB, DCOUT [V] 3.60 3.40 CLOutDC 3.20 3.00 CHOutDC 2.80 2.60 VCC = 4.75V 2.40 LinOutDC CamOutDC (cont = 1.0V) 2.20 2nd/3rd Harmonic Distortion [dB] –35 VRT 3.80 2nd: OUT = 1.8Vp-p –40 –45 2nd: OUT = 1.4Vp-p –50 –55 3rd: OUT = 1.8Vp-p 3rd: OUT = 1.4Vp-p –60 –65 –70 f = 5MHz VCC = 4.5V –75 2.00 1.80 –20 VRB 0 40 20 –80 –20 60 20 40 60 Ta [°C] CL mode 2nd/3rd harmonic distortion temperature characteristics LIN mode 2nd/3rd harmonic distortion temperature characteristics Ta vs. 2nd/3rd harmonic distortion Ta vs. 2nd/3rd harmonic distortion –30 –30 –35 –40 2nd: IN = 800mVp-p, OUT = 1.8Vp-p –45 –50 2nd: IN = 100mVp-p, OUT = 0.6Vp-p –55 –60 –65 3rd: IN = 800mVp-p, OUT = 1.8Vp-p –70 –75 –80 –20 f = 700kHz VCC = 4.5V 3rd: IN = 100mVp-p, OUT = 0.6Vp-p 0 20 40 2nd/3rd Harmonic Distortion [dB] –35 2nd/3rd Harmonic Distortion [dB] 0 Ta [°C] 3rd: OUT = 1.8Vp-p –40 2nd: OUT = 1.8Vp-p –45 –50 –55 2nd: OUT = 1.4Vp-p 3rd: OUT = 1.4Vp-p –60 –65 –70 f = 5MHz VCC = 4.5V –75 –80 –20 60 0 20 40 Ta [°C] Ta [°C] – 22 – 60 CXA2006Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-32P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE – 23 – 0.50 8