CXA2078Q I2C Bus-Compatible Audio/Video Switch with Electronic Volume Description The CXA2078Q is an I2C programmable audio, video switch designed for set top box applications. It interfaces from digital encoder sources to TV, VCR and auxilliary scart connectors. 64 pin QFP (Plastic) Features • 3 scart independent audio/video switching (TV, VCR, AUX) • 0 to –63dB volume control with click noise reduction • 5 stereo audio inputs • I2C control with two address setting • Scart Function Switching input and output • Scart Fast Blanking for OSD • RF modulator output with Y/C mix option • On-chip +12V to +9V voltage regulator • 4 logic outputs Applications Audio/Video switch featuring I2C bus compatibility for set top box Structure Bipolar silicon monolithic IC Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Conditions • Supply voltage • Operating voltage 12 –20 to +75 –65 to +150 500 +10.7 to +12 9 ± 0.5 V °C °C mW V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97843-PS CXA2078Q VOUT8 MONO TRAP RIN4 FNC_TVB FNC_TVA LIN4 HW MUTE FBLK_IN1 DIG_GND LOG_4 LOG_3 LOG_2 DIG_VCC LOG_1 VOUT4 LTV VOUT3 RTV Pin Configuration 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VOUT2 52 32 ROUT1 FBLK_OUT 53 31 VOUT5 VOUT1 54 30 LOUT1 VCC_12V 55 29 VOUT6 VREG_9V 56 28 ROUT2 VREG_BASE 57 27 VOUT7 VIDEO_VCC 58 26 LOUT2 RIN5 59 25 AUDIO_VCC FBLK_IN2 60 24 VIN12 LIN5 61 23 BIAS_AUDIO VIN1 62 22 VIN8 FNC_VCR VIN6 FNC_AUX VIN10 VIDEO_GND VIN2 VIN9 –2– RIN3 9 10 11 12 13 14 15 16 17 18 19 LIN2 8 VIN11 7 VIN7 6 RIN2 5 ADR 4 AUDIO_GND 3 SCL 2 SDA 1 BIAS_VIDEO 20 VIN4 LIN1 21 LIN3 VIN3 64 VIN5 RIN1 63 CXA2078Q Block Diagram TYPICAL CONFIGURATION SOURCE TYPICAL LOAD OUTPUT FBLK_SW FBLK_IN1 ENC 41 Comparator Comparator FBLK_IN2 60 DIGITAL (OSD) BLUE VIN1 62 AUX BLUE VIN2 18 DIGITAL (OSD) GREEN VIN3 64 AUX GREEN VIN4 20 CVBS VIN5 DIGITAL (NO OSD) CHROMA VIN6 6 VCR CHROMA VIN7 14 22 RED AUX RED CHROMA VIN8 DIGITAL (OSD) CVBS LUMA VIN9 4 DIGITAL (NO OSD) CVBS LUMA VIN10 8 VCR CVBS LUMA VIN11 16 AUX CVBS LUMA VIN12 24 53 FBLK_OUT VIDEO SWITCH1 (TV) ×2 54 VOUT1 (BLUE) ×2 52 VOUT2 (GREEN) ×2 50 VOUT3 (RED/CHROMA) ×2 48 Mute BIAS 2 CHROMA DIGITAL (OSD) 5V 0V MODE1 MODE2 AUX TV VOUT4 (CVBS/LUMA) VIDEO SWITCH2 (VCR) (OSD = On-Screen Display) ×2 31 VOUT5 (CHROMA) ×2 29 VOUT6 (CVBS/LUMA) 27 VOUT7 (CVBS) AUX 33 VOUT8 (CVBS) RF MOD 35 TRAP 51 RTV VCR VIDEO SWITCH3 (AUX) ×2 MIX_SW ×2 Input attenuation = 6dB with 6k external resistor. RIN1 6k 63 Y/C MIXER Att. RIN2 6k 15 Att. RIN3 6k 19 Att. RIN4 6k 36 Att. RIN5 6k 59 Att. LIN1 6k 1 Att. LIN2 6k 17 Att. LIN3 6k 21 Att. LIN4 6k 39 Att. LIN5 6k 61 Att. VCC_12V 55 VREG_BASE 57 VREG_9V 56 VIDEO_VCC 58 BIAS_VIDEO 3 VIDEO_GND 9 AUDIO_VCC 25 BIAS_AUDIO 23 AUDIO_GND 13 AUDIO SWITCH1 (TV) VOLUME CONTROL & MUTE ×2 8dB step 1dB step 8dB step 1dB step TV ×2 AUDIO Z.C.D SWITCH2 (VCR) Logic ×2 49 LTV 34 MONO 32 ROUT1 RF MOD VCR 9V REG 4.05V BIAS 1 ×2 30 LOUT1 ×2 28 ROUT2 AUDIO SWITCH3 (AUX) AUX DIG_VCC 47 DIG_GND 42 SDA 11 4.5V BIAS 2 ×2 26 LOUT2 Mute BIAS 4.5V I2C INTERFACE LOGIC 38 FNC_TVA 37 FNC_TVB SCL 10 46 LOG_1 ADR 12 45 LOG_2 FNC_VCR 5 44 LOG_3 FNC_AUX 7 43 LOG_4 HW MUTE 40 P.O.D MONITOR –3– TV CXA2078Q Pin Description Pin No. Symbol 62 18 64 20 2 6 14 22 4 8 16 24 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 63 15 19 36 59 1 17 21 39 61 RIN1 RIN2 RIN3 RIN4 RIN5 LIN1 LIN2 LIN3 LIN4 LIN5 Pin voltage Equivalent circuit Description VCC = 12V VCC = 9V 14µA 62 14 Video signal inputs. Input impedance typically 120kΩ. 120k 18 22 4.6V 64 4 147 20 8 2 16 60µA 6 24 VCC = 12V 4.5V 63 1 33k 15 17 Audio signal inputs. Input impedance typically 60kΩ. 19 21 4.5V 27k 36 39 59 61 7µA VCC = 9V VCC = 12V 54 52 50 48 31 29 27 33 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 200 140µF 54 31 52 29 3.9V Video signal outputs. 50 27 48 33 280µA VCC = 9V VCC = 12V 51 32 28 49 30 26 RTV ROUT1 ROUT2 LTV LOUT1 LOUT2 33µA 22k 51 4.5V 32 28 Audio signal outputs. 20k 55 20k 49 30 33µA 26 –4– CXA2078Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC = 9V 75µA VCC = 12V 200 34 MONO 4.5V Audio mono signal output. 34 200 20k 75µA VCC = 9V VCC = 12V 14µA 11k 3 BIAS_ VIDEO 3.9V Reference Bias for video circuit. Connected to GND with capacitor. 3 200 9k VCC = 9V VCC = 12V 20k 23 BIAS_ AUDIO 4.5V Reference Bias for audio circuit. Connected to GND with capacitor. 23 20k 7µA VCC = 12V VCC = 9V 40k 37 38 FNC_TVB FNC_TVA — 37 38 20k –5– 2.7V I2C controlled output giving 0/2V. Maximum load current = 800µA CXA2078Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC = 12V 77.7k 56 VREG_9V 9V Pin connected to emitter of external regulator transistor. 56 13.5k 120µA VCC = 12V VCC = 12V 1mA 57 57 VREG_ BASE Connection to base of external regulator transistor. 9.7V 413 15p 120µA VCC = 9V 40µA 4k 10 SCL — 10 40k 10k I2C Clock Input. VIL = 1.5V (max) VIH = 3.0V (min) VCC = 9V 40µA 4k 11 SDA — 11 4.5k –6– 40k I2C Data input/output. VIL = 1.5V (max) VIH = 3.0V (min) VOL = 0.4V (max) CXA2078Q Pin No. Symbol Pin voltage Equivalent circuit Description HW MUTE: This pin is active high > 2.5V. When high, audio outputs RTV, LTV and MONO are muted. ADR: Selects the I2C address for the IC. < 1.5V = Low Add = 90H > 2.5V = High Add = 92H VCC = 12V 12 40 ADR HW MUTE 147 40 28k VCC = 12V 43 44 45 46 LOG_4 LOG_3 LOG_2 LOG_1 72k 12 — VCC = 9V 8µA 3V 43 — 40k 44 45 46 4.5k Open collector logic Pins. Maximum current sink = 1mA 7.5k VCC = 9V VCC = 12V Connection to external trap circuit. Trap components should be kept as close as possible to this pin. 1k 35 35 TRAP 3.9V 147 470µA VCC = 12V VCC = 9V 100 53 FBLK_ OUT — 100µA 53 100µA –7– Fast Blank output set by I2C, FBLK_IN1 or FBLK_IN2. High = 5.1V Low = 1.2V Connected to external emitter follower. Maximum load current = 800µA CXA2078Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC = 12V VCC = 9V 50µA 41 60 FBLK_IN1 FBLK_IN2 — Fast Blank inputs. Low = < 0.4V High = > 1.0, < 3.0 147 41 60 90µA VCC = 9V 80µA 50k 5 7 FNC_VCR FNC_AUX Function switching input (Scart pin 8). Typical levels = 0V/6V/12V 50k 5 — 7 10k –8– 100k CXA2078Q Electrical Characteristics Absolute Maximum Ratings Supply Voltage Vcc_12V Operating Conditions • Supply Voltage • Voltage Regulation • Operating Voltage Vcc_12V Vreg_9V Video_Vcc, Dig_Vcc, Audio_Vcc 12 12 to 10.7 9 ± 0.45 9 ± 0.5 9 ± 0.5 V V V (from 12V supply) V V FNC_TVA (pin 38) and FNC_TVB (pin 39) are static sensitive. Precaution should be taken (note 8 in "Notes on Operation"). Operation of the CXA2078Q using a 9V supply connected directly to the VCC_12V, Video_VCC, AUDIO_VCC and Dig_VCC pins is possible but not recommended. (The unused on-chip voltage regulator is then forced to have pins Vreg_base and Vreg_9V floating.) –9– CXA2078Q Electrical Characteristics Nominal conditions (Ta = 25°C) Item Current Consumption Symbol ICC Conditions VCC_12V = 12V, No signal, no load Video system Typ. Max. Unit 30 50 70 mA Nominal conditions (Ta = 25°C, Vcc_12V = 12V) VVPin Vout1 – 8 VVPout Vout8 (mix) VVPoutm GVv GVYC Bandwidth (except Y/C mixer) fV3dB Bandwidth of Y/C Mixer fYC3dB Input dynamic range Output dynamic range Cross talk VDRVI VDRVO Vctv S/N ratio S/NV Input Impedance ZinV Non-linearity Lin Min. Typ. Max. Unit No signal, no load (Fig.1) No signal,no load,Y/C mix inactive (Fig.1) No signal, no load, Y/C mix active (Fig.1) f = 200kHz, 0.3Vp-p input (Fig.2) f = 200kHz, 0.3Vp-p input (Fig.2) 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB (Fig. 2) 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB. No trap connected. (See note below) (Fig.2) 200kHz input (Fig.2) 200kHz, 2.5Vp-p input (Fig.2) f = 4.43MHz, 1Vp-p input (Fig.2) Ratio of 0.7Vp-p white video signal to black line noise. Weighted using CCIR 567. HPF @ 5kHz, LPF @ 5MHz. (Fig.2) 1Vrms 1kHz input through 56kΩ. Attenuation measured to calculate ZinV (Fig.3) 4.3 4.6 4.9 V 3.6 3.9 4.2 V 3.5 3.8 4.2 V 5.5 5.4 6.0 6.0 6.5 6.4 dB dB 15 20 7 15 — MHz 2.5 5.0 — — — — — — –50 Vp-p Vp-p dB — 72 — dB 94 120 –3 –0.4 Input/V Gain (except Y/C mixer) Gain of Y/C mixer Conditions MHz kΩ V2 Input pin voltage Symbol V1 Item Output pin voltage Min. (Fig.4) +3 % V1 = Pin Voltage +0.5V V2 = Pin Voltage +1V At output, non-linearity = Differential Gain DG Differential Phase DP Sync crush SC Delay of Luma over Chroma through mixer tcld V2 –1 × 100 V1 × 2 1.7Vp-p 5-step modulated staircase. (Chroma and Burst are 150mVp-p 4.43MHz) (Fig.2) as above. (Fig.2) Percentage reduction in sync pulse (0.4Vp-p), with tip at –1.2V input offset. (Fig.4) 0.4Vp-p square wave input. Input to output edge delay measured. No trap. (Fig.2) 1.5 % 1 Deg 0.2 3 % 15 40 ns Note) Input output path from Vin9 – 12 to Vout 8 through mixer has BW reduced by external stray capacitance on TRAP pin. – 10 – CXA2078Q Electrical Characteristics Audio system Unless otherwise stated: input coupling capacitor 1µF in series with 6kΩ resistor; output coupling capacitor of 10µF; load of 10kΩ. Nominal conditions (Ta = 25°C, Vcc_12V = 12V) Item Input pin voltage Gain Symbol VAPIN R/LOUT1, 2 GVA RTV, LTV GVATV MONO GVAM Audio frequency response FAF Frequency B/W FBWA1 Distortion THD Input Dynamic Range VdA Cross talk (Channel separation) VctA R/LOUT1, 2 RRA Ripple rejection RTV, LTV RRATV MONO RRAM DC Offset -R/Lout1, 2 Voff Input impedance Output Impedance Zin Zout Phase Difference Vpda S/N ratio S/NA Electronic Volume Control Fine volume attenuation AEVC step Coarse volume AEVF attenuation step Amute Mute DC Offset -RTV, LTV VoffTV Conditions Min. Typ. Max. Unit No signal, no load (Fig. 5) f = 1kHz, 1Vrms input. (Fig. 6) f = 1kHz, 1Vrms input. (Fig. 6) f = 1kHz, 1Vrms "stereo" input. (Fig. 6) 0.3Vp-p input. Output level at 30kHz with 1kHz serving as 0dB. 6kΩ removed. (Fig. 7) 0.3Vp-p input; frequency where output level is –3dB with 1kHz serving as 0dB. 6kΩ removed. No load (Fig. 7) f = 1kHz, 0.5Vrms, unweighted response; LPF @400Hz, HPF @ 80KHz. (Fig. 6) f = 1kHz (Fig. 6) f = 1kHz, 1Vrms input on one input, measure on any other audio output. (Fig.6) f = 100Hz, 0.3Vp-p applied to Vcc_aud (Fig. 8) f = 100Hz, 0.3Vp-p applied to Vcc_aud (Fig. 8) f = 100Hz, 0.3Vp-p applied to Vcc_aud (Fig. 8) Offset voltage between any audio input and R/Lout1, 2 (Fig. 5) (excluding series external 6kΩ) (excluding any external series resistor) f = 1kHz, 1Vrms input to two channels. Phase difference of stereo output measured f = 1kHz, 1Vrms input (at maximum volume). HPF @ 20Hz, LPF @ 20kHz. (Fig. 6) 4.2 –0.5 –0.65 –0.65 4.5 0 0 0 4.8 +0.5 +0.35 +0.45 V dB dB dB –0.3 0 +0.3 dB — 1 — MHz — 0.004 0.2 % 2 — — Vrms — –88 –76 dB — –62 — dB — –75 — dB — –44 — dB –30 +2 +30 mV 48 — 60 10 72 — kΩ Ω — 0.05 — Deg 72 95 — dB 0.6 1 1.4 dB 7.5 8 8.5 dB f = 1kHz, 0.5Vrms input. Set by I2C (Fig.6) f = 1kHz, 0.5Vrms input. Set by I2C (Fig.6) f = 1kHz, 1Vrms input. (Fig.6) Offset voltage between any audio input and RTV, LTV outputs (Fig.5) – 11 – >80 –30 +2 dB +30 mV CXA2078Q 1k BC547B 47µH +9V 25pF 1k Trap Switch SW1 1k +12V BC547B +12V BC547B +12V Measurement Point 1k 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BC547B 1k +12V 1k +12V 32 52 BC547B +12V BC547B +9V +9V 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B +9V 22µF 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 47µF Measurement Point Fig. 1. Video system (d.c.test) Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests. 3. Voltage measurements carried out with a high input impedance DVM. Typically 10GΩ. – 12 – CXA2078Q +12V 1k BC547B +9V +12V 47µH BC547B BC547B +12V 25pF 1k Trap Switch SW1 1k Measurement Point 1k 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BC547B 1k +12V 1k +12V +12V BC547B +9V +9V 75 75 32 52 BC547B 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 2.2µF 61 62 23 2.2µF 63 64 21 1k +12V BC547B 1k +12V BC547B 1k +9V 2.2µF 75 BC547B +12V 22µF 22 2.2µF 75 20 2.2µF SCL SDA 2.2µF 9 10 11 12 13 14 15 16 17 18 19 2.2µF 8 75 75 7 2.2µF 47µF 6 75 5 2.2µF 2.2µF 2.2µF 75 4 75 75 3 2.2µF 2 75 1 75 Input Signal Fig. 2. Video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, signal to noise, Luma-Chroma delay) Signal applied to Pins 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 Output Signal Measured from pins 27, 29, 31, 33, 48, 50, 52, 54 Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. For tests requiring video measuring equipment with 75Ω input impedance, an external video line driver or buffer is used. 3. For bandwidth tests through Y/C mixer, the trap circuit is switched out using SW1. 4. All video outputs are loaded with emitter follower during tests. 5. For Luma and Chroma input to output delay, measure signal at the I.C. pins. – 13 – CXA2078Q +9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 56k 2.2µF 61 62 23 56k 2.2µF 63 64 20 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA Signal Input Measurement Point Fig. 3. Video system (input impedance) Signal applied and measured from pins, 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. Voltage measurements carried out with a high input impedance DVM. Typically 10GΩ. – 14 – 56k 2.2µF 47µF 3 56k 2.2µF 2 56k 2.2µF 1 56k 2.2µF 2.2µF 22µF 21 56k 56k +9V 22 56k 2.2µF 2.2µF +9V 56k 2.2µF +9V 56k 2.2µF BC547B 32 53 56k 2.2µF +12V 52 CXA2078Q 1k BC547B +9V 25pF 1k Trap Switch SW1 1k +12V Measurement Point 1k 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BC547B 1k +12V 32 52 BC547B +12V 47µH BC547B +12V BC547B +12V 1k +12V BC547B +9V +9V 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B +9V 22µF 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 47µF PSU Input Signal Fig. 4. Video system (linearity, sync crush) Signal applied to Pins, 2, 4, 6, 8, 14, 16, 18, 20, 22, 24, 62, 64 Output Signal Measured from pins 27, 29, 31, 33, 48, 50, 52, 54 Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests. – 15 – CXA2078Q Output Measurement Point +9V HW mute +9V SW1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 52 +12V BC547B +9V +9V 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 47µF 5 6 7 8 +9V 22µF 9 10 11 12 13 14 15 16 17 18 19 SCL SDA Input Measurement Point Fig. 5. Audio system (d.c. tests) Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. Voltage measurements carried out with a high input impedance DVM. Typically 10GΩ. – 16 – Measurement Point 10µF 10k +9V 6k 1µF 600 HW SW1 mute 10µF 10k 10µF 10k +9V 6k 1µF 600 CXA2078Q 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10µF 10k 32 52 +12V BC547B +9V +9V 600 1µF 6k 53 31 10µF 10k 54 30 55 29 10µF 10k 28 56 57 27 10µF 10k 26 58 59 25 600 1µF 6k 60 24 61 23 600 1µF 6k 62 22 63 21 64 20 1 6k 1µF 2 3 4 5 6 7 8 +9V 22µF 6k 1µF 600 9 10 11 12 13 14 15 16 17 18 19 47µF SCL SDA 600 6k 6k 6k 1µF 1µF 1µF 600 600 600 Input Signal Fig. 6. Audio system (gain, dynamic range, Signal to noise, Crosstalk, Distortion, Volume control) Signal applied to Pins, 63, 1, 59, 61, 15, 17, 19, 21, 36, 39 Output Signal Measured from pins 26, 28, 30, 32, 34, 49, 51 Notes) 1. All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. 2. When muting audio using Hardware mute, SW1 is closed. – 17 – Measurement Point 10µF 10k 10µF 10k 10µF 10k +9V 1µF 600 +9V HW SW1 mute 1µF 600 CXA2078Q 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10µF 10k 32 52 +12V BC547B +9V +9V 1µF 600 600 1µF 600 1µF 53 31 10µF 10k 54 30 55 29 10µF 10k 28 56 57 27 10µF 10k 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 5 4 6 7 8 +9V 22µF 1µF 9 10 11 12 13 14 15 16 17 18 19 47µF 1µF SCL SDA 600 1µF 1µF 1µF 600 600 600 Input Signal Fig. 7. Audio system (Bandwidth) Signal applied to Pins, 63, 1, 59, 61, 15, 17, 19, 21, 36, 39 Output Signal Measured from pins 26, 28, 30, 32, 34, 49, 51 Note) All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. – 18 – 600 Measurement Point 10µF 10k +9V 6k 1µF 10µF 10k 10µF 10k HW SW1 mute 6k 1µF 600 +9V 600 CXA2078Q 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10µF 10k +12V 52 32 53 31 10µF 10k 30 54 55 BC547B +9V 29 10µF 10k 28 56 57 +9V 58 6001µF 6k 59 27 10µF 10k 26 25 600 1µF 6k 60 +9V 24 100Hz 0.3Vp-p 61 23 600 1µF 6k 62 22 63 21 64 20 1 6k 1µF 2 3 4 5 6 7 8 22µF 6k 1µF 9 10 11 12 13 14 15 16 17 18 19 47µF SCL SDA 600 6k 6k 6k 1µF 1µF 1µF 600 600 600 Fig. 8. Audio system (Ripple Rejection) Output Signal Measured from pins 26, 28, 30, 32, 34, 49, 51 Note) All +9V supplies de-coupled close to supply pins, 25, 47, 58 with 10nF ceramic capacitor. – 19 – 600 2 4 6 8 10 12 14 16 18 1 3 5 7 9 11 13 15 17 19 R L 47µ +12V BC547B 75 75 75 75 5×1k 1µ 1µ 0.47µ 4.7µ 10nF VOUT2 RIN5 1µ 47µ ENCODER 0.47µ 0.47µ 0.47µ 0.47µ 0.47µ 9 8 43 7 44 6 45 46 5 47 10k 4 48 10k 3 49 10k 2 50 600 10µ 4.7µ 10k 10nF 9V_REG 1 1µ 64 63 62 61 6k VIN3 RIN1 VIN1 LIN5 60 59 58 57 56 55 54 53 52 51 600 10µ 6k 6k FBLK_IN2 6k VIDEO_VCC VREG_BASE VREG_9V VCC_12V VOUT1 FBLK_OUT BC547B BC547B BC547B BC547B 20 +12V RTV LIN1 BC547B 75 VOUT3 VIN5 21 LTV BIAS_VIDEO 1k 10 I2C CXA2078Q 42 75 +12V 11 41 6k 6k 10k 0.47µ 1µ 0.47µ 1µ 6k 1µ 0.47µ 75 19 18 33 17 34 16 35 15 36 37 47µH 27pF 1k 14 38 6k 1µ AUDIO4_R 2.2k 10k TO MODULATOR 13 10k 2.2k 10k 50 1k BC547B 12 39 40 6k 1µ AUDIO4_L HW_MUTE HW MUTE T. V. SCART VOUT4 VIN9 AUDIO 5 DIG_VCC FNC_VCR LOG_1 VIN6 LOG_2 FNC_AUX LIN4 ADR LOG_3 VIN10 FNC_TVA AUDIO_GND FNC_TVB VIN7 RIN4 RIN2 LOG_4 VIDEO_GND TRAP VIN11 DIG_GND SCL MONO LIN2 FBLK_IN1 SDA VOUT8 VIN2 – 20 – RIN3 Typical Application Circuit 20 21 22 23 24 25 26 27 28 29 30 31 32 10µ 10µ 10µ 0.47µ VIN4 LIN3 VIN8 75 0.47µ 6k 0.47µ BIAS_AUDIO VIN12 AUDIO_VCC LOUT2 VOUT7 ROUT2 VOUT6 LOUT1 VOUT5 ROUT1 10µ 1µ 22µ 75 75 1k BC547B 1k 75 +12V 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 21 AUX SCART 1k +12V 75 BC547B 1 3 5 7 9 11 13 15 17 19 21 BC547B 2 4 6 8 10 12 14 16 9V_REG 10nF 4.7µ 600 600 600 600 VCR SCART 20 18 75 75 CXA2078Q CXA2078Q Description of operation 1. Explanation of Video Section The video section comprises of 12 high impedance (120kΩ) inputs switched through to 8 video outputs. A +6dB internal amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation which occurs at the external emitter follower stage used for driving video loads. The typical external configuration is shown in Fig. 1-1. A Y/C mixer can be used for mixing Luma and Chroma signals for use with an external RF modulator connected to Vout8. The Y/C mixer is controllable via the I2C data bus. The circuit is shown in Fig. 1-2 with a trap circuit used to give 3dB attenuation at 4.43MHz of the Luma signal. Video_VCC = 9V VCC = 12V SCART_in Switch 75Ω BC547B Vin SCART_out Vout AMP 0.47µ beta = 250 120kΩ 75Ω Load Vbias 75Ω 1kΩ 75Ω Vbias Video element Fig. 1-1. Video circuit element: 6dB gain amplifier with external emitter follower R/C CVBS/Y Vout3 6dB Vout4 6dB 1kΩ 1kΩ 6.5kΩ 0dB Vout8 6dB 147Ω 6.5kΩ 0dB TRAP 1kΩ 47µF 25pF Fig. 1-2. Y/C MIXER Circuit – 21 – CXA2078Q 2. Explanation of Audio System. Audio Switch and Amplifier The audio system consists of 5 stereo inputs, 3 stereo outputs and a mono output. Each output can be independently connected to any one of five inputs, Lin1 to Lin5 for the left stereo audio channel, and Rin1 to Rin5 for the right hand audio channel. In all cases, the input to the switch and amplifier is composed of a potential divider consisting of a 27kΩ series resistor and a 33kΩ connected to a voltage source (4.5V). When used in conjunction with an external 6kΩ series input resistor, the input configuration forms a –6dB attenuator (Fig. 2-1). The net gain of the audio system is zero as there is an internal +6dB amplifier on each output. The output impedance of the audio amplifier is near zero, and is used to drive the external SCART circuit. The output is capacitively coupled through a 10µF capacitor, and an optional 600Ω series compliance resistor. Depending on the length and type of cable used in the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pF to 400pF) and mandatory 10kΩ resistor connected to ground (Fig. 2-2). The customer may chose to place an alternative audio output filter at the AV switch output. TV audio output The TV audio section is composed of an audio switch and 0dB amplifier followed by two variable gain stages, corresponding to the course and fine electronic volume control amplifiers, EVC and EVF. The EVC amplifier attenuates the input signal in steps of 8dB. A range of attenuation from 0dB to 56dB can be programmed by means of the I2C interface. Similarly, the fine volume control (EVF) can be programmed to provide a range of attenuations between 0dB and 7dB. The attenuated signal is passed through to the output buffer stage which provides the necessary +6dB gain, and is used to drive the SCART connector. The final output buffer can also act as a –80dB (mute) amplifier (Fig. 2-4). Zero Cross Detector (ZCD) The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. The change volume or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. The zero cross detection circuit can be turned off by setting the "ZCD" bit low in the I2C write mode. The status of the zero cross detector can be checked in the I2C read mode (Z.C status). When this bit is high, a zero cross condition has been detected subsequent to the issue of an I2C volume change or mute instruction. This may be useful if the input waveform is very low frequency, whereupon the microprocessor can re-issue the same instruction, with the zero cross detector circuit switched off. I2C Mute The mute instruction in the I2C format refers to the TV audio circuit. Audio mute can be implemented after a audio zero cross detection, or immediately depending on whether ZCD = 1 or 0. It can be seen from the I2C write format that the same mute bit occurs in DATA1 and DATA5. This allows the software to action an immediate mute, make any suitable changes to the audio source or electronic volume control and after a minimum period of 4 × 90µs (360µs) un-mute the output buffer. Such a period provides ample time to allow any transient ac voltages to settle during an audio source change. – 22 – CXA2078Q 1µF Audio in R/L in 6kΩ (external) 600Ω 10µF ATT = –6dB SCART Audio out 600 27kΩ 400pF (external) 33kΩ Terminal 10kΩ (internal) 4.5V Fig. 2-2. Audio output configuration Fig. 2-1. Audio input configuration –6dB R/L in R/L in R/L in R/L in R/L in ATT ATT ATT ATT ATT +6dB Audio output Mute 4.5V Fig. 2-3. VCR and AUX audio configuration I2C Registers ATT ATT ATT ATT ATT 0dB 0 to –56dB EVC 0 to –7dB EVF Audio Switch +6dB Mute (–80dB) Mute Zero Cross Detect TV Audio Output to control logic Fig. 2-4. T.V. audio section and Electronic Volume Control – 23 – CXA2078Q I2C Interface Data Format IC Control Data Format S Slave address A DATA1 S: Start condition A DATA2 A: Acknowledge A DATA3 A DATA4 A DATA5 A P: Stop condition There are two possible addresses depending on external address pin (12) tied high or low. Pin 12 = high, Address = 92 Hex Ao = 1 Pin 12 = low, Address = 90 Hex Ao = 0 General I2C data structure (write mode) Address b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 Ao (W) 0 TVMute Z.C.D Data1 EVF EVC Data2 FBLK Vid_Sw1 (TV) Aud_Sw1 (TV) Data3 FNC Vid_Sw2 (VCR) Aud_Sw2 (VCR) Vid_Sw3 (AUX) Aud_Sw3 (AUX) Data4 Y/C Mix x Data5 TVMute x Key EVC: EVF: TVMute: Z.C.D: Vid_Sw1: Vid_Sw2: Vid_Sw3: Aud_Sw1: Aud_Sw2: Aud_Sw3: FNC: FBLK: Y/C Mix: LOG1-LOG4: x x LOG4 LOG3 LOG2 Electronic Volume Course (8dB steps) Electronic Volume Fine (1dB steps) TV Audio mute. Controls the TV audio output buffer. (Same bit appears in data 1 & 5) Zero cross detector active. When ZCD = 1 volume and mute change at zero cross. Selects the input video sources for Vout1, Vout2, Vout3, Vout4 Selects the input video sources for Vout5, Vout6 Selects the input video sources for Vout7 Selects one of 5 stereo inputs for RTV, LTV Selects one of 5 stereo inputs for Rout1, Lout1 Selects one of 5 stereo inputs for Rout2, Lout2 Video function switch control Video Fast Blanking control When Y/C Mix = 1 converts Y/C input to CVBS for output through Vout8 Logic outputs (open collector). 0 = high impedance. 1 = current sink mode. – 24 – LOG1 P CXA2078Q General I2C data structure (read mode) S Slave address A DATA6 NA P NA: No Acknowledge DATA STRUCTURE b7 b6 b5 b4 b3 b2 b1 b0 Slave Address 1 0 0 1 0 0 X (R) 1 Data6 x x ZC STATUS P.O.D. FUNC_VCR: FUNC_AUX: ZC Status: P.O.D.: FUNC_AUX FUNC_VCR At pin 5 AV switch monitors the voltage of pin 8 from VCR scart, and records status. At pin 7 AV switch monitors the voltage of pin 8 from AUX scart, and records status. ZC Status = 1 indicates that zero cross condition has been achieved after a volume or mute instruction issued. Power On Detect. P.O.D. = 1 when DIG_VCC voltage rises above a threshold level of approximately 5V. – 25 – CXA2078Q 3. Video Input I2C Control 3-1. Video Switch 1 (Vid_Sw1) – TV Output Vout1 Vout2 Vout3 Vout4 B G/CVBS/Y R/C CVBS/Y Comment d2_b5 d2_b4 d2_b3 0 0 0 Vin1 Vin3 Vin5 Vin9 Digital encoder 0 0 1 Vbias Vbias Vin6 Vin10 Digital encoder 0 1 0 Vbias Vbias Vin7 Vin11 VCR 0 1 1 Vin2 Vin4 Vin8 Vin12 Aux 1 0 0 Vbias Vbias Vin5 Vin3 Digital encoder 1 0 1 Vin1 Vin3 Vin5 Vin10 Digital encoder 1 1 0 Vin1 Vin3 Vin5 Vin11 Digital encoder 1 1 1 Vbias Vbias Vbias Vbias Video Mute Table 3-1. showing which video input pins connect to the four TV output pins 3-2. Video Switch 2 (Vid_Sw2) – VCR Output Vout5 Vout6 Chroma (C) CVBS/Y Comment d3_b5 d3_b4 d3_b3 0 0 0 Vin5 Vin9 Digital encoder 0 0 1 Vin6 Vin10 Digital encoder 0 1 0 Vin7 Vin11 VCR 0 1 1 Vin8 Vin12 Aux 1 0 0 Vin5 Vin3 Digital encoder 1 0 1 Vbias Vbias Video Mute 1 1 0 Vbias Vbias Video Mute 1 1 1 Vbias Vbias Video Mute Table 3-2. showing which video input pins connect to the two VCR output pins – 26 – CXA2078Q 3-3. Video Switch 3 (Vid_Sw3) – AUX Output Vout7 Comment CVBS d4_b5 d4_b4 d4_b3 0 0 0 Vin9 Digital encoder 0 0 1 Vbias Video Mute 0 1 0 Vin11 VCR 0 1 1 Vin12 Aux 1 0 0 Vin3 Digital encoder 1 0 1 Vbias Video Mute 1 1 0 Vbias Video Mute 1 1 1 Vbias Video Mute Table 3-3. showing which video input pins connect to the single AUX output pin – 27 – CXA2078Q 4. Fast Blanking operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to impose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode 2. RGB mode Scart pin voltage = 0 to 0.4V Scart pin voltage = 1 to 3.0V Threshold voltage is approximately 0.75V DC voltage at scart input. The blanking information is usually generated by the same source as that producing the RGB signal. I2C Control In the CXA2078Q, there are two fast blanking inputs, one associated with the auxiliary RGB/CVBS inputs and another associated with Digital Encoder input. These can be selected by I2C. In addition to the two blanking inputs, the fast blank pin output can be set to a constant 0V or 5V by means of the I2C control. Hence there are four possible states. These are controlled according to the following table. FBLK d2_b7 d2_b6 0 0 FBLK_OUT (pin 53) 0V∗1 0 1 5V 1 0 same state as FBLK_IN1 (0/5V) 1 1 same state as FBLK_IN2 (0/5V) ∗1 Default = 0V at power up – 28 – CXA2078Q 5. Function switch, FNC. The function switch facility is designed to read the status of the SCART function pin 8 from the VCR and AUX inputs (IC pin 5, 7). The output function pins FNC_TVA and FNC_TVB are controlled from the IC using a write instruction. A suitable interface circuit (fig 5-2) will allow FNC_TVA and FNC_TVB to instruct the TV to switch between display modes. Read Mode DATA STRUCTURE Slave Address b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 X (R) 1 Z.C STATUS P.O.D. Data6 FUNC_AUX FUNC_VCR Read mode Status of I2C registers as a function of the voltage on FNC_AUX (pin 7) and FNC_VCR (pin 5) Input Pin Voltage read data6 FNC_AUX or FNC_VCR Level (SCART Defn) b3/b1 b2/b0 0V to +2V (default) (Internal TV) 0 0 +4.5 to +7V (16:9 External) 0 1 +9.5 to +12V (4:3 External) 1 1 Write mode TV Function switch, Interface table d3_b7 d3_b6 FNC_TVA Pin voltage FNC_TVB Pin voltage Comment 0 0 2V 2V Internal TV (default) 0 1 0V 2V External 16:9 1 0 0V 0V External 4:3 1 1 0V 0V External 4:3 Default is Internal TV (0, 0) at power up – 29 – CXA2078Q The two function output pins are controlled via logic to swing from 0 to +2V. 2V FNC_TVA (38) < 0.4V 2V Logic Drive Circuit < 0.4V FNC_TVB (37) Mux d3_b7 d3_b6 Fig. 5-1. TV Function switch output Some external circuitry is required to interface from the IC pins to the SCART pin 8. A typical interface circuit is shown in Fig. 5-2. 12V 1kΩ TV scart pin 8 FNC_TVA 1kΩ FNC_TVB 2.2kΩ 50Ω 2.2kΩ CXA2078Q Fig. 5-2. External circuit for function switch – 30 – CXA2078Q 6. Logic outputs I2C control of logic outputs achieved using bits LOG1 – 4. Specification I2C bit 0 = open collector/high output impedance on logic pin I2C bit 1 = current sink mode resulting in 0.2V saturation voltage on logic pin Vmax at logic pin = 12V Imax during current sink = 1mA VCC = 9V 10kΩ 10kΩ 10kΩ LOG_1 LOG_2 LOG_3 LOG_4 d5_b3 d5_b2 d5_b1 Logic Logic cct. cct. d5_b0 Fig. 6-1. Open collector logic outputs – 31 – 10kΩ External resistors CXA2078Q 7. I2C Audio Signal Control I2C Audio input select using Aud_Sw1 (TV), Aud_Sw2 (VCR), Aud_Sw3 (AUX) b2 b1 b0 RTV, ROUT1, ROUT2 LTV, LOUT1, LOUT2 0 0 0 Rin1 Lin1 0 0 1 Rin2 Lin2 0 1 0 Rin3 Lin3 0 1 1 Rin4 Lin4 1 0 0 Rin5 Lin5 1 0 1 Audio mute Audio mute 1 1 0 Audio mute Audio mute 1 1 1 Audio mute Audio mute I2C Electronic Volume control (coarse) DATA 1, EVC b7 b6 b5 Gain (dB) 0 0 0 0 0 0 1 –8 0 1 0 –16 0 1 1 –24 1 0 0 –32 1 0 1 –40 1 1 0 –48 1 1 1 –56 I2C Electronic Volume control (fine) DATA 1, EVF b4 b3 b2 Gain (dB) 0 0 0 0 0 0 1 –1 0 1 0 –2 0 1 1 –3 1 0 0 –4 1 0 1 –5 1 1 0 –6 1 1 1 –7 – 32 – CXA2078Q I2C Mute function TV Mute DATA1 b1 DATA5 b7 Z.C.D DATA1 b0 0 0 Un-mute immediately 0 1 Un-mute on next zero cross 1 0 Mute immediately 1 1 Mute on the next zero cross RTV, LTV, MONO output Notes on operation 1) Supply de-coupling capacitors, 10nF and 4.7µF in parallel should be inserted as close to the supply pins, 25, 47, 58 as possible. 2) To minimise crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) The trap components on pin 35 should be kept as close to the IC as possible to minimise parasitic capacitance to ground. 4) Attention should be given to the electrolytic capacitors on the input and output signal pins. As the pin's voltage is between 3.7V and 4.7V dc the positive terminal on the capacitor should be orientated towards the pin. 5) The audio outputs may be muted at any time after power up by connecting the HW MUTE pin (40) to a voltage > 2.5V and < 9V. 6) The I2C address of the IC can be changed using the ADR pin (12). By connecting this pin to >5V and <9V the Address changes from 90H to 92H. 7) When driving video loads with impedance = 75Ω an emitter follower or video line driver is required to be connected at the video outputs. Stray capacitance on pins Vout1-8 must be kept to a minimum by placing loads as close to the pins as possible. 8) As shown on the application schematic, static protection for pins 38 and 37 may typically be achieved using Zener diodes. Diodes with a Zener voltage > 5V are suitable. – 33 – CXA2078Q Typical audio output distortion Input = 1kHz, 400Hz – 80kHz BPF THD [%] 1 0.1 0.01 0.001 0 1 2 Input [Vrms] 3 3.66 Audio frequency characteristics Audio input/output gain [dB] 4 2 0 –2 Input = 0.3Vp-p –4 –6 100 1k 10k Frequency [Hz] 100k 1M NOTE: Audio input 6kΩ resistor removed for this test. Video frequency characteristics Video input/output gain [dB] 8 VOUT1-8 (MIX = OFF) 6 4 VOUT8 (MIX = ON) 2 0 Input = 0.3Vp-p 100k 1M 10M Frequency [Hz] – 34 – 50M CXA2078Q Package Outline Unit: mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 51 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 0.8 ± 0.2 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP–64P–L01 LEAD TREATMENT EIAJ CODE QFP064–P–1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 35 –