CXA2096N Digital CCD Camera Head Amplifier Description The CXA2096N is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, A/D sample and hold, blanking, A/D reference voltage, and an output driver. 24 pin SSOP (Plastic) Features • High sensitivity made possible by a high-gain AGC amplifier • Blanking function provided for the purpose of calibrating the CCD output signal black level • Regulator output pin provided for A/D converter reference voltage • Built-in sample-and-hold circuits for camera signals required by external A/D converters Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation VCC Topr Tstg PD Operating Conditions Supply voltage VCC1, 2, 3 3.0 to 3.6 11 –20 to +75 –65 to +150 417 V °C °C mW V Applications DVC/still cameras for consumer use Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97449B8Y CXA2096N ICONT VCC2 DIN PIN CLPDM GND1 SHD SHP VCC1 CCDLEVEL AGCCONT AGCCLP Block Diagram and Pin Configuration 24 23 22 21 20 19 18 17 16 15 14 13 BUF SH1 SH2 DC SHIFT AGC CDS CLP2 DMSW2 OB SW SH3 AGC CLP VREF CAM SH DMSW1 VRT DRV OFFSET CDS CLP1 VRT BLK SW POWER SAVE CONT VRB DRV DRV PS GND3 DRVOUT VCC3 N.C. 7 8 9 10 11 12 CLPOB 6 XRS 5 PBLK 4 OFFSET 3 VRT 2 VRB 1 GND2 VRB –2– CXA2096N Pin Description Pin No. Symbol 1 3 19 GND2 GND3 GND1 (VCC1, 2, 3 = 3V) Pin voltage Equivalent circuit Description Ground. GND 60k 1.5V 30k 145 2 PS 2 VTH = 1.5V Power saving mode. 10µA IOFFSET 25µA 200µA 5k 25µA 0 to 50µA 2k VRB = 1.35V 4 DRVOUT 50µA VRB to VRB + 100mV 50µA Driver output for A/D converter capable of DC coupling. ICONT 3.2 to 6.4mA Dynamic range = 1Vp-p. 145 4 CAM signal 48 5 16 23 VCC3 VCC1 VCC2 VCC Power supply. –3– CXA2096N Pin No. 6 Symbol Pin voltage Equivalent circuit Description No connection; normally ground. N.C. 1.35V regulator output. 200 16.5k Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 145 7 VRB 1.35V 1.35V 7 13.5k 110µA 30k 2.35V regulator output. 30k 6.5k 145 2.35V 8 VRT 8 2.35V 23.5k 200 55µ 55µ 220µ 50k 50k 30k 9 OFFSET 1.5 to 3V & 0V Controls the output offset. 2k 1.85V 1.5k 3k 25k VRB 30k 50µA 145 50µA 9 50µA 30k 145 1.85V PBLK Active: Low 10 30k 50µA –4– When 3V: VRB When 1.5V: VRB + 100mV When 0V (preset mode): VRB + 35mV Camera signal preblanking pulse input. 30k VTH = 1.85V 10 Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) Active when Low. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to VRB. CXA2096N Pin No. Symbol Pin voltage Equivalent circuit 770µA 40µA VTH = 0.68V Description 24k 145 11 11 XRS 0.68V Camera signal sample-and-hold pulse input. 7k Sampling 97µ 30k VTH = 1.5V Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier. 30k 145 12 1.5V CLPOB 12 30k 50µA Active: Low 5k 3k 5k 145 13 AGCCLP 13 Approx. 1.3V 145 AGC clamp capacitor. (Recommended value: 0.1µF) 50k 3k 3.3k AGC gain control. 3.3k 145 14 14 AGCCONT 1.5 to 3.0V 3.4k 3.4k 2.14V ICONT 300µA 100µA 300µA 100µA –5– 3.4k 200µA 2.29V 200µA 3.4k When 1.5V: –1dB (Minimum gain) When 3.0V: 31.5dB (Maximum gain) CXA2096N Pin No. Symbol Pin voltage Equivalent circuit Description 100µA 15 CCD signal black level of CCDLEVEL DIN input approx. 2.2V Enables monitoring of the SH3 output camera signal. 15 500 340 17 VTH = 0.65V Preset level sampleand-hold pulse input. 365µA 20µA SHP 36k 145 17 18 0.65V 18 SHD 30k VTH = 1.5V 20 Data level sampleand-hold pulse input. 10k Sampling Clamp pulse used to clamp the dummy pixel portion of the input CCD signal. 145 1.5V CLPDM 20 30k 50µA Active: Low 15µA 15µA 145 21 21 22 PIN DIN Black level approx. 2.1V 22 145 2k CCD signal input. 23k 14k 200µA 7k 2k 50µA DRVOUT output waveform rise time control. 15k 145 2.25V 24 ICONT 24 1.5 to 3V 6k 6k 45k 100µA –6– When 1.5V: Maximum rise time When 3V: Minimum rise time CXA2096N Electrical Characteristics Item Symbol PS = OFF Current (PS indicates IDC consump Power Save) -tion PS = ON IDP AGC (Ta = 25°C, VCC1, 2, 3 = 3V) Conditions Min. Typ. Max. Unit AGCCONT = 1.5V, open between VRT and VRB PS = 3V, ICONT = 3V 25.1 37.1 49.0 0 1.8 4.2 28.5 31.3 — — –0.8 1.4 27.1 32.1 — 800 970 — PS = 0V Maximum gain A CONT max. DIN = 1µs, 20mVp-p pulse AGCCONT = 3V, ICONT = 3V Minimum gain A CONT min. DIN = 1µs, 500mVp-p pulse AGCCONT = 1.5V, ICONT = 3V Range of gain AGC G variance A CON max. – A CON min. mA dB Dynamic range maximum AGCmax. AGCCONT = 3V D DRVOUT output signal at saturation level Dynamic range typical AGCTYP. D AGCCONT = 2V DRVOUT output signal at saturation level 900 960 — Offset high CAOF high OFFSET = 1.5V 80 98 — Offset low CAOF low OFFSET = 3.0V — 2 5 Offset preset CAOF pre OFFSET = 0V 25 34 40 VRT DC level VRTO With a 400Ω load 2300 2340 2400 VRB DC level VRBO With a 400Ω load 1300 1353 1400 VRT – VRG ∆VR With a 400Ω load 950 988 1050 BLK Offset BLKOF BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V) –15 9 30 mV SH3 Dynamic range SH3 D DIN = 1µs, 1Vp-p pulse 600 790 — mV DRV REF mV –7– mV mV CXA2096N Electrical Characteristics Measurement Circuit 23 24 19 20 18 17 15 16 14 C3 0.1µF AGCCLP AGCCONT VCC1 SHP SHD GND1 PIN 21 22 V3 1.5 to 3V PL3 VCC1 3V C2 1µF DIN VCC2 C1 1µF PL2 CLPDM VCC2 3V ICONT V1 1.5 to 3V PL1 CCDLEVEL AC V2 13 BUF SH1 SH2 DC SHIFT AGC OB SW SH3 CDS CLP2 DMSW2 AGC CLP VREF CAM SH DMSW1 VRT DRV OFFSET CDS CLP1 VRT VRB DRV BLK SW POWER SAVE CONT V5 1.85V SW1 POWER SAVE H OFF L ON VRT VRB N.C. VCC3 C5 4.7µ C6 40pF –8– C4 4.7µ V4 0 to 3V 11 12 CLPOB R3 10k SW2 R1 400 10 XRS V6 3V VCC3 3V 9 8 7 PBLK R2 22 6 OFFSET SW1 H DRVOUT L VRB 5 4 3 PS GND2 2 GND3 1 DRV PL6 PL5 PL4 GND CXA2096N Measurement Timing Chart 1H 2µs 2.5V PL4 (CLPOB) GND 1H 2µs 2.5V PL1 (CLPDM) GND 2.5V PL6 (PBLK) GND 1H V2 (DIN) Different for each test Equivalent to CCD signal black level 2.5V PL2 (SHD) PL3 (SHP) PL5 (XRS) GND –9– CXA2096N Application Circuit CCD 23 21 22 19 20 SHP SHD GND1 CLPDM PIN DIN VCC2 ICONT 1µF 18 17 0.1µF 15 16 AGCCLP VCC 1µF CCDLEVEL VCC 24 VAGCCONT 1.5 to 3V SHP VCC1 VICONT 1.5 to 3V SHD AGCCONT CLPDM 13 14 BUF SH1 SH2 DC SHIFT AGC OB SW SH3 CDS CLP2 DMSW2 AGC CLP VREF CAM SH DMSW1 VRT DRV OFFSET CDS CLP1 VRT BLK SW PBLK OFFSET VRT 10 12 11 CLPOB 9 8 7 VRB N.C. 6 VCC3 GND3 22 VRB 5 4 3 PS GND2 2 DRVOUT 1 DRV XRS POWER SAVE CONT VRB DRV XRS CLPOB VCC 3V VOFFSET PBLK 0 to 3V 4.7µ A/D IN VRB 4.7µF A/D GND VRT Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXA2096N Description of Operation Refer to the Block Diagram. Operating Conditions The camera signal processing system operates when PS is High. Timing Chart (when VCC = 3V) Signal interval Idle transfer interval OPB interval Signal interval Precharge level CCD output Signal level SHP SHD SH1 output 2.1V [∗1] SH2 output [∗2] SH3 output 2.1V CLPDM (2µ dummy bit portion during the idle transfer interval) AGC output SH3 output –SH2 output 2µs Basic black level × (–N) Black level 0.65V [∗3] XRS CLPOB (2µ during the OPB interval) 2µs CAMSH output 0.65V PBLK (10µ during the idle transfer interval) 10µs BLK SW output 1.35V [∗4] DRVOUT output [∗5] – 11 – Approx. VRB + 35mV when OFFSET = 0V Approx. VRB + 100mV when OFFSET = 1.5V Applox. VRB when OFFSET = 3V CXA2096N CDS (SH1, SH2, SH3): The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the sample-and-hold circuits for the precharge level; SH3 is the sample-and-hold circuit for the signal level. CDSCLP 1, 2: CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([∗1], [∗2]) of SH2 and SH3 in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for the signal level. AGC: AGC is the gain control amplifier for the camera signal. The gain can be varied from –1 to +31dB by adjusting the AGCCONT voltage control VAGCCONT from 1.5 to 3.0V. CAM SH: CAM SH is the sample-and-hold circuit for synchronizing the data read-in timing for the external A/D. Sampling is possible according to the approximately 10ns sampling pulse width input to XRS. AGCCLP: The basic black level is set ([∗3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin. DC SHIFT: This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black level is maintained at its previous setting. BLK SW: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential with VRB. ([∗4]) The signal is blanked when PBLK is Low. OFFSET: OFFSET controls the DRV output waveform black level offset. The offset of the DRVOUT camera signals can be adjusted when a voltage is applied to OFFSET. ([∗5]) The voltage controlled by OFFSET is output as the DRV output DC offset via AGCCLP, DCSHIFT, CAMSH and BLKSW. When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from VRB + 100mV to VRB. In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV. – 12 – CXA2096N DRV: DRV drives the external A/D. The current that flows to the last-stage amplifier in DRV is controlled by applying voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected. VRTDRV, VRBDRV: These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB, supplying 2.35V and 1.35V, respectively, when VCC is 3V. The IC's internal primary voltage is also generated on the basis of the VRT and VRB voltage. (VRB, VB and VCENT) POWER SAVE CONTROL: The PS pin is the power save pin; the operating state is enabled when this pin is High, while the power saving function operates when it is Low. – 13 – CXA2096N Characteristics Graphs AGCCONT control supply voltage characteristics VAGCCONT vs. Gain OFFSET control supply voltage characteristics VOFFSET vs. OFFSET 140 Tc = 27°C 35 VCC = 3V VCC = 3.15V VCC = 3.6V 30 Tc = 27°C 120 OFFSET [mV] Gain [dB] 100 20 10 80 60 40 0 –4 1.5 2.0 2.5 3.0 3.5 20 VCC = 3.6V VCC = 3V VAGCCONT [V] (VRB =) 0 0 1.0 2.0 3.0 3.5 VOFFSET [V] OFFSET control temperature characteristics VOFFSET vs. OFFSET AGCCONT control temperature characteristics AGCCONT vs. Gain VCC = 3.0V Tc = –20°C Tc = +27°C Tc = +75°C 35 30 VCC = 3.0V Tc = –20°C Tc = +27°C Tc = +75°C OFFSET [mV] Gain [dB] 150 20 100 10 50 0 –4 (VRB =) 0 1.5 2.0 2.5 0 3.0 1.0 2.0 VOFFSET [V] AGCCONT [V] – 14 – 3.0 CXA2096N Maximum signal amplitude temperature characteristics (Max. gain) Tc vs. Vout Maximum signal amplitude temperature characteristics (Min. gain) Tc vs. Vout VCC = 3.0V, AGCCONT = 3.0V Input amplitude DIN = 28mVp-p Input amplitude DIN = 24mVp-p Input amplitude DIN = 21mVp-p 0.9 Gain temperature characteristics from –20 to +100°C VCC = 3.0V, AGCCONT = 1.5V Input amplitude DIN = 870mVp-p Input amplitude DIN = 800mVp-p Input amplitude DIN = 750mVp-p Input amplitude DIN = 700mVp-p Input amplitude DIN = 600mVp-p DIN = 28mVp-p 0.8 30.99dB 30.99dB DIN = 24mVp-p DIN = 870mVp-p Vout [Vp-p] 1.0 30.76dB +0 31.41 –0.38 dB DIN = 800mVp-p 0.7 DIN = 750mVp-p 0.9 31.41dB 31.41dB DIN = 21mVp-p DIN = 700mVp-p 31.03dB +0 31.45 –0.33 dB 0.8 31.45dB 0.75 –20 0 0.6 DIN = 600mVp-p 31.12dB 31.45dB 50 0.53 –20 100 0 50 Tc [°C] Tc [°C] VRT, VRB, VRT – VRB temperature characteristics Tc vs. VRT, VRB, VRT – VRB 2.4 VRT 2.2 VRT, VRB, VRT – VRB [V] Vout [Vp-p] +0 30.99 –0.23 dB 2.0 VCC = 3.0V 1.8 1.6 VRB 1.4 1.2 VRT – VRB 1.0 0.8 –20 0 20 40 Tc [°C] – 15 – 60 80 100 CXA2096N Package Outline Unit: mm 24PIN SSOP(PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 0.1 24 13 ∗5.6 ± 0.1 7.6 ± 0.2 A 1 12 b 0.13 M 0.5 ± 0.2 (0.15) (0.22) 0.1 ± 0.1 DETAIL B : SOLDER b=0.22 ± 0.03 + 0.03 0.15 – 0.01 + 0.1 b=0.22 – 0.05 + 0.05 0.15 – 0.02 0.65 B DETAIL B : PALLADIUM 0° to 10° NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-24P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE SSOP024-P-0056 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 16 –