SONY CXA2108Q

CXA2108Q
Constant-Current Driver for Full Color LED Display
For the availability of this product, please contact the sales office.
Description
The CXA2108Q is a 1,024-gradation LED driver
which is ideal for full color LED displays. This IC has
24 outputs and a maximum output current of 60mA.
Time division allows driving of either two or six LEDs
per output by connecting an external FET or other
switch. The luminance (PWM) and drive current for
each LED are set using the internal RAM. The LED
type is common anode.
80 pin QFP (Plastic)
Features
• 24 outputs: 10-bit (1,024-gradation) PWM current outputs
• Maximum output current: 60mA
• LED type: Common anode
• 4-bit brightness function capable of switching the basic PWM pulse width in 16 steps
• Time division allows driving of up to six LEDs with a single output, making it possible to configure a high
definition display with few driver ICs.
• Coarse Adj. (2 bits) and Fine Adj. (8 bits) output current adjustment for each LED makes it possible to drive
R, G and B using the same output from the same IC. In addition, the characteristics variance of each LED
can also be corrected.
• All luminance (PWM) data and drive current data are set by writing to the internal RAM.
• PWM emitting can be performed up to 15 times per frame to realize a screen with little flicker.
• Two built-in PWM data RAM make it possible to set the next luminance data even during PWM operation.
• Abnormal internal temperature detection circuit
• Single 5V power supply
• Surface mounting package (80-pin QFP)
Applications
LED display panels
Structure
Bi-CMOS silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Digital input voltage
• Digital output current
• Driver output voltage
• Driver output current
• Operating temperature∗1
• Storage temperature
• Allowable power dissipation∗1 (Ta = 65°C or less)
AVCC, DVCC
VI_D
Io_D
V_DVR
I_DVR
Topr
Tstg
PD
–0.3 to +6.0
–0.3 to DVCC + 0.3
–5.0 to +5.0
0 to AVCC + 0.3
–1 to +80
–40 to +80
–65 to +150
1.5
V
V
mA
V
mA
°C
°C
W
Recommended Operating Range
• Supply voltage
• Driver output compliance voltage
• Operating temperature (ambient temperature)∗1
• Operating temperature (case temperature)∗1
AVCC, DVCC
Vcmp
Ta
Tc
4.75 to 5.25
1.5 to AVCC + 0.3
–20 to +65
–20 to +110
V
V
°C
°C
∗1 When mounted on a printed circuit board
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98333B91-PS
10
10
Drive Current data RAM
(6word × 24ch × 10bit)
PWM data RAM (B)
(6word × 24ch × 10bit)
PWM data RAM (A)
(6word × 24ch × 10bit)
D0 to 9
RDY
R_CLK
XR/W
MODE
A0 to 9
Data Read Counter
XRD
CLK
XWR
10
DATA
10
DATA
BRT
4
R_ADR
9
10bit × 24
Shift Reg.
&
Latch
Drive
Current
data
PWM data
10bit × 24
Shift Reg.
&
Latch
10 × 24
Data
Comparator
Counter
out
10
PWM Counter
10 × 24
DLDI
Band
Gap
Ref.
XTAO
–2–
24
8bit DAC with
2bit coarse Adj.
(× 24)
PWMout
24
REXT
Block Diagram
Rext
IOUT23
× 24
IOUT0
XB
XG
XR
XUPR
DLDO
CXA2108Q
CXA2108Q
IOUT6
IGND
IOUT7
IOUT8
IOUT9
IGND
IOUT10
IOUT11
IOUT12
IOUT13
IGND
IOUT14
IOUT15
IOUT16
IGND
IOUT17
Pin Configuration (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
IOUT18 1
64 IOUT5
IOUT19 2
63 IOUT4
IOUT20 3
62 IOUT3
IOUT21 4
61 IOUT2
IGND 5
60 IGND
IOUT22 6
59 IOUT1
IOUT23 7
58 IOUT0
AVCC 8
57 AVCC
AGND 9
56 AGND
NC 10
55 REXT
MODE 11
54 NC
DGND 12
53 NC
RDY 13
52 XTAO
DLDO 14
51 XRST
WALL 15
50 XR/W
XUPR 16
49 XRD
TEST_O 17
48 XWR
XB 18
47 XCS
XR 19
46 DLDI
XG 20
45 A9
CLK 21
44 A8
DGND 22
43 DVCC
DVCC 23
42 DGND
41 A7
D0 24
–3–
A6
A5
A4
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXA2108Q
Pin Description
Reference
Pin
No.
Symbol
9, 56
AGND
—
8, 57
AVCC
— 5V (Typ.)
Analog power supply.
12, 22, 42 DGND
—
Digital GND.
23, 43 DVCC
— 5V (Typ.)
Digital power supply.
5, 60,
66, 70, IGND
75, 79
—
GND for driver output.
10,
NC
53, 54
—
21
51
I/O voltage
Equivalent circuit
CLK
XRST
I
I
GND
Analog GND.
GND
GND
Open.
This pin is not connected with the
internal circuits.
CMOS
Clock input.
Driver operation is synchronized with
this clock.
CMOS
Reset input.
The IC is initialized by inputting low
level. However, the memory is not
initialized. Input high level during
normal operation.
DVCC
21 51 11
11
MODE
I
CMOS
34 35 36
37 38 39
40 41 44 45
34 to 41,
A0 to 8
44
45
Description
level
A9
I
I
CMOS
DGND
Output mode switching.
Upper/Lower mode for low level input.
Upper/Lower/RGB mode for high level
input. (See the Description of Operation.)
Address input.
These pins are used to input the internal
RAM (luminance data, brightness data
and drive current data RAM) address.
RAM selection.
The luminance data RAM is selected
when this pin is low, and the drive
current data RAM when high.
CMOS
DVCC
DGND
24 to 33 D0 to 9
I/O CMOS
DVCC
24 25 26
27 28 29
30 31 32 33
DGND
–4–
Data I/O.
These pins are used to input and
output data to and from the internal
RAM (luminance data, brightness data
and drive current data RAM). See
Table 1. Read/Write Switching
Condition Correspondence Table for
the data I/O switching conditions.
CXA2108Q
Pin
No.
47
50
Symbol
Reference
I/O voltage
Equivalent circuit
XCS
XR/W
I
I
CMOS
Internal RAM chip select.
Internal RAM access is enabled by
inputting low level. (See Table 1.
Read/Write Switching Condition
Correspondence Table.)
CMOS
Internal RAM read/write select.
Write mode is selected for high level, and
read mode for low level. See Table 1.
Read/Write Switching Condition
Correspondence Table for the actual
read/write switching signal input conditions.
DVCC
46 47 48
48
XWR
I
CMOS
49 50
DGND
49
46
Description
level
XRD
DLDI
I
I
Write clock input.
This pin is used to input the clock for
writing the luminance, brightness and
drive current data. It is not
synchronized with CLK.
CMOS
Read clock input.
This pin is used to input the clock for
externally reading the luminance,
brightness and drive current data. It is
not synchronized with CLK.
CMOS
Trigger signal input for luminance data
RAM (A)/(B) switching and PWM
output start.
(See the Timing Charts.)
–5–
CXA2108Q
Pin
No.
Symbol
Reference
I/O voltage
Equivalent circuit
Description
level
13
RDY
O
CMOS
READY signal output.
This indicates the drive current data
RAM access enabled period. Access
is enabled while high level is output.
(See the Timing Charts.)
14
DLDO
O
CMOS
DLDI signal output.
This outputs the DLDI signal
synchronized with CLK.
15
WALL
O
CMOS
DVCC
13 14 15
16 17 18
19 20 52
16
XUPR
O
CMOS
DGND
17
18
19
20
52
TEST_O O
XB
XR
XG
XTAO
O
O
O
O
Write ALL signal output.
One pulse (= high level signal with a
width of 1 clock) is output
synchronized with the rising edge of
the next CLK after the final address∗1
of the currently selected mode is input.
Note that both the final address must
be input and the XCS and XWR input
levels must be low at the rising edge
of this CLK.
(See the Timing Charts for details.)
∗1 02Fh (Upper/Lower mode)
08Fh (Upper/Lower/RGB mode)
Upper signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
CMOS
Test signal output.
This pin is unrelated to the functions of this IC.
Do not connect anything; leave this pin open.
CMOS
Blue signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
CMOS
Red signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
CMOS
Green signal output.
This is used as the LED switching signal.
(See the Timing Charts and Application
Circuits for details.)
CMOS
Thermal Alarm Out signal output.
This pin normally outputs high level, but it
outputs low level when the internal
temperature rises to an abnormally high level.
–6–
CXA2108Q
Pin
No.
Symbol
Reference
I/O voltage
Equivalent circuit
Description
level
AVCC
REXT
55
O
Drive current setting.
Connect a resistor between this pin
and GND. The drive current is
proportional to the current flowing to
this resistor. (See Table 2. Drive
Current Setting and Power
Consumption.)
55
AGND
AVCC
1 to 4,
6, 7,
58, 59,
61 to 65, IOUT0
67 to 69, to 23
71 to 74,
76 to 78,
80
1
2
6
7 58 59
3
4
61 62 63 64
O
65 67 68 69
Drivers.
These pins drive the LED.
71 72 73 74
76 77 78 80
IGND
XCS
[I]
XR/W
[I]
L
L
H
L
H
H
Luminance
Drive current
A9
[I]
Write
Read
Write
Read
D0 to 9
[I/O]
L
Disable
Enable
Disable
Disable
Output
H
Disable
Disable
Disable
Enable
Output
L
Enable
Disable
Disable
Disable
Input
H
Disable
Disable
Enable
Disable
Input
L
Disable
Disable
Disable
Disable
Hi-Z
H
Disable
Disable
Disable
Disable
Hi-Z
L
Disable
Disable
Disable
Disable
Hi-Z
H
Disable
Disable
Disable
Disable
Hi-Z
Table 1. Read/Write Switching Condition Correspondence Table
–7–
CXA2108Q
Rext [kΩ]
D9
D8
Io (FFh) [mA] Io (00h) [mA]
2.0
0
0
21.7
2.0
0
1
2.0
1
0
43.3
65.0 ∗1
2.0
1
1
2.5
0
2.5
Istb [mA]
Pstb [W]
Po (max) [W]
10.8
27.3
0.136
1.36
21.7
48.3
0.241
1.26
32.5
69.2
0.346
1.15
86.7 ∗2
43.3
90.2
0.451
1.05
0
17.3
8.7
22.4
0.112
1.39
0
1
34.7
17.3
39.2
0.196
1.30
2.5
1
0
26.0
55.9
0.280
1.22
2.5
1
1
52.0
69.3 ∗1
34.7
72.7
0.364
1.14
3.0
0
0
14.4
7.2
19.1
0.096
1.40
3.0
0
1
28.9
14.4
33.1
0.166
1.33
3.0
1
0
43.3
21.7
47.1
0.235
1.26
3.0
1
1
57.8
28.9
61.1
0.305
1.19
3.5
0
0
12.4
6.2
16.8
0.084
1.42
3.5
0
1
24.8
12.4
28.8
0.144
1.36
3.5
1
0
37.1
18.6
40.8
0.204
1.30
3.5
1
1
49.5
24.8
52.8
0.264
1.24
4.0
0
0
10.8
5.4
15.1
0.075
1.42
4.0
0
1
21.7
10.8
25.6
0.128
1.37
4.0
1
0
32.5
16.3
36.0
0.180
1.32
4.0
1
1
43.3
21.7
46.5
0.233
1.27
∗1 Operation guaranteed current exceeded.
∗2 Absolute maximum rating exceeded.
Table 2. Drive Current Setting and Power Consumption (when D0 to D7 = FFh)
Rext
: External resistor that sets the DAC reference current (Iref)
D9, D8 : Data that sets the maximum drive current (Io (FFh))
Iref
: DAC reference current
Iref [mA] = 1.3 [V]/Rext [kΩ]/24
Io (FFh) : Maximum drive current that can be set by D0 to D7
Io (FFh) [mA] = Iref × (2 × D9 + D8 + 1) × 800
Io (00h) : Minimum drive current that can be set by D0 to D7
Io (00h) [mA] = Io(FFh)/2
Istb
: Standby current (Internal current consumption excluding the driver block)
Istb [mA] = 2.86 + 24 × Iref × (16/3 + 32.25 × (2 × D9 + D8 + 1))
Pstb
: Standby power (Internal power consumption excluding the driver block, Vcc = 5 V)
Pstb [W] = 5 [V] × Istb [mA]/1000
Po (max) : Maximum power that can be consumed by the driver block
Po (max) [W] = 1.5 [W] – Pstb [W]
Note) Istb, Pstb and Po (max) are the values when D0 to D7 = 11111111 (FFh).
In addition, these values assume the case where all channels are set to the same drive current.
–8–
CXA2108Q
Electrical Characteristics
Item
(AVCC, DVCC = +5V, AGND, DGND, IGND = 0V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
15
MHz
1356
mV
Driver block
PWM reference clock frequency
fCLK
REXT pin voltage
VREXT
Rext = 2kΩ
REXT pin voltage
Supply voltage dependency
∆VREXT
VREXT (@AVCC = 5.25V)
– VREXT (@AVCC = 4.75V)
0
20
mV
Standby supply current
IDD
Rext = 2kΩ, D8 = D9 = 0
Note) Excluding the driver block
25
35
mA
1253
1300
10
bit
Coarse Adj.
2
bit
Fine Adj.
8
bit
PWM output resolution
Drive current setting resolution
DC characteristics
DLE
Differential linearity error
Output current
Io (FFh) = 60mA
(D0 [LSB] to D7 [MSB] = FFh)
IOUT
1.5
Output compliance voltage Vcmp
–9–
±0.8
LSB
60
mA
AVCC + 0.3
V
CXA2108Q
(AVCC, DVCC = +5V, AGND, DGND, IGND = 0V)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Logic block
Digital input current (I, I/O)
(H)
IIH, IIZH
VIN = 5V
–5
5
µA
(L)
IIL, IIZL
VIN = 0V
–5
5
µA
(H)
VIH, VIZH
VIN = 5V
0.7DVCC
DVCC + 0.3
V
(L)
VIL, VIZL
VIN = 0V
–0.3
0.3DVCC
V
(H)
VOH
DVCC = 5V, IOH = –2mA
(L)
VOL
DVCC = 5V, IOL = 4mA
(H)
VOZH
DVCC = 5V, IOH = –2mA
(L)
VOZL
DVCC = 5V, IOL = 4mA
Digital input voltage (I, I/O)
Digital output voltage (O)
4
V
0.4
V
Digital output voltage (I/O)
3.7
V
0.4
V
RAM write mode
Write cycle
TWR
133.3
ns
Write pulse width
TCWR
55
ns
Setup time
TSWR
10
ns
Hold time
THWR
10
ns
RAM read mode
Read cycle
TRD
133.3
ns
Read pulse width
TCRD
55
ns
Setup time
TSRD
10
ns
Hold time
THRD
10
ns
Output delay time
TPDD
Output load 50pF or less
– 10 –
100
ns
CXA2108Q
Timing Charts (RAM)
(1) Write mode (XR/W = H)
TWR
TCWR
XWR
TSWR
THWR
A0 to 9
D0 to 9
Note) The address is not latched internally, so do not change the address while XWR is low.
(1) Read mode (XR/W = L)
TRD
TCRD
XRD
TSRD
THRD
A0 to 9
TPDD
D0 to 9
Note) The address is not latched internally, so do not change the address while XRD is low.
– 11 –
CXA2108Q
Electrical Characteristics Measurement Circuit
DC Characteristics Measurement Circuit
CLK
15MHz
CXA2108Q
REXT
5V
0V
10
10
IOUT0 to 23
AGND
DGND
IGND
Logic Tester
XRST
MODE
XR/W
XRD
XWR
DLDI
A0 to 9
D0 to 9
XCS
AVCC
DVCC
5V
2kΩ
– 12 –
A
1.5V
CXA2108Q
Description of Operation
1. Description
The CXA2108Q is an LED driver for full color LED displays. The RGB luminance which becomes the video
data is controlled by pulse width modulation (PWM), and the luminance variance of each LED is corrected by
the drive current. The basic PWM clock width can be set in 16 steps from 1× to 16× by the brightness data,
making it possible to adjust the brightness of the entire screen. There are 24 driver outputs, and time division
allows driving of either two or six LEDs per output by adding an external FET or other switch.
The luminance (pulse width), drive current and brightness are set by writing data to the internal memory
according to the memory map. The luminance and drive current can be set independently for each LED.
2. Relationship between the luminance data (PWM data: Dv), brightness data (Db) and the LED emitting duty
The CXA2108Q adjusts the LED luminance which becomes the video data by changing the LED emitting time
duty through PWM of the luminance data. The luminance consists of luminance data and brightness data. The
luminance data (Dv) has an accuracy of 10 bits (= 1,024 steps: 0 to 1,023) and can be set independently for
each LED. The brightness data (Db) controls the basic PWM clock width with 4 bits (= 16 steps: 1× to 16×),
and is common data for all outputs. The brightness data is normally used when adjusting the brightness of the
entire screen.
Labeling the LED emitting cycle as Ts and the CLK cycle as TCLK , this relationship is given by the following
formula.
Ts = 1,024 × 16 × TCLK
The LED emitting time Tv within this Ts time is:
Tv = Dv × Db × TCLK
Therefore, the emitting duty is:
Tv/Ts × 100 = (Dv × Db)/(1,024 × 16) × 100 [%]
The drive current waveform and the relationship between the luminance data, brightness data and the emitting
duty are shown below.
Current
Tv = Dv × Db × TCLK
IOUT
0
Drive current
TS = 1,024 × 16 × TCLK
TS
Fig. 1. Drive Current Waveform
– 13 –
Time
CXA2108Q
Nv∗1 and emitting duty
Luminance data (Dv)
D9 to 0
Brightness (D3 to 0) = 0000
D9
D0
Emitting duty [%]
Nv
Nv
Emitting duty [%]
Nv
Emitting duty [%]
0
8
16
:
4096
:
8184
0
0.049
0.098
:
25.00
:
49.95
0
16
32
:
8192
:
16368
0
0.098
0.195
:
50.00
:
99.90
:
0
0.006
0.012
:
3.125
:
6.244
0
1
2
:
512
:
1023
:
0000000000
0000000001
0000000010
:
1000000000
:
1111111111
Brightness (D3 to 0) = 1111
Brightness (D3 to 0) = 0111
∗1 Nv = Tv/TCLK = Dv × Db
Table 3. Relationship Between Luminance Data, Brightness Data and Emitting Duty
3. Drive current data (Dd)
Even when driving LEDs of the same color with the same current value, individual differences in characteristics
result in an uneven emitting intensity. In addition, the required current value also differs according to the
emitting color (RGB). That is to say, the necessary current differs for each LED. This drive current IOUT
corresponds to the amplitude of the IOUT output PWM waveform as shown in Fig. 1. The CXA2108Q can set
this current independently for each LED using Coarse Adj. (2 bits: D8, D9) and Fine Adj. (8 bits: D0 to D7). The
maximum drive current (Io (FFh): IOUT @ D0 to D7 = FFh) is set by Coarse Adj. (2 bits: D8, D9). The
minimum drive current (Io (00h): IOUT @ D0 to D7 = 00h) is approximately 1/2 of Io (FFh), and the range from
the minimum to the maximum drive current can be set at an accuracy of 8 bits (D0 to D7 = 256 steps).
Note that this drive current is generated using the Iref described in 6. as the reference.
The relationship between the Fine Adj. (8 bits: D0 to D7) data and the drive current, and the drive current data
(D0 to D9) to drive current correspondence table are shown below.
Drive current
Io (FFh)
(Maximum drive current)
• •
(256 steps)
• •
1 LSB
= (Io (FFh)
– Io (00h))/255
Io (00h)
≈ Io (FFh)/2
(Minimum drive current)
0
FEh
FFh
01h
00h
Fine Adj. (8 bits: D0 to D7) data
Fig. 2. Relationship Between Fine Adj. (8 bits: D0 to D7) Data and Drive Current
Drive current data (Dd)
D7 to 0
D7
D0
00000000 (00h)
:
10000000 (80h)
:
11111111 (FFh)
Drive current
D9
0
D8 D9
0 0
D8 D9
1 1
D8 D9
0 1
D8
1
400 × Iref 800 × Iref 1200 × Iref 1600 × Iref Minimum drive current Io (00h)
:
:
:
:
1200
× Iref 1800 × Iref 2400 × Iref
600 × Iref
:
:
:
:
1600
× Iref 2400 × Iref 3200 × Iref Maximum drive current Io (FFh)
800 × Iref
Table 4. Drive Current Data (D0 to D9) to Drive Current Correspondence Table
– 14 –
CXA2108Q
4. Operating modes (Upper/Lower, Upper/Lower/RGB)
The CXA2108Q has the following two operation modes which are set by the MODE pin.
4-1. Upper/Lower mode (MODE = low)
In this mode, two LEDs are driven by time division for each IOUT output.
First, PWM waveform output starts triggered by the DLDI input signal. In this mode, two kinds of luminance
data are output by time division for each output. Labeling these data as U and L, the driver outputs the data in
the order of U → L → U → L → U → and so on. The XUPR pin output voltage switches in sync with the LED
emitting cycle Ts in the order of L → H → L → and so on, so this can be used as the FET or other switch signal
for switching the LED. (See Fig. 6. Timing Chart 2-1 and Fig. 11. Application Circuit (1) for details.)
New PWM data is output when the next DLDI signal is input.
4-2. Upper/Lower/RGB mode (MODE = high)
In this mode, six LEDs can be driven by time division for each IOUT output.
PWM waveform output starts triggered by the DLDI input signal. In this mode, six kinds of luminance data are
output by time division for each output. Labeling these data as UB, UR, UG, LB, LR and LG, the driver
switches the output in the order of UB → UR → UG → LB → LR → LG → UB → and so on. Like Upper/Lower
mode, the XUPR and also the XB, XR and XG output voltages switch in sync with Ts, so these can be used as
the FET or other switch signals for switching the LEDs. The output voltages at this time are: XUPR = low for
U∗, XUPR = high for L∗, XB = low (XR = XG = high) for ∗B, XR = low (XB = XG = high) for ∗R, and XG = low
(XB = XR = high) for ∗G. (See Fig. 7. Timing Chart 2-2 and Fig. 12. Application Circuit (2) for details.)
New PWM data is output when the next DLDI signal is input.
5. Luminance data memory and DLDI signal
The CXA2108Q uses two sets of 6-word × 24-channel × 10-bit RAM (RAM (A), RAM (B)) as luminance data
memories, and switches these memories. While the data in one memory is being loaded internally and PWM
output is being performed, the next luminance data can be written to the other memory from an external
source. Memory switching is performed by inputting a trigger signal to the DLDI pin. The read/write enabled
memory alternates from A → B → A → and so on, and the memory used for PWM output alternates from B →
A → B → and so on each time the signal is input to DLDI. The DLDI signal switches the memory, and at the
same time functions as the PWM output start trigger pulse. See the Timing Charts for details.
6. Reference current (Iref)
The drive current is generated using the current flowing to an external resistor as the reference. This resistor
Rext is connected between the REXT pin and GND. The REXT pin voltage is designed to be unaffected by
supply voltage, temperature or other fluctuations, and is always a constant voltage (approximately 1.3V).
Therefore, a constant current can be realized by using a resistor that does not have temperature
characteristics. The current obtained by dividing this current value by the number of IOUT outputs (24) is
defined as Iref.
Iref = (1.3/Rext)/24
The maximum drive current value can be changed by varying the resistance value. See Table 2. Drive Current
Setting and Power Consumption for details.
– 15 –
CXA2108Q
7. Data setting
The above mentioned luminance data Dv, brightness data Db and drive current data Dd are set using address
input pins A0 to A9 and data I/O pins D0 to D9. See the Timing Charts for the memory read/write enabled
period, and Table 1. Read/Write Switching Condition Correspondence Table for the pin setting conditions. The
address, data, XWR and XRD setup, hold and other timings should be as stated in the Electrical
Characteristics. See Tables 5. and 6. LED Driver Memory Map with respect to the memory address of each
IOUT output pin (IOUT0 to IOUT23).
The relationship between the data and the memory address is as follows.
A9 to A0
MSB
A9
LSB
A0
,
,
•
•
Can't use
Can't use
Brightness Data
Brightness Data
0100101000
0100100111
•
•
0100100000
0100011111
•
•
Don't use
0010010000
0010001111
•
•
LG
0001111000
0001110111
•
•
LR
Don't use
0001100000
0001011111
•
•
a + 23
LB
IOUT23
IOUT22
IOUT21
UG
•
•
0001001000
0001000111
•
•
0000110000
0000101111
•
•
UR
L
UB
U
Upper/Lower/RGB
Upper/Lower
0000011000
0000010111
•
•
a
IOUT4
IOUT3
IOUT2
IOUT1
IOUT0
0000000000
MODE
Fig. 3. Relationship Between Memory Address and Data (Luminance Data Dv, Brightness Data Db)
– 16 –
CXA2108Q
A9 to A0
MSB
A9
LSB
A0
,,,,
, •
•
Can't use
1010010000
1010001111
•
•
LG
1001111000
1001110111
•
•
LR
Can't use
1001100000
1001011111
•
•
a + 23
LB
IOUT23
IOUT22
IOUT21
UG
•
•
1001001000
1001000111
•
•
1000110000
1000101111
•
•
UR
L
UB
U
Upper/Lower/RGB
Upper/Lower
1000011000
1000010111
•
•
a
IOUT4
IOUT3
IOUT2
IOUT1
IOUT0
1000000000
MODE
Fig. 4. Relationship Between Memory Address and Data (Drive Current Data Dd)
– 17 –
– 18 –
LOWER
L
U
LOWER
L
Table 5. LED Driver Memory Map (Upper/Lower mode)
A2 to A0 = Don't care
111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23
110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22
101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21
100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20
011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19
010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18
001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17
000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16
1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001
UPPER
111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23
110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22
101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21
100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20
011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19
010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18
001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17
Brightness data: A9 to A3 = 0100100b (24h)
A2 to A0
U
000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16
Drive Current Data
A2 to A0
UPPER
A9 to A3
0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001
Luminance Data
CXA2108Q
– 19 –
R
UR
G
UG
B
LB
R
LR
G
LG
UB
R
UR
G
UG
B
LB
R
LOWER
LR
G
LG
Table 6. LED Driver Memory Map (Upper/Lower/RGB mode)
A2 to A0 = Don't care
111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23
110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22
101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21
100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20
011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19
010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18
001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17
000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16
1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001
B
UPPER
111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23
110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22
101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21
100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20
011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19
010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18
001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17
Brightness data: A9 to A3 = 0100100b (24h)
A2 to A0
UB
LOWER
000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16
Drive Current Data
A2 to A0
B
UPPER
A9 to A3
0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001
Luminance Data
CXA2108Q
R/W Enable
– 20 –
R/W Enable
L
U
R/W Disable
U
U
L
U
L
U
R/W Enable
(Accessing Internally)
RAM (A)
L
•••
R/W Enable
(Accessing Internally)
•••
Note)
L
L
U
R/W Disable
U
U
L
U
L
U
(Accessing Internally)
R/W Enable
RAM (B)
L
(Accessing Internally)
•••
•••
L
L
U
R/W Enable
R/W Disable
U
U
RAM (A)
L
R/W Enable
R/W Disable
RAM (A)
UB UR UG LB LR LG UB
U
and other symbols correspond to Tables 5. and 6. LED Driver Memory Map.
R/W Disable
R/W Enable
RAM (B)
UB UR UG LB LR LG UB UR UG LB LR
U , L
Partial enlargement diagram (Fig. 7. Timing Chart 2-2)
R/W Disable
RAM (A)
UB UR UG LB LR LG UB UR UG LB LR
U
Fig. 5. Timing Chart 1. Relationship between PWM waveform output and luminance RAM (A)/(B) with respect to DLDI input pulse
RAM (B)
RAM (A)
IOUT
output data
DLDI
L
Partial enlargement diagram (Fig. 6. Timing Chart 2-1)
U
Case 2: Upper/Lower/RGB mode
RAM (B)
RAM (A)
IOUT
output data
DLDI
Case 1: Upper/Lower mode
CXA2108Q
– 21 –
U
Emitting start
1024 × 16 clk = 1 Cycle
L
Emitting end
U
Note)
L
U , L
L
U
and other symbols correspond to Tables 5. LED Driver Memory Map.
U
Fig. 6. Timing Chart 2-1. DLDI input to IOUT output (Upper/Lower mode)
Partial enlargement diagram (Fig. 8. Timing Chart 3-1)
XUPR
IOUT
RDY
DLDO
DLDI
1 clk
CXA2108Q
– 22 –
UB
Emitting start
1024 × 16 clk = 1 Cycle
UG
LR
LG
UB
Note) UB , LG and other symbols correspond to Tables 6. LED Driver Memory Map.
LB
Fig. 7. Timing Chart 2-2. DLDI input to IOUT output (Upper/Lower/RGB mode)
Emitting end
UR
Partial enlargement diagram (Fig. 9. Timing Chart 3-2)
XG
XR
XB
XUPR
IOUT
RDY
DLDO
DLDI
1 clk
CXA2108Q
– 23 –
E = R/W Enable
D = R/W Disable
Luminance data RAM (A)
Luminance data RAM (B)
Driver current RAM
IOUT
XUPR
RDY
DLDO
DLDI
CLK
E
D
E
8 clk
9 clk
Emitting start
Nv clk
D
E
E
D
∗ NV = Dv × Db (Dv: Luminance data, Db: Brightness data)
1024 × 16 clk = 1 Cycle
Emitting end
48 clk
Fig. 8. Timing Chart 3-1. DLDI input to IOUT output (1 cycle) example (Upper/Lower mode)
D
48 clk
E
Emitting start
CXA2108Q
– 24 –
E = R/W Enable
D = R/W Disable
Luminance data RAM (A)
Luminance data RAM (B)
Driver current RAM
IOUT
XG
XR
XB
XUPR
RDY
DLDO
DLDI
CLK
E
D
E
8 clk
9 clk
Emitting start
Nv clk
D
E
E
D
∗ NV = Dv × Db (Dv: Luminance data, Db: Brightness data)
1024 × 16 clk = 1 Cycle
Emitting end
48 clk
Fig. 9. Timing Chart 3-2. DLDI input to IOUT output (1 cycle) example (Upper/Lower/RGB mode)
D
48 clk
E
Emitting start
CXA2108Q
D
128 clk
IOUT
XUPR
RDY
WALL
DLDO
E = R/W Enable
D = R/W Disable
Luminance data RAM (A)
Luminance data RAM (B)
Driver current RAM
– 25 –
D
IC initialization
1 clk = 7.5MHz (Max)
02F
Dv2F
48 clk
9 clk
E
D
E
Nv clk
D
E
E
Emitting start
∗ NV = Dv × Db (Dv: Luminance data, Db: Brightness data)
∗ Dd: Drive current data
D
8 clk
Fig. 10. Timing Chart 4. XRST input to IOUT output example (Upper/Lower mode)
Brightness data write
Luminance data write
Dd2F Db Dv0 Dv1 Dv2
22F 120 000 001 002
Drive current data write
Dd0 Dd1 Dd2
D0 to 9
DLDI
200 201 202
A0 to 9
XR/W
XWR
XRST
,,,,,,,
CLK
1 clk = 15MHz (Max)
Emitting end
CXA2108Q
– 26 –
G
G
G
Red
R
VB = 5.5V
Bule
B
B
B
DGND
XUPR
MODE
IOUT23
IOUT22
IOUT21
IOUT11
IOUT14
IOUT16
IOUT17
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
41
Data: D0 to D9
From Data Bus
42
24
43
23
44
22
45
21
46
20
47
18
19
48
49
50
51
52
53
54
55
56
57
58
17
16
15
14
13
12
11
10
9
8
7
59
60
5
6
61
62
63
64
IGND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
IOUT10
4
3
2
1
IOUT15
IGND
IOUT7
IOUT5
DGND
DVCC
AGND
2kΩ
AGND
AVCC
IGND
Address: A0 to A9
From Address Bus
XWR
XRD
XR/W
REXT
IOUT0
IOUT1
IOUT2
IOUT3
IOUT4
5V
0V
5V
0V
Address
Bus
Data Bus
5V
0V
Bus CLK
Bus CLK
(7.5MHz)
Read/Write
Control signal
7.5MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
DVCC
15MHz CLK
DGND
DGND
AGND
AVCC
IGND
Fig. 11. Application Circuit (1)
VG, VR, VB: LED DC supply
from IOUT0
from IOUT1
from IOUT2
from IOUT3
•
•
•
•
•
•
•
•
•
from IOUT23
from XUPR
IOUT20
IOUT19
IOUT18
IOUT12
IGND
IOUT13
IGND
IOUT9
VR = 4.0V
Green
VG = 5.5V
IOUT8
UPPER/LOWER mode
IOUT6
Application Circuit
CXA2108Q
– 27 –
G
G
G
G
G
R
R
R
R
R
B
B
B
B
B
Bule
VB = 5.5V
Red
VR = 4.0V
Green
VG = 5.5V
DGND
XG
XR
XB
XUPR
MODE
IOUT23
IOUT22
IOUT11
IOUT13
IOUT12
IOUT14
IOUT15
IOUT16
IOUT17
24
23
22
21
20
19
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Data: D0 to D9
From Data Bus
41
42
43
44
45
46
47
48
17
18
49
50
51
52
53
54
55
56
57
58
16
15
14
13
12
11
10
9
8
7
59
60
6
61
5
62
63
64
IGND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
IOUT10
4
3
2
1
IOUT7
DGND
DVCC
AGND
2kΩ
AGND
AVCC
IGND
Address: A0 to A9
From Address Bus
XWR
XRD
XR/W
REXT
IOUT0
IOUT1
IOUT2
IOUT3
IOUT4
IOUT5
Data Bus
Address
Bus
Bus CLK
5V
0V
5V
0V
5V
0V
Bus CLK
(7.5MHz)
Read/write
control signal
7.5MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
DVCC
15MHz CLK
DGND
AGND
DVCC
AVCC
IGND
IOUT21
IOUT20
IOUT19
IOUT18
Fig. 12. Application Circuit (2)
VG, VR, VB: LED DC supply
from IOUT0
from IOUT1
•
•
•
•
•
•
•
•
•
from IOUT23
from XUPR
from XG
from XR
from XB
IGND
IOUT9
IGND
IOUT8
IGND
IOUT6
UPPER/LOWER/RGB mode
CXA2108Q
CXA2108Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
+ 0.15
0.35 – 0.1
0.8
0.2
M
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 28 –
0.8 ± 0.2
80