CXA2125Q Audio/Video Switch with Electronic Volume for 3 Scart Description The CXA2125Q is an I2C programmable audio, video switch designed primarily for set top box applications. It interfaces from digital encoder sources to TV, VCR and auxiliary scart connectors. 64 pin QFP (Plastic) Features • 3 scart independent audio/video switching (TV, VCR, AUX) • 0 to –63dB volume control with click noise reduction • 5 stereo audio inputs • I2C control • Scart Function Switching input and output • Scart Fast Blanking for OSD • Mono switchable to stereo on TV, VCR and AUX outputs • On-chip +12V to +9V voltage regulator • Logic output • Selectable +6dB, +12dB gain on TV output • RGB input on VCR scart • Compatible with 2 scart Audio/Video switch CXA2126Q Applications Digital Set Top Box Structure Bipolar silicon monolithic IC Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Conditions • Supply voltage • Operating voltage 12 –20 to +75 –65 to +150 850 10.7 to 12 9 ± 0.5 V °C °C mW V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99338-PS CXA2125Q Block Diagram Typical Connection Typical Connection DIG FBLK_IN1 52 VCR FBLK_IN2 53 AUX FBLK_IN3 51 DIG BLUE VIN1 63 VCR BLUE VIN2 61 AUX BLUE VIN3 13 VIN4 DIG GREEN/CVBS 100Ω 50 TV_FBLANK VIDEO_SWITCH1 (TV) ×2 100Ω 48 VOUT1 TV BLUE 47 VOUT2 TV GREEN 46 VOUT3 TV RED/C 49 VOUT4 TV CVBS/Y 41 VOUT5 VCR CHROMA 2 VCR GREEN VIN5 59 AUX GREEN VIN6 15 DIG RED/CHROMA VIN7 4 DIG CHROMA VIN8 6 VCR RED/CHROMA VIN9 57 AUX RED/CHROMA VIN10 17 ×2 ×2 100Ω TV 100Ω 8 DIG CVBS/LUMA VIN11 DIG CVBS/LUMA VIN12 10 VCR CVBS/LUMA VIN13 55 AUX CVBS/LUMA VIN14 21 TV CVBS VIN15 23 ANALOGUE SAT CVBS VIN16 25 VID_VCC 60 VID_BIAS 62 VID_GND FBLK_SW +5V 0V ×2 100Ω VIDEO_SWITCH2 (VCR) ×2 4.05V 100Ω Bias 1 VCR 7 AUD_VCC 20 AUD_BIAS 19 ×2 4.5V 100Ω 44 VOUT6 VCR CVBS/Y 39 VOUT7 AUX CVBS Bias 2 AUD_GND 26 DIG_VCC 38 VIDEO_SWITCH3 (AUX) DIG_GND 43 VCC_12V 58 VREG_BASE 56 ×2 100Ω 9V reg VREG_9V 54 Bias 3 DIG RIN1 VCR RIN2 12 –6dB AUX RIN3 16 –6dB TV RIN4 22 –6dB ANALOGUE SAT RIN5 27 VOLUME CONTROL AUDIO_SWITCH1 (TV) & MUTE 8dB 5 LIN1 VCR LIN2 14 –6dB AUX LIN3 18 –6dB TV LIN4 24 –6dB ANALOGUE SAT LIN5 29 –6dB 33 MONO ×2 35 PHONO_R ×2 40 RTV ×2 42 LTV ×2 37 PHONO_L ×2 34 ROUT1 ×2 36 LOUT1 ×2 31 ROUT2 ×2 32 LOUT2 0/6dB TV ZCD –6dB DIG 1dB ×2 8dB 1dB 0/6dB MONO SWITCH Selectable Gain Stage AUDIO_SWITCH2 (VCR) VCR MONO SWITCH AUDIO_SWITCH3 (AUX) AUX MONO SWITCH Bias 4.5V HW_MUTE 45 Mute FNC_VCR 64 Monitor I2C Interface 1 Monitor LOGIC FNC_AUX SDA 11 SCL 30 FNC_TV 28 LOGIC P.O.D 9 3.3V or 5V –2– AUX CXA2125Q MONO ROUT1 PHONO_R LOUT1 PHONO_L DIG_VCC VOUT7 RTV VOUT5 DIG_GND LTV VOUT6 HW_MUTE VOUT3 VOUT2 VOUT1 VOUT4 TV_FBLANK FBLK_IN3 Pin Configuration 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FBLK_IN1 52 32 LOUT2 FBLK_IN2 53 31 ROUT2 VREG_9V 54 30 FNC_TV VIN13 55 29 LIN5 VREG_BASE 56 28 LOGIC VIN9 57 27 RIN5 VCC_12V 58 26 AUD_GND 25 VIN16 VIN5 59 24 LIN4 VID_VCC 60 23 VIN15 VIN2 61 22 RIN4 VID_BIAS 62 21 VIN14 VIN1 63 20 AUD_VCC –3– LIN3 AUD_BIAS RIN3 VIN10 LIN2 VIN6 VIN3 9 10 11 12 13 14 15 16 17 18 19 SDA 8 RIN2 VIN7 7 SCL RIN1 6 VIN12 VIN4 5 VIN11 4 VID_GND 3 LIN1 2 VIN8 1 FNC_AUX FNC_VCR 64 CXA2125Q Pin Description Pin No. 63 61 13 2 59 15 4 6 57 17 8 10 55 21 23 25 Symbol VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15 VIN16 Pin voltage Equivalent circuit Description VCC = 12V VCC = 9V 14µA 63 4 61 6 13 57 4.6V Video signal inputs. An input coupling capacitor is required. (typ = 0.47µF) 120kΩ 2 17 59 8 147Ω 15 10 60µA 55 21 23 25 VCC = 12V 12 16 22 27 RIN2 RIN3 RIN4 RIN5 14 18 24 29 LIN2 LIN3 LIN4 LIN5 4.5V 12 14 16 18 4.5V Audio signal inputs. An input coupling capacitor is required. (typ = 2.2µF) 33kΩ 22 24 27 29 33kΩ 7µA VCC = 12V 48 47 46 49 41 44 39 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 48 VCC = 9V 200Ω 140µA 47 46 3.9V 100Ω Video signal outputs. 49 41 44 280µA 39 –4– CXA2125Q Pin No. Symbol 40 34 31 42 36 32 35 37 33 RTV ROUT1 ROUT2 LTV LOUT1 LOUT2 PHONO_R PHONO_L MONO Pin voltage Equivalent circuit Description VCC = 12V VCC = 9V 33µA 22kΩ 35 31 4.5V 37 42 20kΩ 33 36 20kΩ 55Ω 40 32 Audio signal outputs. A coupling capacitor may be used. (typ = 10µF) 33µA 34 VCC = 12V VCC = 9V 14µA Reference Bias for video circuit. Connected to GND with capacitor. (typ = 47µF) 11kΩ 62 BIAS_ VIDEO 3.9V 62 200Ω 9kΩ VCC = 12V VCC = 9V Reference Bias for audio circuit. Connected to GND with capacitor. (typ = 22µF) 20kΩ 19 BIAS_ AUDIO 4.5V 19 20kΩ 7µA VCC = 12V 120Ω 30 FNC_TV — 15kΩ I2C controlled output giving 0V, 6V or 12V. 30 3kΩ –5– CXA2125Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC = 12V 77.7kΩ 54 VREG_9V 9V Pin connected to emitter of external regulator transistor. 54 13.5kΩ VCC = 12V 120µA VCC = 12V 1mA 56 VREG_ BASE Connection to base of external regulator transistor. Max I = 1mA 56 9.7V 413Ω 15pF 120µA VCC = 9V 40µA 4kΩ 9 SCL — 9 I2C clock input. 40kΩ 10kΩ VCC = 9V 40µA 4kΩ 11 SDA — 11 I2C data input/output. 40kΩ 4.5kΩ –6– CXA2125Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC = 12V 45 HW_MUTE 147Ω — HW MUTE: This pin is active high > 2.5V < 9V. When high, all audio muted. 72kΩ 45 28kΩ VCC = 12V VCC = 9V 3V 8µA 40kΩ 28 LOGIC — Open collector logic pins. 28 4.5kΩ 7.5kΩ VCC = 12V VCC = 9V 100Ω 100µA 50 FBLK_ OUT — 100Ω 50 100µA Fast Blank output set by I2C to input FBLK_IN1, FBLK_IN2, or FBLK_IN3. High = 5.3V Low = 1.2V Connected to external emitter follower. VCC = 9V VCC = 12V 50µA 52 53 51 FBLK_IN1 FBLK_IN2 FBLK_IN3 — Fast Blank inputs. Low = < 0.4V High = > 1.0V, < 3.0V 52 53 51 147Ω 90µA –7– CXA2125Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC = 9V 80µA 12.5kΩ 12.5kΩ 64 1 FNC_VCR FNC_AUX — Function switching input. (Scart pin 8) 64 1 10kΩ 25kΩ VCC = 12V 4.5V 33kΩ 3 RIN1 5 LIN1 4.5V Audio signal inputs. A coupling capacitor is required for these inputs. (typ = 2.2µF) 3 5 7µA –8– CXA2125Q Electrical Characteristics Nominal conditions (Ta = 25°C) Item Current consumption Symbol ICC Video system Item Conditions VCC_12V = 12V, No signal, no load Min. Typ. Max. Unit 30 50 80 mA Nominal conditions (Ta = 25°C, Vcc_12V = 12V, VREG_9V = 9V) Symbol Conditions Min. Typ. Max. Unit No signal, no load (Fig.1) 4.3 4.6 4.9 V Output pin voltage – with output on. VVPout1 No signal, no load (Fig.1) 3.6 3.9 4.2 V Output pin voltage – with output off. VVPout2 No signal, no load (Fig.1) — 0 0.2 V Gain GVv f = 200kHz, 0.3Vp-p input (Fig.2) 5.5 6.0 6.5 dB Bandwidth fV3dB 0.3Vp-p input, frequency where output level is –3dB with 200kHz serving as 0dB (Fig. 2) 15 20 — MHz Input dynamic range VDRVI 200kHz input (Fig.2) 2.5 — — Vp-p Output dynamic range VDRVO 200kHz, 2.5Vp-p input (Fig.2) 5.0 — — Vp-p Cross talk Vctv f = 4.43MHz, 1Vp-p input (Fig.2) — — –50 dB S/N ratio S/NV Ratio of 0.7Vp-p white video signal to "black line" noise. Weighted using CCIR 567. HPF @5kHz, LPF @5MHz. (Fig.2) — 72 — dB Input impedance ZinV 1Vrms 1kHz input through 56kΩ. Attenuation measured to calculate ZinV (Fig.3) 94 120 175 kΩ Non-linearity Lin –3 –0.4 3 % V1 V2 VVPin Input Pin V Plus Input pin voltage (Fig.4) V1 = Pin voltage +0.5V, V2 = Pin voltage +1V At output, non-linearity = V2 –1 × 100 V1 × 2 Differential gain DG 1.7Vp-p 5-step modulated staircase. (Chroma and Burst are 150mVp-p 4.43MHz) (Fig.2) –3 1.5 2 % Differential phase DP as above. (Fig.2) –3 1 2 Deg Sync crush SC Percentage reduction in sync pulse (0.4Vp-p), with tip at –1.2V input offset. (Fig.4) –2 0 2 % –9– CXA2125Q Audio system Unless otherwise stated: input coupling capacitor 1µF; output coupling capacitor of 10µF; load of 10kΩ. Nominal conditions (Ta = 25°C, Vcc_12V = 12V, VREG_9V = 9V) Item Symbol Input/output pin voltage Conditions Min. Typ. Max. Unit VAPIN No signal, no load (Fig. 5) 4.2 4.5 4.8 V Gain Input Output RIN1/LIN1 TV/Phono GVA1 f = 1kHz, 0.5Vrms input. TV output amplifier set to 0dB (Fig. 6) 5.5 6 6.5 dB RIN1/LIN1 TV/Phono GVA2 f = 1kHz, 0.5Vrms input. TV output amplifier set to +6dB (Fig. 6) 11 12 13 dB RIN1/LIN1 VCR/AUX GVA3 f = 1kHz, 1Vrms input. (Fig. 6) — 6 — dB RIN1 + LIN1 TV mono GVA4 f = 1kHz, 0.5Vrms stereo input. TV output amplifier set to 0dB (Fig. 6) — 6 — dB RIN1 + LIN1 TV mono GVA5 f = 1kHz, 0.5Vrms stereo input. TV output amplifier set to +6dB (Fig. 6) — 12 — dB RIN1 + LIN1 VCR mono AUX mono GVA6 f = 1kHz, 0.5Vrms stereo input. (Fig. 6) — 6 — dB RIN2, 3, 4, 5 LIN2, 3, 4, 5 TV/Phono GVA7 f = 1kHz, 1Vrms input. TV output amplifier set to 0dB (Fig. 6) –0.5 0 +0.5 dB RIN2, 3, 4, 5 LIN2, 3, 4, 5 TV/Phono GVA8 f = 1kHz, 1Vrms input. TV output amplifier set to +6dB (Fig. 6) 5.5 6 6.5 dB RIN2, 3, 4, 5 TV mono + LIN2, 3, 4, 5 GVA9 f = 1kHz, 1Vrms stereo input. TV output amplifier set to 0dB (Fig. 6) –0.7 0 +0.3 dB RIN2, 3, 4, 5 TV mono + LIN2, 3, 4, 5 GVA10 f = 1kHz, 1Vrms stereo input. TV output amplifier set to +6dB (Fig. 6) 5 6 7 dB RIN2, 3, 4, 5 LIN2, 3, 4, 5 GVA11 f = 1kHz, 1Vrms input. (Fig. 6) –0.5 0 +0.5 dB RIN2, 3, 4, 5 VCR mono + LIN2, 3, 4, 5 AUX mono GVA12 f = 1kHz, 1Vrms stereo input. (Fig. 6) –0.7 0 +0.3 dB Audio frequency response FAF 0.3Vp-p input. Output level at 30kHz with 1kHz serving as 0dB. (Fig. 7) –0.3 0 +0.3 dB Frequency B/W FBWA1 0.3Vp-p input; frequency where output level is –3dB with 1kHz serving as 0dB. No load (Fig. 7) — 1 — MHz Distortion THD f = 1kHz, 0.5Vrms, unweighted response; LPF @400Hz, HPF @80kHz. (Fig. 6) — 0.003 0.2 % Input dynamic range RIN2, 3, 4, 5 LIN2, 3, 4, 5 VdA1 f = 1kHz (Fig. 6) 2 — — Vrms Input dynamic range RIN1 LIN1 VdA2 f = 1kHz (Fig. 6) 1 — — Vrms Cross talk (Channel separation) VctA f = 1kHz, 1Vrms input on one input, measure on any other audio output. (Fig.6) — — –76 dB VCR/AUX – 10 – CXA2125Q Item Symbol Conditions Min. Typ. Max. Unit –30 — +30 mV DC offset Voff Offset voltage between input and output (Fig. 5) Input impedance RIN2, 3, 4, 5 LIN2, 3, 4, 5 Zin1 (excluding any external series resistor) — 66 — kΩ Input impedance RIN1/LIN1 Zin2 (excluding any external series resistor) — 33 — kΩ Output impedance Zout (excluding any external series resistor) — 10 — Ω Phase difference Vpda f = 1kHz, 1Vrms input to two channels. Phase difference of stereo output measured — 0.05 — Deg S/N ratio S/NA f = 1kHz, 1Vrms input (at maximum volume). HPF @20Hz, LPF@20kHz. (Fig. 6) 80 90 — dB Fine volume attenuation step AEVC f = 1kHz, 0.5Vrms input. Set by I2C. (Fig.6) 0.6 1 1.4 dB Coarse volume attenuation step AEVF f = 1kHz, 0.5Vrms input. Set by I2C. (Fig.6) 7.5 8 8.5 dB Mute Amute f = 1kHz, 1Vrms input. (Fig.6) — — –80 dB DC Offset -RTV, LTV VoffTV Offset voltage between any audio input and RTV, LTV outputs. (Fig.5) –30 0 +30 mV Electronic Volume Control – 11 – CXA2125Q I2C Electrical Characteristics Nominal conditions (Ta = 25°C, Vcc_12V = 12V, VREG_9V = 9V) Item Symbol Conditions Min. Typ. Max. Unit High level input voltage VIH 2.3 — 5.0 V Low level input voltage VIL 0 — 1.5 V Low level output voltage VOL 0 — 0.4 V Maximum clock frequency fSCL 0 — 100 kHz Minimum waiting time for data change tBUF 4.5 — — µs Minimum waiting time for data transfer start tHD;STA 4.0 — — µs 4.7 — — µs 4.0 — — µs With SDA, 3mA current supplied tLOW High level clock pulse width tHIGH Low level clock pulse width Minimum waiting time for start preparation tSU;STA 4.7 — — µs Minimum data hold time tHD;DAT 5 — — s Minimum data preparation time tSU;DAT 250 — — ns Rise time tR tF — — 1 µs — — 300 ns tSU;STO 4.7 — — µs Fall time Minimum waiting time for stop preparation – 12 – CXA2125Q V +12V +12V +12V +12V +12V +12V +12V BC547B BC547B BC547B BC547B BC547B BC547B BC547B 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ Measurement point +9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V +9V BC547B 52 32 53 31 54 30 55 29 56 28 57 27 CXA2125Q 58 +9V 26 59 25 60 24 61 23 62 22 63 21 64 20 +9V 47µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 22µF V Measurement point Fig. 1. Video system (d.c. test) d.c. measured from pins: 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 39, 41, 44, 46, 47, 48, 49, 55, 57, 59, 61, 63 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests. – 13 – CXA2125Q V +12V +12V +12V +12V +12V +12V +12V BC547B BC547B BC547B BC547B BC547B BC547B BC547B 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ Measurement point +9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V 75Ω 2.2µF +9V BC547B 75Ω 2.2µF 52 32 53 31 54 30 55 29 56 28 57 27 CXA2125Q 58 75Ω 2.2µF 75Ω +9V 2.2µF 75Ω 2.2µF 26 59 25 60 24 61 23 62 22 63 21 64 20 75Ω 2.2µF 75Ω 2.2µF 2.2µF 75Ω +9V 47µF 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 75Ω 2.2µF 8 75Ω 2.2µF 7 75Ω 2.2µF 6 2.2µF 5 75Ω 4 75Ω 2.2µF 3 75Ω 2.2µF 2 75Ω 2.2µF 75Ω 2.2µF 1 22µF Input signal Fig. 2. Video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, signal to noise) Signal applied to Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 Output signal measured from Pins 39, 41, 44, 46, 47, 48, 49 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. For tests requiring video measuring equipment with 75Ω input impedance, an external video line driver or buffer is used. 3. All video outputs are loaded with emitter follower during tests. – 14 – CXA2125Q +9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V 56kΩ 2.2µF +9V BC547B 56kΩ 2.2µF 52 32 53 31 54 30 55 29 56 28 57 56kΩ 56kΩ 27 CXA2125Q 58 2.2µF +9V 2.2µF 56kΩ 2.2µF 26 59 25 60 24 61 23 62 22 63 21 64 20 56kΩ 2.2µF 56kΩ 2.2µF 2.2µF +9V 47µF 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 56kΩ 2.2µF 8 56kΩ 2.2µF 7 56kΩ 2.2µF 6 2.2µF 5 56kΩ 4 56kΩ 2.2µF 3 56kΩ 2.2µF 2 56kΩ 2.2µF 56kΩ 2.2µF 1 22µF 1kHz Input signal V Measurement point Fig. 3. Video system (input impedance) Signal applied and measured from Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. Voltage measurements carried out with a high input impedance DVM. Typically 10GΩ. – 15 – 56kΩ CXA2125Q V +12V +12V +12V +12V +12V +12V +12V BC547B BC547B BC547B BC547B BC547B BC547B BC547B 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ +9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V +9V BC547B 52 32 53 31 54 30 55 29 56 28 57 27 CXA2125Q 58 +9V 26 59 25 60 24 61 23 62 22 63 21 64 20 +9V 47µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 22µF PSU Input signal Fig. 4. Video system (linearity) Signal applied to Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 Output signal measured from Pins 39, 41, 44, 46, 47, 48, 49 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests. – 16 – Measurement point CXA2125Q Output measurement point V HW mute +5V 1kΩ SW1 +9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V +9V BC547B 52 32 53 31 54 30 55 29 56 28 57 27 CXA2125Q 58 +9V 26 59 25 60 24 61 23 62 22 63 21 64 20 +9V 47µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 22µF V Input measurement point Fig. 5. Audio system (d.c. tests) d.c. measured from pins: 3, 5, 12, 14, 16, 18, 22, 24, 27, 29, 31, 32, 33, 34, 35, 36, 37, 40, 42 Note) All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. – 17 – CXA2125Q Measurement point 10kΩ +9V 10µF SW1 10µF 10µF 1kΩ 10µF 10µF 10µF +5V 10µF V HW mute 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V +9V BC547B 52 32 53 31 54 30 55 29 56 28 57 27 CXA2125Q 58 +9V 10µF 10µF 2.2µF 600Ω 2.2µF 600Ω 26 59 25 60 24 61 23 62 22 63 21 64 20 600Ω 2.2µF 600Ω 2.2µF +9V 47µF 6 7 8 9 10 11 12 13 14 15 16 17 18 19 600Ω 2.2µF 600Ω 2.2µF SCL SDA 22µF 5 600Ω 2.2µF 4 600Ω 2.2µF 3 600Ω 2.2µF 2 600Ω 2.2µF 1 Input signal Fig. 6. Audio system (gain, dynamic range, signal to noise, crosstalk, distortion, volume control) Signal applied to Pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29 Output signal measured from Pins 31, 32, 33, 34, 35, 36, 37, 40, 42 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. When muting audio using hardware mute, SW1 is closed. – 18 – CXA2125Q Measurement point +9V 10µF SW1 10µF 10µF 1kΩ 10µF 10µF 10µF +5V 10µF V HW mute 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 +12V +9V BC547B 52 32 53 31 54 30 55 29 56 28 57 27 CXA2125Q 58 +9V 10µF 10µF 2.2µF 600Ω 2.2µF 600Ω 26 59 25 60 24 61 23 62 22 63 21 64 20 600Ω 2.2µF 600Ω 2.2µF +9V 47µF 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SDA 600Ω 2.2µF 600Ω 2.2µF 600Ω 2.2µF SCL 22µF 4 600Ω 2.2µF 3 600Ω 2.2µF 2 600Ω 2.2µF 1 Input signal Fig. 7. Audio system (bandwidth) Signal applied to Pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29 Output signal measured from Pins 31, 32, 33, 34, 35, 36, 37, 40, 42 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. When muting audio using hardware mute, SW1 is closed. – 19 – 75Ω 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 VCR SCART 1µF 1µF 75Ω 75Ω 75Ω 1kΩ 1µF 1µF 47µF 2.2µF +12V VIN9 2.2µF 2.2µF RED 2.2µF CHROMA 2.2µF 2.2µF 2.2µF I 2C 20 21 22 23 24 25 26 27 28 29 30 31 32 22µF 560Ω 10µF 10µF 560Ω RF Modulator 10µF Phono Outputs L R 9 10 11 12 13 14 15 16 17 18 19 CXA2125Q CVBS LUMA 8 7 6 5 4 3 2 1 GREEN 64 63 62 61 60 59 58 57 56 55 54 53 52 10nF 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Digital Encoder FNC_VCR VIN1 VID_BIAS VIN2 VID_VCC VIN5 VCC_12V BC547B VREG_BASE FAST BLANK AUDIO R AUDIO L BLUE 10kΩ BC547B 1kΩ 10nF +12V VIN13 VREG_9V FBLK_IN2 FBLK_IN1 1kΩ FBLK_IN3 10µF AUD_VCC VIN14 RIN4 VIN15 LIN4 VIN16 AUD_GND 2.2µF 2.2µF 1µF RIN5 1µF 10kΩ LOGIC LIN5 FNC_TV ROUT2 LOUT2 75Ω BC547B +12V 10nF Analogue Satellite CVBS Audio R Audio L Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 75Ω 75Ω BC547B 10µF 2.2µF 2.2µF 2.2µF 75Ω BC547B TV_FBLANK FNC_AUX +12V 1kΩ VOUT4 VIN4 TV SCART 1kΩ VOUT1 RIN1 1kΩ VOUT2 VIN7 1kΩ VOUT3 LIN1 75Ω HW_MUTE VIN8 1µF VOUT6 VIN11 VID_GND BC547B DIG_GND 10µF SCL 75Ω 10µF VOUT5 560Ω 10µF SDA BC547B LTV VIN12 75Ω RTV RIN2 BC547B DIG_VCC LIN2 1µF 75Ω 560Ω VOUT7 VIN3 BC547B PHONO_L 10µF VIN6 20 18 16 14 12 10 8 6 4 2 LOUT1 RIN3 +12V 560Ω MONO 21 19 17 15 13 11 9 7 5 3 1 PHONO_R 560Ω 10µF VIN10 75Ω ROUT1 LIN3 – 20 – AUD_BIAS Application Circuit 10kΩ 21 19 17 15 13 11 9 7 5 3 1 AUX SCART 20 18 75Ω 16 14 75Ω 12 10 8 6 4 2 75Ω 75Ω 75Ω CXA2125Q CXA2125Q Description of Operation 1. Explanation of Video Section The video section comprises of 16 high impedance inputs switched through to 7 video outputs. A +6dB internal amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation which occurs at the external emitter follower stage used for driving video loads. All video outputs have an integrated 100Ω series protection resistor. The typical external configuration is shown in Fig. 1-1. VID_VCC = 9V Scart In +12V 75Ω 0.47µF Scart Out Switch 100Ω Amp 75Ω BC547B 75Ω Load 120kΩ 1kΩ Vbias 75Ω Vbias Video Element Fig. 1-1. Video Circuit Element: 6dB gain amplifier with external emitter follower Switching the Video Outputs Off Each video output can be individually turned off using the I2C. When turned off, the output dc voltage is approximately 0V and hence the current consumption of the external emitter followers is reduced. – 21 – CXA2125Q 2. Explanation of Audio System Inputs and Outputs The audio system consists of 5 stereo inputs, 3 stereo outputs and separate mono and phono outputs. The stereo outputs can be connected to any one of the 5 stereo inputs. All audio inputs have a –6dB attenuator except RIN1 and LIN1. Thus, the net gain of the audio system is 0dB, as the internal switch is followed by an audio amplifier having +6dB of gain. The stereo input RIN1/LIN1 does not have an input attenuator and therefore the net gain from input to output is +6dB. The output impedance of each audio amplifier is near zero, and can be capacitively coupled directly to the external scart circuit. The output circuitry is typically a 10µF capacitor, and an optional 560Ω series compliance resistor. Depending on the length and type of cable used in the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pF to 400pF) and mandatory 10kΩ resistor connected to ground. The customer may chose to place an alternative audio filter at the AV switch output. TV Audio Output The TV audio section is composed of an audio switch followed by two variable gain stages, corresponding to the coarse and fine electronic volume control. The coarse volume control gives a 0 to –56dB range in 8dB steps. Similarly the fine control gives a 0 to –7dB range in 1dB steps. The volume control section is followed by a switchable 0/+6dB amplifier which allows compensation for low level signals from a DAC. Finally, a mono switch allows the mixed R + L signal to be switched to the R and L output channels. (Fig. 2-1) TV Audio Output 1µF RIN1 3 RIN2 12 –6dB Audio RIN3 16 Source RIN4 22 –6dB RIN5 27 –6dB LIN1 Volume Control 8dB 1dB LIN3 18 –6dB LIN4 24 –6dB LIN5 29 –6dB ×2 40 560Ω 0/6dB 8dB 1dB Scart Pin 10µF C ZCD 5 –6dB 35 PHONO_R RTV –6dB LIN2 14 ×2 0/6dB MONO SWITCH ×2 42 LTV Optional Low Pass Filter ×2 37 PHONO_L Mute Fig. 2-1. TV Audio Output TV Mute The I2C mute function acts only on the TV, phono and mono audio circuit. Audio mute can be implemented after a audio zero cross detection to reduce click noise, or immediately depending on the I2C setting of ZCD. It can be seen from the I2C write format that the same mute bit occurs in DATA 1 and DATA 7. This allows the software to action an immediate mute, make any suitable changes to the audio source or electronic volume control and after a minimum period of 6 × 90µs (540µs) un-mute the output buffer. Such a period provides ample time to allow any transient ac voltages to settle during an audio source change. – 22 – CXA2125Q Zero Cross Detector (ZCD) The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. The change volume or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. The zero cross detection circuit can be turned off by setting the "ZCD" bit low in the I2C write mode. Hardware Mute A hardware mute pin is provided which will mute all audio outputs when the pin voltage exceeds 2.5V. This muting is instantaneous. VCR and AUX Output The outputs ROUT1, 2 and LOUT1, 2 have a fixed gain of 0dB from the input. If any attenuation is required then it is possible to insert a series resistance on the input. (Fig. 2-2) VCR and AUX Audio Circuit 1µF RIN1 3 RIN2 12 –6dB Audio RIN3 16 Source RIN4 22 –6dB RIN5 27 –6dB LIN1 ×2 –6dB ×2 –6dB LIN3 18 –6dB LIN4 24 –6dB LIN5 29 –6dB Scart Pin • 31 560Ω 10µF C 5 LIN2 14 34 ROUT1/2 MONO SWITCH 36 • 32 LOUT1/2 Optional Low Pass Filter Mute Fig. 2-2. VCR and AUX Audio Output Phono Outputs There is a stereo phono output which carries the same signal as the TV output. This is typically used for connection to a hi-fi. The user may connect an external attenuator which is a.c. coupled to the outputs. – 23 – CXA2125Q I2C Data Interface Table IC Control Data Format S Slave address A S: Start condition DATA1 A DATA2 A: Acknowledge A DATA3 A DATA4 A DATAn A P P: Stop condition Address = 90H I2C Data Structure (write mode) Address b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 0 0 0 = Write TV Aud Mute Z.C.D EVC Data1 EVF Data2 Not used Not used Vid_Switch 1 TV Aud_Switch 1 TV Data3 Vout5 Mute Not used Vid_Switch 2 VCR Aud_Switch 2 VCR Data4 Not used Not used Vid_Switch 3 AUX Aud_Switch 3 AUX Data5 Not used Not used FBLK Data6 Not used Vout7 on/off Vout6 on/off Vout5 on/off Vout4 on/off Vout3 on/off Vout2 on/off Vout1 on/off Data7 TV Aud Mute TV Aud Gain mono AUX mono VCR mono TV Not used Not used Not used Key EVC: EVF: TV Aud Mute: Z.C.D: Vid_Switch 1: Vid_Switch 2: Vid_Switch 3: Aud_Switch 1: Aud_Switch 2: Aud_Switch 3: FNC: FBLK: LOGIC: FNC LOGIC Electronic Volume Course (8dB steps) Electronic Volume Fine (1dB steps) TV Audio mute. Controls the TV audio output buffer. (Same bit appears in data 1 & 7) Zero cross detector active. When ZCD = 1 volume and mute change at zero cross. Selects the input video sources for Vout1, Vout2, Vout3, Vout4 Selects the input video sources for Vout5, Vout6 Selects the input video sources for Vout7 Selects one of 5 stereo inputs for RTV, LTV, PHONO_L, PHONO_R, MONO Selects one of 5 stereo inputs for Rout1, Lout1 Selects one of 5 stereo inputs for Rout2, Lout2 Video function switch control Video Fast Blanking control Logic outputs (open collector). 0 = high impedance. 1 = current sink mode. – 24 – CXA2125Q I2C Data Format (read mode) S Slave address A DATA8 NA P NA: No Acknowledge I2C Data Structure (read mode) b7 b6 b5 b4 b3 b2 b1 b0 Address 1 0 0 1 0 0 0 1 = Read Data x x ZC Status P.O.D. Key FNC_VCR: FNC_AUX: ZC Status: P.O.D.: FNC_AUX FNC_VCR At Pin 64, AV switch monitors the voltage of pin 8 from VCR scart, and records status. At Pin 1, AV switch monitors the voltage of pin 8 from AUX scart, and records status. ZC Status = 1 indicates that zero cross condition has been achieved after the ZCD is turned on. Power On Detect. P.O.D. = 1 when DIG_VCC voltage rises above a threshold level of approximately 5V. – 25 – CXA2125Q 3. Video Input I2C Control Switch 1 (TV Output) Data 2 Bits 3, 4, 5 Switch setting Vout1 (B) Vout2 (Green) Vout3 (R/C) Vout4 (CVBS/Y) 0 xx000xxx VIN1 VIN4 VIN7 VIN11 Digital encoder 1 xx001xxx Bias Bias VIN8 VIN12 Digital encoder 2 xx010xxx VIN2 VIN5 VIN9 VIN13 VCR 3 xx011xxx VIN3 VIN6 VIN10 VIN14 AUX 4 xx100xxx Bias Bias VIN7 VIN4 Digital encoder 5 xx101xxx Bias Bias Bias VIN15 TV 6 xx110xxx Bias Bias Bias VIN16 Analogue satellite 7 xx111xxx Bias Bias Bias Bias Note) After power on all TV outputs are off and muted. Switch 2 (VCR Output) Switch setting Data 3 Bits 3, 4, 5 Vout5 (Chroma (C)) Vout6 (CVBS/Y) Comment 0 xx000xxx VIN7 VIN11 Digital encoder 1 xx001xxx VIN8 VIN12 Digital encoder 2 xx010xxx VIN9 VIN13 VCR 3 xx011xxx VIN10 VIN14 AUX 4 xx100xxx VIN7 VIN4 Digital encoder 5 xx101xxx Bias VIN15 TV 6 xx110xxx Bias VIN16 Analogue satellite 7 xx111xxx Bias Bias Video mute Note) After power on VCR outputs are off and muted. VCR Chroma Mute Data 3 Bit 7 0 x x x x x x x = Vout5 active. Connected to input specified in above table. 1 x x x x x x x = Vout5 muted (the output dc bias still remains). – 26 – Comment Video mute CXA2125Q Switch 3 (AUX Output) Data 4 Switch setting Vout7 (CVBS) Bits 3, 4, 5 Comment 0 xx000xxx VIN11 Digital encoder 1 xx001xxx Bias 2 xx010xxx VIN13 VCR 3 xx011xxx VIN14 AUX 4 xx100xxx VIN4 Digital encoder 5 xx101xxx VIN15 TV 6 xx110xxx VIN16 Analogue satellite 7 xx111xxx Bias Video mute Video mute Note) After power up the AUX video outputs are off and muted. Standby Mode Control Data 6 Bits 0, 1, 2, 3, 4, 5, 6 Each video output can be individually turned off using data byte 6. 0 = Video output off 1 = Video output on Note) When switched off, the video outputs are high impedance to prevent d.c. driving of the external emitter follower stage. The reduction of overall current consumption will depend on how many video outputs are turned off. After power on all video outputs are in the off state. – 27 – CXA2125Q 4. Fast Blanking Operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode 2. RGB mode Scart pin voltage = 0 to 0.4V Scart pin voltage = 1 to 3.0V Threshold voltage is approximately 0.75V at the scart input. Fast Blanking I2C Control In the CXA2125Q, there are three fast blanking inputs, one associated with the Digital Encoder input (FBLANK_IN1), one with the VCR RGB/CVBS input (FBLANK_IN2), and another associated with the AUX RGB/CVBS input (FBLANK_IN3). These can be selected by I2C. In addition to the two blanking inputs, the fast blank pin output can be set to a constant 0V or 5V by means of the I2C control. Hence there are four possible states. These are controlled according to the following table. FBLK Control Data 5 Bits 3, 4, 5 I2C Setting Fast Blank Output 0 xx000xxx 0V 1 xx001xxx +5V 2 xx010xxx Same level as Fast Blank in 1 (0/+5V) 3 xx011xxx Same level as Fast Blank in 2 (0/+5V) 4 xx100xxx Same level as Fast Blank in 3 (0/+5V) 5 xx101xxx +5V 6 xx110xxx +5V 7 xx111xxx +5V Note) After power on the output is 0V. Fast Blank output circuit The output requires an external buffer stage to drive the required 75Ω scart termination. The levels at the IC output are 0V and +5V. VCC Fast Blank 0V/5V 75Ω Scart line 16 1kΩ TV 75Ω CXA2125Q Fig. 4-1. Fast Blanking Interface to TV SCART – 28 – CXA2125Q 5. Function Switch, FNC. The function switch facility is designed to read the status of the SCART function pin 8 from the VCR input. The read register holds the status of the input function lines. The function output is controlled by I2C and is used to change the voltage on the function line to the TV. The output can be connected directly to the scart pin. (Fig. 5-1) Read Mode Reads the status of the inputs FNC_VCR and FNC_AUX. Read Data8 Input Pin Voltage FNC_VCR/FNC_AUX Level (SCART Defn.) b1/b3 b0/b2 0 to +2V (default) (Internal TV) 0 0 +4.5 to +7V (16:9 External) 0 1 +9.5 to +12V (4:3 External) 1 1 Write Mode Controls the voltage at the TV function line (pin 8) I2C Control (Data 5) Mode/(Typical pin Voltage) 0 xxxxx00x Internal TV/(1V) 1 xxxxx01x External scart input 16:9 mode/(6V) 2 xxxxx10x External scart input 4:3 mode/(11V) 3 xxxxx11x External scart input 4:3 mode/(11V) Note) After power on output is internal TV mode ie. 0V at the pin. > 10V > 4.5V < 7V < 2V FNC_TV Scart Pin 8 10kΩ CXA2125Q Fig. 5-1. TV Function Switch Output – 29 – CXA2125Q 6. Logic Output A single logical output pin is provided. This is controlled via the I2C and is an open collector output. Specification I2C bit 0 = open collector/high output impedance I2C bit 1 = Vsat (to 0.2V) Vmax at logic pin = 12V Imax during current sink = 1mA LOGIC I2C Open collector logic outputs Logic cct. Fig. 6-1. Logic Output Interface – 30 – CXA2125Q 7. I2C Audio Signal Control Outputs TV, VCR, AUX Switch Setting Data 2, 3, 4 Bits 0, 1, 2 RTV, ROUT1, ROUT2 LTV, LOUT1, LOUT2 0 xxxxx000 Rin1 Lin1 1 xxxxx001 Rin2 Lin2 2 xxxxx010 Rin3 Lin3 3 xxxxx011 Rin4 Lin4 4 xxxxx100 Rin5 Lin5 5 xxxxx101 Audio mute Audio mute 6 xxxxx110 Audio mute Audio mute 7 xxxxx111 Audio mute Audio mute Note) After power on the audio outputs are muted. Volume Control Fine Setting Data 1 Bits 2, 3, 4 Volume Fine Control Gain 0 xxx000xx 0dB 1 xxx001xx –1dB 2 xxx010xx –1dB 3 xxx011xx –3dB 4 xxx100xx –4dB 5 xxx101xx –5dB 6 xxx110xx –6dB 7 xxx111xx –7dB Volume Control Coarse Setting Data 1 Bits 5, 6, 7 Gain 0 000xxxxx 0dB 1 001xxxxx –8dB 2 010xxxxx –16dB 3 011xxxxx –24dB 4 100xxxxx –32dB 5 101xxxxx –40dB 6 110xxxxx –48dB 7 111xxxxx –56dB – 31 – CXA2125Q TV output amplifier Data 7 Bit 6 x 0 x x x x x x = 0dB x 1 x x x x x x = +6dB Note) After power on the gain is set to 0dB. TV Mono Switch Data 7 Bit 3 x x x x 0 x x x = Normal stereo output x x x x 1 x x x = Mono signal switched onto R + L line. VCR Mono Switch Data 7 Bit 4 x x x 0 x x x x = Normal stereo output x x x 1 x x x x = Mono signal switched onto R + L line. AUX Mono Switch Data 7 Bit 5 x x x 0 x x x x = Normal stereo output x x x 1 x x x x = Mono signal switched onto R + L line. Mute and Zero Cross Operation For TV, Phono and mono outputs. There are two mute control bits in the bus map to allow the TV outputs to be muted before the channel change instruction occurs. The normal structure for a click free audio channel change is as follows: Data 1 Mute the TV audio output with the ZCD switched on. Data 2 Change the TV audio source. Data 7 Un-mute the TV audio output again with the ZCD switched on. TV Aud Mute Data 1 Bit 1 Data 7 Bit 7 ZCD Data 1 Bit 0 0 0 Un-mute immediately 0 1 Un-mute on next zero cross 1 0 Mute immediately 1 1 Mute on next zero cross Note) After power on TV Mute and ZCD are set to 0. – 32 – RTV, LTV, Phono_R, Phono_L, Mono outputs CXA2125Q Notes on operation 1) Supply de-coupling capacitors, 10nF and 4.7µF in parallel should be inserted as close to the supply pins, 20, 38, 60 as possible. 2) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) Attention should be given to the electrolytic capacitors on the input and output signal pins. As the pin's voltage is between 3.7V and 4.7V dc the positive terminal on the capacitor should be orientated towards the pin. 4) The audio outputs may be muted at any time after power up by connecting the HW_MUTE pin (45) to a voltage > 2.5V and < 9V. 5) When driving video loads with impedance = 75Ω an emitter follower or video line driver is required to be connected at the video outputs as shown in the application schematic. Stray capacitance on pins Vout1-8 must be kept to a minimum by placing loads as close to the pins as possible. 6) The supply voltage on pin 58 "VCC_12V" should not exceed +12V. If the supply has poor regulation then a series diode or zener diode may be used to limit the voltage at this pin. – 33 – CXA2125Q Typical audio output distortion Inputs RIN1, LIN1 selected Inputs RIN2, 3, 4, 5/LIN2, 3, 4, 5 selected THD [%] 0.1 0.1 0.01 0 0.5 1 Input [Vrms] 0.0001 1.5 0 1 2 Input [Vrms] Audio frequency characteristics 4 2 0 –2 Input = 0.3Vp-p –4 –6 100 1k 8 Video Output/Input gain [dB] 0.001 0.01 0.001 Audio Output/Input gain [dB] THD [%] 1 10k 100k Frequency [Hz] 1M 10M Video frequency characteristics 6 4 2 0 100k 10M 1M Frequency [Hz] – 34 – 50M 3 3.3 CXA2125Q Package Outline Unit: mm 64PIN QFP(PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 0.15 64 20 1 16.3 32 + 0.4 14.0 – 0.1 52 17.9 ± 0.4 33 + 0.2 0.1 – 0.05 19 + 0.35 2.75 – 0.15 + 0.15 0.4 – 0.1 1.0 0.2 M 0° to10° 0.8 ± 0.2 51 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING SONY CODE QFP-64P-L01 LEAD TREATMENT EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.5g JEDEC CODE – 35 –