SONY CXA3017R

CXA3017R
Decoder/Driver/Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXA3017R is an IC designed to drive the color
LCD panels LCX005BK/BKB, LCX009AK/AKB,
LCX024AK/AKB, LCX027AK/AKB and DCX501BK.
This IC allows two-panel simultaneous and switching
drive by simultaneously outputting the timing pulses
for the LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB,
LCX027AK/AKB and DCX501BK.
This IC greatly reduces the number of peripheral
circuits and parts by incorporating an RGB decoder,
driver, and timing generator for video signals onto a
single chip. This chip has a built-in serial interface
circuit and electronic attenuators which allow various
settings to be performed by microcomputer control,
etc.
Features
• Color LCD panel LCX005BK/BKB, LCX009AK/AKB,
LCX024AK/AKB, LCX027AK/AKB and DCX501BK driver
• Supports two-panel simultaneous and switching
drive using the LCX005BK/BKB, LCX009AK/AKB,
LCX024AK/AKB, LCX027AK/AKB and the DCX501BK
• Supports NTSC and PAL systems
• Supports 16:9 wide display
(letter box and pulse elimination display)
• Supports composite inputs, Y/C inputs and Y/color
difference inputs
• Serial interface circuit
• Electronic attenuators (D/A converter)
• VCO
• BPF, trap and delay line
• Sharpness function
• 2-point γ correction circuit
• R, G, B signal delay time adjustment circuit
• Polarity inversion circuit (line inverted mode)
• Supports external RGB input
• D/A output pin (0 to 3V, 8 levels)
• Supports AC drive for LCD panel during no signal
64 pin LQFP (Plastic)
Applications
• Compact LCD monitors
• LCD viewfinders
• Compact liquid crystal projectors, etc.
Structure
Bi-CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC1 – GND1 6
V
VCC2 – GND2 14
V
VCC3 – GND3 14
V
VDD1, 2 – VSS 4.5
V
• Analog input pin voltage VINA
–0.3 to VCC1 V
• Digital input pin voltage VIND –0.3 to VDD1 + 0.3V
• Operating temperature Topr
–15 to +75 °C
• Storage temperature
Tstg
–40 to +125 °C
∗
1
• Allowable power dissipation
PD (Ta ≤ 75°C)
Approximately 350mW
Operating Conditions
Supply voltage VCC1 – GND1
VCC2 – GND2
VCC3 – GND3
VDD1, 2 – VSS
∗1 With substrate
2.7 to 3.6
11.0 to 13.5
11.0 to 13.5
2.7 to 3.6
V
V
V
V
Size: 30 × 30 × 1.6mm
Material: Glass fabric base epoxy
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98Y29-PS
CXA3017R
38
37
36
35
34
GND3
VDD2
39
+12V
DWN
40
RGT1
41
FB PSIG
42
GND2
GND3
43
PSIG
44
+12V
VCC3
G OUT
45
B OUT
FB G
46
FB B
R OUT
47
GND2
FB R
48
VCC2
SIG.CENTER
Block Diagram
33
+3V
I/F
Buf
Buf
Buf
Buf
VCC1 49 +3.0V
D/A
BLKLIM
WHTLIM
32 DA OUT
31 VD
VXO OUT 50
POL SW
INT/EXT
VXO IN 51
PAL ID
COLOR
DEMOD
EXT COLOR
& BALANCE
APC 52
POL SW
30 EN2
PSIGBRIGHT
PSIG-BRT
WIDE
VGATE
VJOG
29 EN1
PALSW
HUE
B-Y IN 53
INT/EXT
SUBBRIGHT
LPF
BRIGHT
MATRIX
USER
BRIGHT
R-BRT
B-BRT
FRP
28 XEN1
CLAMP
R-Y IN 54
APC
C OUT 55
VXO
PS
HUE
HUE
V REG 56
REG
COLOR CONT
26 VCK2
USERBRT
PALSW
HUE
COLOR
BRIGHT
CONT
R-BRT
B-BRT
γ-1
VCO
CONTRAST
S/H
R-CONT
ACC DET
SUB
CONTRAST
RESET 58
B-CONT
KILLER
R G B
γ -1
BPF
VPAL
VWIN
CONT
COLOR
C IN 57
Y IN 59
27 VCK1
BRIGHT
γ-2
PSIG-BRT
R-CONT
B-CONT
PICTURE
USER-BRT
BLKLIM
WHTLIM
D/A
25 VCK3
24 VCK4
23 VST
22 XVST
GAMMA
ACC AMP
γ -2
PICTURE
HAFC
PLL-COUNTER
& DECODER
PIC CONT
FILT ADJ
HD
EXT SW
SYNC IN 61
HCNT
H-PULSE
CLP
BGP
SBLK
VSEP TC 62
CLAMP
DL1
TRAP
F0 ADJ 63
H.FILTER
21 HD
20 PCG
19 XPCG
HGATE
H-SKEW DET
PD
18 HCK1
V SEP
SYNC SEP
VCO
GND1 64 GND1
VCO
17 HCK2
SERIAL BAS I/F
TRAP
VDD1
LOAD
DATA
10
11
12
13
14
15
XHST1
EXT B
9
HST1
EXT G
8
HST2
7
CLR
6
BLK
5
TEST1
4
RPD
3
SCLK
2
EXT R
+3V
1
–2–
VSS
16
VSS
TEST2 60
CXA3017R
Pin Description
Pin
No.
Symbol
I/O
Description
1
EXT R
I
External digital R input
2
EXT G
I
External digital G input
3
EXT B
I
External digital B input
4
TRAP
O
External trap connection
5
VDD1
6
LOAD
I
Serial interface load input
7
DATA
I
Serial interface data input
8
SCLK
I
Serial interface clock input
9
RPD
O
Phase comparator output
10
TEST1
I
Test (Connect to GND.)
11
BLK
O
BLK pulse output
12
CLR
O
CLR pulse output
13
HST2
O
H start pulse 2 output
14
HST1
O
H start pulse 1 output
15
XHST1
O
XH start pulse 1 output (reverse polarity of HST1)
16
VSS
17
HCK2
O
H clock pulse 2 output
18
HCK1
O
H clock pulse 1 output
19
XPCG
O
XPCG pulse output (reverse polarity of PCG)
20
PCG
O
PCG (precharge) pulse output
21
HD
O
HD pulse output
22
XVST
O
XV start pulse output (reverse polarity of VST)
23
VST
O
V start pulse output
24
VCK4
O
V clock pulse 4 output
25
VCK3
O
V clock pulse 3 output
26
VCK2
O
V clock pulse 2 output
27
VCK1
O
V clock pulse 1 output
28
XEN1
O
XEN pulse 1 output (reverse polarity of EN1)
29
EN1
O
EN pulse 1 output
30
EN2
O
EN pulse 2 output
31
VD
O
VD pulse output
32
DA OUT
O
DAC output
33
VDD2
34
DWN
Input pin processing
for open status
Digital 3V power supply for oscillation cell
Digital 3V GND
Digital 3V power supply
O
DCX501BK up/down inverted display switching
(open collector output)
–3–
L
CXA3017R
Pin
No.
Symbol
I/O
Description
35
RGT1
O
DCX501BK right/left inverted display switching
(open collector output)
36
FB PSIG
I
PSIG signal DC voltage feedback circuit capacitor connection
37
GND3
38
PSIG
39
VCC3
40
B OUT
O
B signal output
41
FB B
I
B signal DC voltage feedback circuit capacitor connection
42
GND2
43
G OUT
O
G signal output
44
FB G
I
G signal DC voltage feedback circuit capacitor connection
45
R OUT
O
R signal output
46
FB R
I
R signal DC voltage feedback circuit capacitor connection
47
VCC2
48
SIG.CENTER
49
VCC1
50
VXO OUT
O
VXO output
51
VXO IN
I
VXO input
52
APC
O
APC detective filter connection
53
B-Y IN
I
B-Y color difference signal input
54
R-Y IN
I
R-Y color difference signal input
55
C OUT
O
Chroma signal output
56
V REG
O
Constant voltage capacitor connection
57
C IN
I
Chroma signal input
58
RESET
I
System reset
59
Y IN
I
Y signal input
60
TEST2
I
Test (Connect to GND.)
61
SYNC IN
I
Video input for sync separation
62
VSEP TC
63
F0 ADJ
64
GND1
Input pin processing
for open status
Analog 12V GND for PSIG
O
PSIG output
Analog 12V power supply for PSIG
Analog 12V GND
Analog 12V power supply
I
R, G, B and PSIG output DC voltage adjustment
Analog 3V power supply
Capacitor connection for vertical sync separation
(or external VSYNC input)
O
Internal filter adjusting resistor connection
Analog 3V GND
∗ DWN: DOWN SCAN and UP SCAN
RGT: RIGHT SCAN and LEFT SCAN
–4–
L
CXA3017R
Analog Block Pin Description
Pin
No.
1
Symbol
Pin voltage
EXT-R
Equivalent circuit
Description
VCC1
25µA
1
2
EXT-G
—
300
2
3
50k
3
1.1V
GND1
EXT-B
VCC1
75µA
1k
4
TRAP
1.0V
300
4
200µA
GND1
External digital signal inputs.
There are two thresholds: Vth1
(= 1.0V) and Vth2 (= 2.0V).
When one of the RGB signals
exceeds Vth1, all of the RGB
outputs go to black level; when
an input exceeds Vth2, only
the corresponding output goes
to white level.
Connect these pins to GND
when not used.
External trap connection.
Connect the trap between this
pin and GND to eliminate the
chroma component.
Leave this pin open when
using Y/C and Y/color
difference mode.
VDD2
50k
50k
32
DA OUT
0.2 to 2.9V
32
50k
DAC output.
8-level, 7-step DC voltage from
approximately 0.2 to 2.9V is
output from this pin.
VSS
34
DWN
VCC2
—
500
34
35
35
RGT1
36
FB PSIG
41
—
VCC1
1k
FB B
36
1.5V
44
GND2
41
44
FB G
1k
46
46
FB R
37
GND3
DCX501BK up/down and
right/left inversion switching.
These pins are open collector
outputs, so first connect a
100kΩ resistor between these
pins and the panel VDD (15.5V)
and then connect to the
DCX501BK.
100k
Smoothing capacitor
connection for the feedback
circuit of R, G, B and PSIG
output DC level control.
Use a low-leakage capacitor
because of high impedance.
GND2
GND for the PSIG circuit.
0V
–5–
CXA3017R
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC3
150
38
PSIG
VCC2
2
PSIG signal output.
38
20
GND3
39
VCC3
40
B OUT
43
G OUT
12V power supply for the PSIG
circuit.
12V
VCC2
VCC2
2
40
20
RGB signal outputs.
43
20
45
40µA
45
R OUT
42
GND2
0V
12V GND.
47
VCC2
12V
12V power supply.
GND2
VCC2
150k
48
SIG.
CENTER
VCC2
2
10k
300
48
150k
GND2
49
VCC1
RGB/PSIG output DC voltage
control.
When used with a VCC2 or
VCC3 of 12V or more, or when
used with a signal center
voltage of other than VCC2/2 or
VCC3/2, apply voltage of 5.2 to
6.5V from an external source.
3.0V power supply.
3.0V
VCC1
200
50
VXO OUT
1.2V
50
370µA
VXO output.
Leave this pin open when
using Y/color difference mode.
GND1
VCC1
500
VXO input.
Leave this pin open when
using Y/color difference mode.
51
51
VXO IN
1.6V
10k
3.5k
10p
3.5k
GND1
–6–
1.6V
CXA3017R
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
APC detective filter
connection.
Leave this pin open when
using Y/color difference mode.
500
1k
52
APC
1.7V
52
GND1
53
VCC1
B-Y IN
4k
10k
5k
53
—
1k
54
54
4k 40µA
R-Y IN
30µA
GND1
VCC1
55
C OUT
1.2V
55
50µA
GND1
VCC1
V REG
2.0V
Color adjusted chroma signal
output during D-PAL. The
output level is tripled in order
to compensate for the
attenuation of the external U/V
separation delay line. The
standard burst output level is
approximately 200mVp-p.
Leave this pin open in modes
other than D-PAL.
Smoothing capacitor
connection for the internally
generated constant voltage
source circuit.
Connect a capacitor of 1µF or
more.
56
56
Y/color difference signal inputs.
When using color difference
input, the standard signal input
level is 0.3Vp-p (75% color bar)
and the clamp level is
approximately 1.7V.
During D-PAL, the COUT (Pin
55) chroma signal is U/V
separated and then input.
Input at low impedance (75Ω or
less).
18.5k
30k
GND1
VCC1
15µA
50k 5p
57
C IN
—
57
50k
10p
30µA
Video signal input when using
composite signal input.
Chroma signal input when
using Y/C signal input.
Leave this pin open when
using Y/color difference mode.
GND1
∗ D-PAL is a demodulation method that uses an external delay line during demodulation.
S-PAL is a demodulation method that internally processes chroma demodulation.
–7–
CXA3017R
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
VDD1
2µA
TG block system reset pin.
The system is reset when this
pin is connected to GND.
Connect a capacitor between
this pin and GND.
300
58
RESET
—
58
1k
GND1
VCC1
1k
59
Y IN
1.6V
59
20µA
Y signal input.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
Input at low impedance (75Ω
or less).
GND1
VDD1
1k
61
SYNC IN
1k
1.6V
61
500
0.6µA
12µA
GND1
Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (100% white level
from the sync tip).
Input at low impedance (75Ω
or less).
VDD1
500
1k
62
VSEP TC
1.7V
Capacitor connection for
vertical sync separation.
62
1k
20µA
20µA
GND1
VCC1
200
63
F0 ADJ
1.5V
63
5p
500 5p
GND1
500
Filter reference current
generation.
Connect resistance of 15 kΩ
between this pin and GND1 to
adjust the internal filters using
the outflow current value.
Leave this pin open when
using Y/C or Y/color difference
mode.
64
GND1
0V
3.0V GND.
60
TEST2
0V
Test. Connect to GND.
–8–
CXA3017R
Digital Block Pin Description
Pin
No.
Symbol
5
VDD1
6
LOAD
Pin voltage
Equivalent circuit
Description
Power supply for VCO.
6
1k
7
7
DATA
8
SCLK
9
RPD
Phase comparator output.
33
VDD2
Power supply for digital block.
10
TEST1
Test. Connect to GND.
11
BLK
12
CLR
13
HST2
11
14
HST1
12
15
XHST1
17
HCK2
18
HCK1
Serial bus inputs.
8
VSS
13
14
15
17
18
19
XPCG
20
PCG
20
21
HD
21
22
XVST
23
VST
24
VCK4
19
VDD2
Digital block outputs.
22
23
24
25
26
25
VCK3
26
VCK2
28
27
VCK1
29
28
XEN1
29
EN1
30
EN2
31
VD
VSS
27
30
31
–9–
CXA3017R
Setting Conditions for Measuring Electrical Characteristics
Use the Electrical Characteristics Measurement Circuit on page 30 while measuring electrical characteristics.
Also, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below.
Setting 1. System reset
After turning on the power, set SW58 to ON and start up V58 from GND in order to activate the TG
block system reset. (See Fig. 1-1.)
The serial bus is set to the default values.
Setting 2. Horizontal AFC adjustment
Input SIG5 (VL = 0mV) to (A) and adjust serial bus register VCO so that the TP9 phase comparison
output waveform (near VSYNC) is horizontal.
SW48 = OFF, SW58 = ON, V58 = 3.0V
(See Fig. 1-2.)
Note) When measuring a band of 2MHz or more such as Y signal frequency response or sharpness characteristics
among the items being measured, the measurement must be made with the sample-and-hold circuit set to
through (sample and hold not performed) by the serial bus.
VDD
V58 (PWRST)
TR
TR > 10µs
Fig. 1-1. System reset
SIG5
VSYNC
VSYNC
TP9
approximately 1/2VDD
TP9
Adjust to a horizontal waveform.
Fig. 1-2. Horizontal AFC adjustment
– 10 –
CXA3017R
Electrical Characteristics — DC Characteristics
Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 3.0V, VCC2 = VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS = 0V, Ta = 25°C
SW1/SW2/SW3 = A, SW53/SW54/SW57 = B
SW58 = ON, SW48 = OFF
V58 = 3.0V
Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified items should be set to the
default settings.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
ICC11
Input SIG4 to (A) and SIG2 (0dB) to (B), and measure
the ICC1 current value. COMP input mode.
SW57 = A
27
34
41
mA
ICC12
Input SIG4 to (A) and SIG2 (0dB) to (B), and measure
the ICC1 current value. Y/C input mode.
SW57 = A
24
30
37
mA
ICC13
Input SIG4 to (A), (D) and (E) and measure the ICC1
current value. Y/color difference input mode.
SW53 = SW54 = A
19
25
30
mA
ICC2
Input SIG4 to (A) and SIG2 (0dB) to (B), and measure
the ICC2 current value.
SW57 = A
6
8
10
mA
IDD1
Input SIG4 to (A) and SIG2 (0dB) to (B), and measure
the IDD3 and IDD4 current values.
IDD1 = IDD3 + IDD4, LCX009AK/AKB
SW57 = A
8.5
11
13.5
mA
IDD2
Input SIG4 to (A) and SIG2 (0dB) to (B), and measure
the IDD3 and IDD4 current values.
IDD2 = IDD3 + IDD4, LCX005BK/BKB
SW57 = A
7.5
10
12.5
mA
0.3VDD
V
Current characteristics
Current
consumption
VCC1
Current
consumption
VCC2, 3
Current
consumption
VDD1, 2
Digital block I/O characteristics
Low level input
voltage
VIL
Digital block input pins∗1
SW57 = A
(A) = SIG4, (B) = SIG2
High level input
voltage
VIH
Digital block input pins∗1
SW57 = A
(A) = SIG4, (B) = SIG2
High level output
voltage
Low level output
voltage
V
VDD = 3.0V
SW57 = A
IOH = –1.2mA∗2
(A) = SIG4, (B) = SIG2
2.8
V
VDD = 2.7V
SW57 = A
IOH = –1.2mA∗2
(A) = SIG4, (B) = SIG2
2.6
V
VOH1
VOL1
0.7VDD
IOL = 1.2mA∗2
SW57 = A
(A) = SIG4, (B) = SIG2
0.3
V
∗1 Digital block input pins: SCLK, DATA, LOAD
∗2 Output pins except RPD: BLK, CLR, HST2, HST1, XHST1, HCK2, HCK1, XPCG, PCG, HD, XVST, VST,
VCK4, VCK3, VCK2, VCK1, XEN1, EN1, EN2, VD
– 11 –
CXA3017R
Electrical Characteristics — AC Characteristics
Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 3.0V, VCC2 = VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS = 0V, Ta = 25°C
SW1, SW2, SW3 = A SW53, SW54, SW57 = B
SW58 = ON SW48 = OFF
V58 = 3.0V
Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified items should be set to the
default settings.
Unless otherwise specified, measure the non-inverted outputs for TP40, TP43 and TP45.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
Y signal system
Video maximum
gain
GV
Input SIG4 to (A) and measure the ratio between the
output amplitude (white-black) and input amplitude at
TP43.
19
21
23
dB
Contrast
characteristics
TYP
GCNTTP
Input SIG4 to (A) and measure the ratio between the
output amplitude (white-black) and input amplitude at
TP43.
14
16
18
dB
Contrast
characteristics
MIN
GCNTMN
Input SIG4 to (A) and measure the ratio between the
output amplitude (white-black) and input amplitude at
TP43.
–3
1
3
dB
FCYYC
Y signal frequency
response
FCYCMN
FCYCMP
Picture quality
adjustment
variable amount 1
(Y/C input)
LCX009AK/AKB
Picture quality
adjustment
variable amount 2
(Y/C input)
LCX005BK/BKB
Picture quality
adjustment
variable amount 3
(composite input)
LCX005BK/BKB
Picture quality
adjustment
variable amount 4
(composite input)
LCX009AK/AKB
Assume the output amplitude at
TP43 when SIG1 (0dB, no burst,
100kHz) is input to (A) as 0dB.
Vary the frequency of the input
signal to obtain the frequency
with an output amplitude of –3dB.
CL = 400pF
GSHP1X
GSHP1N
GSHP2X
Y/C input
5.0
MHz
Composite input
(NTSC)
2.5
MHz
Composite input
(PAL)
3.0
MHz
2.5MHz MAX
11
Assume the output amplitude at
TP43 when SIG7 (100kHz) is
2.5MHz MIN
input to (A) as 0dB. Obtain the
amount by which the output
amplitude of SIG7 (2.5MHz or
1.8MHz MAX
1.8MHz) changes when PICTURE
is set to the MAX and MIN values.
GSHP2N
1.8MHz MIN
GSHP3X
1.8MHz MAX
GSHP3N
GSHP4X
Assume the output amplitude at
TP43 when SIG7 (100kHz) is
1.8MHz MIN
input to (A) as 0dB. Obtain the
amount by which the output
amplitude of SIG7 (1.8MHz or
2.5MHz MAX
2.5MHz) changes when PICTURE
is set to the MAX and MIN values.
GSHP4N
2.5MHz MIN
– 12 –
14
–3
11
2
dB
dB
–2
dB
dB
9
–6
dB
dB
11
–5
6
0
14
–1
8
dB
–3
dB
CXA3017R
Symbol
Item
Carrier leak
(residual carrier)
CRLEKY
Conditions
Y signal I/O delay
time
TDYCMP
Typ.
Input SIG2 (0dB) to (A). Using a spectrum analyzer,
measure the input and the 3.58MHz or 4.43MHz
component of TP43, and obtain
CRLEKY = 150mV × 10∆CLK/20
using their difference ∆CLK.
TDYYC
TDYCMN
Min.
Input SIG9 to (A). Measure
the delay time from the 2T
pulse peak of the input signal
to the 2T pulse peak of the
non-inverted output at TP43.
TDYDEF
Max.
Unit
30
mV
Y/C input
260
360
460
ns
Composite input
(NTSC)
520
620
720
ns
Composite input
(PAL)
520
620
720
ns
Y/color difference input
SW53 = SW54 = A
100
200
300
ns
NTSC
–3
0
3
dB
PAL
–3
0
3
dB
NTSC
–3
0
3
dB
PAL
–3
0
3
dB
Chroma signal block
ACC amplitude
characteristics 1
ACC amplitude
characteristics 2
APC pull-in range
ACC1
ACC2
FAPC
Color adjustment
characteristics
MAX
GCOLMX
Color adjustment
characteristics
MIN
GCOLMN
HUE adjustment
characteristics
MAX
HUEMX
HUE adjustment
characteristics
MIN
HUEMN
Input SIG5 (VL = 150mV) to (A) and SIG2
(0dB/+6dB/–20dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Measure the output
amplitude at TP55, assuming the output
corresponding to 0dB, +6dB and –20dB as
V0, V1 and V2, respectively.
ACC1 = 20 log (V1/V0)
ACC2 = 20 log (V2/V0)
Input SIG5 (VL = 150mV) to (A) and SIG2
(0dB, 3.58MHz burst/chroma phase = 180°,
or 4.43MHz burst/chroma phase = ±135°) to
(B). Vary the SIG2 burst frequency and
measure the frequency f1 at which the TP40
output appears (the killer mode is canceled).
NTSC: FAPCN = f1 – 3579545Hz
PAL: FAPCP = f1 – 4433619Hz
NTSC
±500
Hz
PAL
±500
Hz
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz burst/chroma phase = 180°) to (B). Assume
the chroma signal amplitude at TP55 when serial bus
register COLOR = 128, 255 and 0 as V0, V1 and V2,
respectively.
GCOLMX = 20 log (V1/V0)
GCOLMN = 20 log (V2/V0)
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
burst/chroma phase variable) to (B). Assume the
phase at which the output amplitude at TP40 reaches
a minimum when serial bus register HUE = 128, 255
and 0 as θ0, θ1 and θ2, respectively.
HUEMX = θ1 – θ0
HUEMN = θ2 – θ0
SW57 = A
– 13 –
+3
+5
–25
dB
–20
dB
–30
–40
deg
30
60
deg
CXA3017R
Item
Symbol
ACKN
Killer operation
input level
ACKP
VRBN
Demodulation
output amplitude
ratio (NTSC)
VGBN
θRBN
Demodulation
output phase
difference (NTSC)
θGBN
VRBP
Demodulation
output amplitude
ratio (PAL)
VGBP
θRBP
Demodulation
output phase
difference (PAL)
θGBP
Color difference
input color
adjustment
characteristics MAX
GEXCMX
Color difference
input color
adjustment
characteristics MIN
GEXCMN
Color difference
balance
VEXCBL
Conditions
Input SIG5 (VL = 150mV) to (A) and SIG2
(level variable, 3.58MHz burst/chroma phase
= 180°, or 4.43MHz burst/chroma phase =
±135°) to (B), and measure the output
amplitude at TP40. Gradually reduce the
SIG2 amplitude level and measure the level
at which the killer operation is activated.
SW57 = A
Min.
Typ.
Max.
Unit
NTSC
–36
–30
dB
PAL
–36
–30
dB
0.53
0.63
0.73
0.25
0.32
0.39
99
109
119
deg
230
242
254
deg
0.65
0.75
0.85
0.33
0.40
0.47
80
90
100
deg
232
244
256
deg
+3
+5
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz) to (B) and vary the chroma phase. Assume
the maximum amplitude at TP40 as VB, the maximum
amplitude at TP43 as VG, and the maximum amplitude
at TP45 as VR.
VRBN = VR/VB, VGBN = VG/VB
SW57 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
3.58MHz) to (B) and vary the chroma phase. Assume
the phase at which the amplitude at TP40, TP43 and
TP45 reaches a maximum as θB, θG and θR,
respectively.
θRBN = θR – θB, θGBN = θG – θB
SW57 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
4.43MHz) to (B) and vary the chroma phase. Assume
the maximum amplitude at TP40 as VB, the maximum
amplitude at TP43 as VG, and the maximum amplitude
at TP45 as VR.
VRBP = VR/VB, VGBP = VG/VB
SW57 = A
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
4.43MHz) to (B) and vary the chroma phase. Assume
the phase at which the amplitude at TP40, TP43 and
TP45 reaches a maximum as θB, θG and θR,
respectively.
θRBP = θR – θB, θGBP = θG – θB
SW57 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP40 (100kHz) when serial bus register
COLOR = 128 as VC0, when COLOR = 0 as VC2,
and when SIG1 is set to –10dB and COLOR = 255
as VC1.
GEXCMX = 20 log (VC1/VC0) + 10
GEXCMN = 20 log (VC2/VC0)
SW53 = SW54 = A
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D) and (E). Assume the output
amplitude at TP40 (100kHz) as VB and the output
amplitude at TP45 (100kHz) as VR.
VEXCBL = VR/VB
SW53 = SW54 = A
– 14 –
0.8
dB
–20
–15
1.0
1.2
dB
CXA3017R
Item
Color difference
input balance
adjustment R
Color difference
input balance
adjustment B
Symbol
GEXRMX
GEXRMN
GEXBMX
GEXBMN
Conditions
Input SIG5 (VL = 150mV) to (A) and SIG1 (–6dB,
100kHz, no burst) to (D) and (E). Assume the output
amplitude at TP45 (100kHz) and TP40 (100kHz)
when serial bus register HUE = 128 as VR0 and VB0,
respectively, when HUE = 255 as VR1 and VB1,
respectively, and when HUE = 0 as VR2 and VB2,
respectively.
GEXRMX = 20 log (VR1/VR0)
GEXRMN = 20 log (VR2/VR0)
GEXBMX = 20 log (VB1/VB0)
GEXBMN = 20 log (VB2/VB0)
SW53 = SW54 = A
Min.
Typ.
Max.
Unit
–5
–2
dB
+2
+3
dB
+2
+3
dB
–5
–2
dB
VEXGBN
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP40 (100kHz) as VEXB and the output
amplitude at TP43 (100kHz) as VEXBG.
VEXGBN = VEXBG/VEXB
SW53 = SW54 = A
0.23
0.26
0.29
VEXGRN
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (E). Assume the output
amplitude at TP45 (100kHz) as VEXR and the output
amplitude at TP43 (100kHz) as VEXRG.
VEXGRN = VEXRG/VEXR
SW53 = SW54 = A
0.46
0.51
0.56
VEXGBP
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (D). Assume the output
amplitude at TP40 (100kHz) as VEXB and the output
amplitude at TP43 (100kHz) as VEXBG.
VEXGBP = VEXBG/VEXB
SW53 = SW54 = A
0.17
0.20
0.23
VEXGRP
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB,
100kHz, no burst) to (E). Assume the output
amplitude at TP45 (100kHz) as VEXR and the output
amplitude at TP43 (100kHz) as VEXRG.
VEXGRP = VEXRG/VEXR
SW53 = SW54 = A
0.46
0.51
0.56
VOUT
Input SIG5 (VL = 0mV) to (A). Adjust serial bus
registers BRIGHT and PSIG-BRT so that the output
(black-black) at TP43 and TP38 is 9Vp-p and measure
the DC voltage at TP40, TP43, TP45 and TP38.
5.85
6.00
6.15
V
∆VOUT
Input SIG5 (VL = 0mV) to (A). Adjust serial bus
registers BRIGHT and PSIG-BRT so that the output
(black-black) at TP43 and TP38 is 9Vp-p, measure the
DC voltage at TP40, TP43, TP45 and TP38, and obtain
the maximum difference between each of these values.
0
100
mV
6.5
V
G-Y matrix
characteristics
(NTSC)
G-Y matrix
characteristics
(PAL)
RGB signal output block
RGB signal and
PSIG output DC
voltage
RGB signal and
PSIG output DC
voltage difference
SIG center variable
VORNG
range
Set V48 to 5.2V or 6.5V in the VOUT measurement
conditions and confirm that ∆VOUT in the preceding
item is satisfied and that |V48 – VOUT| ≤ 0.15V.
SW48 = ON
– 15 –
5.2
CXA3017R
Item
Symbol
VLIMMX
RGB and PSIG
output black limiter
operation voltage
VLIMMN
Difference in RGB
output inverted/
non-inverted gain
Difference in black
level potential
between RGB
output signals
7.0
UBRTMX
Input SIG3 to (A) and measure the amount of change
in the black level output at TP40, TP43 and TP45
when serial bus register USER-BRT is changed from
128 to 255.
UBRTMN
Input SIG3 to (A) and measure the amount of change
in the white level output at TP40, TP43 and TP45
when serial bus register USER-BRT is changed from
128 to 0.
BRTMX
Input SIG3 to (A) and measure the black level output
at TP40, TP43 and TP45 when serial bus register
BRIGHT is changed from 128 to 255.
BRTMN
Input SIG3 to (A) and measure the white level output
at TP40, TP43 and TP45 when serial bus register
BRIGHT is changed from 128 to 0.
SBBRT
Input SIG5 (VL = 0mV) to (A) and measure the
difference between the outputs (black-black) at TP40
and TP45 and the output (black-black) at TP43 when
serial bus registers R-BRT = B-BRT = 0 and when
R-BRT = B-BRT = 255.
±1.3
±1.7
∆GRGB
Input SIG4 to (A) and obtain the level difference
between the maximum and minimum non-inverted
output amplitudes (white-black) at TP40, TP43 and
TP45.
–0.6
0
SBCNT
Input SIG4 to (A) and measure the difference between
the non-inverted outputs (white-black) at TP40 and
TP45 and the non-inverted output (white-black) at
TP43 when serial bus registers R-CNT = B-CNT = 0
and when R-CNT = B-CNT = 255.
±1.5
±2
∆GINV
Input SIG4 to (A) and obtain the difference between
the non-inverted output amplitudes (white-black) and
the inverted output amplitudes at TP40, TP43 and
TP45.
–0.3
0
∆VBL
Input SIG4 to (A) and obtain the level difference
between the maximum and minimum black levels of
both the inverted and non-inverted outputs at TP40,
TP43 and TP45.
9.0
–2.5
V
V
2.5
–2.5
Vp-p
V
3.0
–3.0
2.0
Vp-p
Vp-p
1.5
2.5
Unit
Vp-p
Input SIG3 (VL = 0mV) to (A) and measure the output
(black-black) at TP38 when serial bus register
PSIG-BRT = 0.
– 16 –
Max.
9.0
PSIGMN
Amount of change
in brightness
Amount of change
in sub-contrast
Typ.
Input SIG3 (VL = 0mV) to (A) and measure the output
(black-black) at TP38 when serial bus register
PSIG-BRT = 255.
Amount of change
in user brightness
Difference in gain
between RGB
output signals
Input SIG3 to (A). Vary BLKLIM and measure the
maximum value VLIMMX and minimum value
VLIMMN of the voltage range (black-black) over
which the black limiter operates for the TP38, TP40,
TP43 and TP45 outputs. Assume the value when
BLKLIM = 0 as VLIMMX, and when BLKLIM = 255 as
VLIMMN.
Min.
PSIGMX
Amount of change
in PSIG output
Amount of change
in sub-brightness
Conditions
–2.0
V
V
0.6
dB
dB
0.3
dB
300
mV
CXA3017R
Item
Symbol
Gγ1
γ gain
Gγ2
Gγ3
V γ 1MN
γ 1 adjustment
variable range
V γ 1MX
V γ 2MN
γ 2 adjustment
variable range
V γ 2MX
tPSIGH
PSIG transition
time
tPSIGL
RGB output white
limiter operation
voltage
VWLIMX
VWLIMN
Conditions
Input SIG8 to (A). Adjust the non-inverted output
amplitude (black-white) at TP43 to 3.5Vp-p with serial
bus register CONT and the black level at TP43 to 1.5V
with serial bus register RBT.
Measure VG1, VG2 and VG3.
G γ 1 = 20 log (VG1/0.0375)
G γ 2 = 20 log (VG2/0.0375)
G γ 3 = 20 log (VG3/0.0375)
(See Fig. 5 for definitions of VG1, VG2 and VG3.)
Input SIG8 to (A) and adjust serial bus register
BRIGHT so that the output at TP43 is 9Vp-p (blackblack).
Read the point where the gain of the non-inverted
output at TP43 changes when serial bus register
γ 1 = 0 and 255 from the input signal IRE level.
V γ 1MN when γ 1 = 0, and V γ 1MX when γ 1 = 255.
Input SIG8 to (A) and adjust serial bus register
BRIGHT so that the output at TP43 is 9Vp-p (blackblack).
Read the point where the gain of the non-inverted
output at TP43 changes when serial bus register
γ 2 = 0 and 255 from the input signal IRE level.
V γ 2MN when γ 2 = 0, and V γ 2MX when γ 2 = 255.
Typ.
Max.
Unit
23.0
26.0
29.0
dB
12.0
15.0
18.0
dB
18.0
22.0
26.0
dB
0
IRE
100
IRE
100
IRE
0
IRE
1.5
3.0
µs
1.5
3.0
µs
1.0
1.1
1.2
V
0.45
0.55
0.65
V
0
100
mV
0
100
mV
Input SIG4 to (A) and adjust serial bus register PSIGBRT so that the output at TP38 is 9Vp-p (black-black).
Measure the time it takes to change to an amplitude of
9Vp-p.
tPSIGH: rise time, tPSIGL: fall time
Load: 20000pF
Input SIG3 to (A) and measure the potential difference
between the white limiter level of the TP43 output and
SIGCENTER.
VWLIMX when WHITELIM = 0
VWLIMN when WHITELIM = 3
Black limiter DC
voltage difference
∆VBLIM
Input SIG5 (VL = 0mV) to (A) and adjust BLKLIM so that
the output at TP43 is 9Vp-p (black-black). Measure the
DC voltage at TP40, TP43 and TP45 and obtain the
difference versus the RGB output voltage VOUT.
White limiter DC
voltage difference
∆VWLIM
Input SIG5 (VL = 350mV) to (A). Measure the DC
voltage at TP40, TP43 and TP45 and obtain the
difference versus the RGB output voltage VOUT.
RGB output range
when FRP polarity VDROFF
inversion is stopped
Min.
Input SIG8 to (A). Assume the black limiter level of
the output at TP40, TP43 and TP45 when serial bus
register BRIGHT = 0 as VDRB and the white limiter
level when BRIGHT = 255 as VDRW.
VDROFF = VDRW – VDRB
– 17 –
3.0
Vp-p
CXA3017R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
NTSC 1.5MHz
–18
–12
dB
PAL
2.0MHz
–16
–10
dB
NTSC 5.5MHz
–6
–2
dB
PAL
–6
–2
dB
NTSC
–40
–30
dB
PAL
–40
–30
dB
1.2
1.5
MHz
Filter characteristics
Amount of BPF
attenuation
ATBPF
ATRAPN
Amount of TRAP
attenuation
ATRAPP
R-Y and B-Y LPF
characteristics
Assume the chroma amplitude at
TP55 when SIG5 (VL = 0mV) is input
to (A) and SIG1 (0dB at input center
frequency (3.58MHz or 4.43MHz)) is
input to (B) as 0dB. Obtain the
amount by which the output at TP55
is attenuated when the frequencies
noted on the right are input.
SW57 = A
Input SIG2 (0dB, 3.58MHz and
4.43MHz) to (A) and measure the
output at TP43 with a spectrum
analyzer. Assume the amplitude at
TP43 during Y/C input mode as 0dB,
and obtain the amount of attenuation
during COMP input mode.
6.8MHz
Assume the amplitude of the 100kHz component of
the output at TP43 when SIG5 (VL = 150mV) is input
to (A) and SIG2 (0dB, 3.58MHz + 100kHz) is input to
(B) as 0dB. Obtain the frequency which attenuates
the beat component of the output by 3dB when the
SIG2 frequency is increased with respect to 3.58MHz.
0.9
WSSEP
Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to
(A) and confirm that it is synchronized with the HD
output at TP21. Gradually narrow the WS of SIG5
from 4.7µs and obtain the WS at which
synchronization with the HD output at TP21 is lost.
2.0
VSSEP
Input SIG5 (VL = 0mV, WS = 4.7µs, VS variable) to
(A) and confirm that it is synchronized with the HD
output at TP21. Gradually reduce the VS of SIG5 from
143mV and obtain the VS at which synchronization
with the HD output at TP21 is lost.
DEMLPF
Sync separation, TG block
Input sync signal
width sensitivity
Sync separation
input sensitivity
TDSY1
HD output delay
time
TDSY2
HPLLN
Horizontal pull-in
range
HPLLP
Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to
(A) and measure the delay time with the HD output at
TP21. TDSY1 is from the falling edge of the input
HSYNC to the rising edge of the HD output, and
TDSY2 is from the falling edge of the input HSYNC to
the falling edge of the HD output.
Input SIG5 (VL = 0mV, WS = 4.7µs, VS =
143mV, horizontal frequency variable) to
NTSC
(A) and confirm that it is synchronized
with the HD output at TP21. Obtain the
frequency fH at which the input and
output are synchronized by changing the
horizontal frequency of SIG5 from the
PAL
non-synchronized condition.
HPLLN = fH – 15734, HPLLP = fH – 15625
– 18 –
µs
40
60
mV
2.3
2.6
2.9
µs
4.3
4.6
4.9
µs
±500
±1000
Hz
±500
±1000
Hz
CXA3017R
Item
Symbol
Conditions
Min.
Output transition
time
(page 11∗2 pins)
tTLH
Cross-point time
difference
∆T
Input SIG5 (VL = 0mV) to (A) and measure
HCK1/HCK2, VCK1/VCK2 and VCK3/VCK4.
Load = 50pF (See Fig. 4.) SW57 = A
HCK duty
DTYHC
Input SIG5 (VL = 0mV) to (A) and measure the
HCK1/HCK2 duty.
Load = 50pF, SW57 = A
47
VBKLTH
Measure the output voltage at TP23 when DA OUT = 7.
IOH = –1mA
2.7
VBKLTL
Measure the output voltage at TP23 when DA OUT = 0.
IOH = 1mA
tTHL
DA OUT output
voltage
Typ.
Input SIG5 (VL = 0mV) to (A) and measure the
transition time for each output.
Load = 50pF (See Fig. 3.) SW57 = A
50
Max.
Unit
30
ns
30
ns
10
ns
53
%
V
0.3
V
External I/O characteristics
VTEXTB
External RGB input
threshold voltage
VTEXTW
Propagation delay
time between
external RGB input
and output
Output blanking
level during
external RGB input
Output white level
during external
RGB input
Minimum pulse
width during
external RGB input
TD1EXT
TD2EXT
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to
(C). Raise the SIG6 amplitude (VL) from 0V and assume
the voltage where the outputs at TP40, TP43 and TP45
go to black level as VTEXTB. Then raise the amplitude
further and assume the voltage where these outputs go
to white level as VTEXTW.
SW1 = SW2 = SW3 = B
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C).
Measure the rise delay time TD1EXT and the fall delay
time TD2EXT of the outputs at TP40, TP43 and TP45.
(See Fig. 2.)
SW1 = SW2 = SW3 = B
EXTBK
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to
(C). Measure the difference from the black level of the
outputs at TP40, TP43 and TP45.
SW1 = SW2 = SW3 = B
EXTWT
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to
(C). Measure the difference from the black level of the
outputs at TP40, TP43 and TP45.
SW1 = SW2 = SW3 = B
TEXMIN
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to
(C). Measure the minimum pulse width at which each
of the outputs at TP40, TP43 and TP45 reach the
white limiter.
SW1 = SW2 = SW3 = B
– 19 –
0.8
1.0
1.2
V
1.8
2.0
2.2
V
50
90
130
ns
50
100
140
ns
0
V
3.0
V
180
ns
CXA3017R
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
ts0
LOAD setup time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
ts1
DATA setup time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
th0
LOAD hold time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
th1
DATA hold time, activated by the rising edge of SCLK.
(See Fig. 6.)
150
ns
tw1L
SCLK pulse width. (See Fig. 6.)
156
ns
tw1H
SCLK pulse width. (See Fig. 6.)
156
ns
tw2
LOAD pulse width. (See Fig. 6.)
1
µs
Serial transfer block
Data setup time
Data hold time
Minimum pulse
width
– 20 –
– 21 –
ICC13
ICC12
ICC11
Symbol
VIL
VIH
VOH1
VOL1
GV
GCNTTP
GCNTMN
Low level input
voltage
High level input
voltage
High level output
voltage
Low level output
voltage
Video maximum
gain
Contrast
characteristics TYP
Contrast
characteristics MIN
IDD1
Current
consumption VDD1, 2
IDD2
Current
ICC2
consumption VCC2, 3
Current
consumption VCC1
Horizontal AFC
adjustment
Item
—
Y/color
NTSC
difference
COMP NTSC
COMP NTSC
COMP NTSC
COMP NTSC
COMP NTSC
COMP NTSC
—
—
—
—
—
—
—
128
ON 128 128 128 128
ON 128 128 128 128
ON 128 128 128 128
ON 128 128 128 128
ALL ON 128 128 128
0
ALL ON 128 128 128 128
128
128
128
128
128
128
128
128
ON 128 128 128 128
ON 128 128 128 128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
Serial bus
BRBRT BRT
ON 128 128 128 128
ON 128 128 128 128
ON 128 128 128 128
ON 128 128 128 128
ON 128 128 128 128
ALL ON 128 128 128 255
1
1
1
1
1
COMP NTSC 005
COMP NTSC
1
1
1
1
1
1
COMP NTSC 009
COMP NTSC 501
—
—
NTSC
Y/C
COMP NTSC
—
System Panel S/H FRP HUE COL BRT CNT
COMP NTSC
Input
Mode settings
VCO must be reset when the panel mode is changed.
Y signal block
Digital block I/O characteristics
Current characteristics
Setting 2
Description of Electrical Characteristics Measurement Methods
Serial Bus Register Initial Settings
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ2
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128
128
128
128
128
128
128
128
128
128
128
128
128
128
USER
WHITE DA
BLK
BPSIG RPIC -BRT VCO LIM
OUT
BRT CNT CNT LIM
DAC settings
CXA3017R
– 22 –
Y signal block
ALL ON 128 128 128 128
Y/C
128
ALL ON 128 128 128 128
SPAL 005
128
ALL ON 128 128 128 128
—
—
ACC1
ACC2
FAPC
ACC amplitude
characteristics 2
APC pull-in range
TDYDEF
—
SPAL
128
ALL ON 128 128 128 128
—
COMP NTSC
SPAL
—
ALL ON 128 128 128 128
128
128
ALL ON 128 128 128 128
—
COMP NTSC
COMP
128
ALL ON 128 128 128 128
—
SPAL
COMP
128
ALL ON 128 128 128 128
128
ALL ON 128 128 128 128
—
—
128
ALL ON 128 128 128 128
—
SPAL
COMP
COMP NTSC
Y/color
difference
TDYCMP COMP
128
128
ALL ON 128 128 128 128
—
Y/C
TDYCMN COMP NTSC
ACC amplitude
characteristics 1
Y signal I/O delay
time
TDYYC
ALL ON 128 128 128 128
128
ALL ON 128 128 128 128
—
—
128
ALL ON 128 128 128 128
COMP NTSC 009
—
128
ALL ON 128 128 128 128
128
ALL ON 128 128 128 128
COMP NTSC 005
COMP NTSC 009
128
ALL ON 128 128 128 128
128
ALL ON 128 128 128 128
NTSC 005
Y/C
COMP NTSC 005
128
ALL ON 128 128 128 128
NTSC 005
Y/C
128
ALL ON 128 128 128 128
NTSC 009
Y/C
Carrier leak (Y block) CRLEKY COMP
Picture quality
GSHP4X
adjustment variable
GSHP4N
amount 4
Picture quality
GSHP3X
adjustment variable
GSHP3N
amount 3
Picture quality
GSHP2X
adjustment variable
amount 2
GSHP2N
128
ALL ON 128 128 128 128
NTSC 009
Y/C
FCYCMP COMP
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
180
BRBRT BRT
ALL ON 128 128 128 128
NTSC 009
System Panel S/H FRP HUE COL BRT CNT
Input
Mode settings
FCYCMN COMP NTSC 005
FCYYC
Symbol
Picture quality
GSHP1X
adjustment variable
amount 1
GSHP1N
Y signal frequency
response
Item
VCO must be reset when the panel mode is changed.
Chroma signal block
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
Serial bus
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ2
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128 ADJ
128 ADJ
128 ADJ
128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
0
255 128 ADJ
0
255 128 ADJ
0
255 128 ADJ
0
255 128 ADJ
128 128 ADJ
128 128 ADJ
180 128 ADJ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
USER
WHITE DA
PSIG RBBLK
PIC -BRT VCO LIM
BRT CNT CNT LIM
OUT
DAC settings
CXA3017R
– 23 –
COMP NTSC
COMP NTSC
COMP
HUEMN
ACKN
ACKP
HUE adjustment
characteristics MIN
Color difference
balance
Color difference
input color
adjustment
Demodulation
output phase
difference (PAL)
Demodulation
output amplitude
ratio (PAL)
Demodulation
output phase
difference (NTSC)
Demodulation
output amplitude
ratio (NTSC)
COMP NTSC
COMP NTSC
COMP NTSC
VGBN
θRBN
θGBN
—
—
—
COMP
COMP
Y/color
difference
Y/color
difference
Y/color
difference
θRBP
θGBP
GEXCMX
GEXCMN
VEXCBL
SPAL
COMP
VGBP
SPAL
SPAL
COMP
VRBP
SPAL
COMP NTSC
VRBN
SPAL
COMP NTSC
HUE adjustment
HUEMX
characteristics MAX
Killer operation
input level
COMP NTSC
GCOLMN
0
128 128
—
—
—
—
0
128 128
ALL ON 128 128 128 128
ALL ON 128
ALL ON 128 255 128 128
ALL ON 128 128 150 128
ALL ON 128 128 150 128
128
128
128
128
128
128
ALL ON 128 128 150 128
—
—
128
128
ALL ON 128 128 150 128
ALL ON 128 128 150 128
128
—
—
ALL ON 128 128 150 128
128
ALL ON 128 128 150 128
—
—
128
128
ALL ON 128 128 150 128
—
ALL ON 128 128 150 128
128
ALL ON 128 128 150 128
—
—
128
128 150 128
128
128
128
ALL ON
0
ALL ON 255 128 150 128
ALL ON 128
ALL ON 128 255 128 128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BRBRT BRT
—
—
—
—
System Panel S/H FRP HUE COL BRT CNT
Color adjustment
characteristics MIN
Input
Mode settings
COMP NTSC
Symbol
Color adjustment
GCOLMX
characteristics MAX
Item
VCO must be reset when the panel mode is changed.
Chroma signal block
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ2
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
3
3
3
3
3
3
128 128 ADJ
0
0
3
3
128 128 ADJ
128 128 ADJ
3
0
0
128 128 ADJ
3
128 128 ADJ
0
0
3
3
128 128 ADJ
0
128 128 ADJ
3
128 128 ADJ
0
0
3
3
3
3
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
USER
WHITE DA
BLK
PSIG RBPIC -BRT VCO LIM OUT
BRT CNT CNT LIM
DAC settings
0
0
0
0
γ1
Serial bus
CXA3017R
Chroma signal block
– 24 –
—
—
—
Y/color
difference
Y/color
NTSC
difference
Y/color
NTSC
difference
Y/color
SPAL
difference
Y/color
SPAL
difference
GEXBMN
VEXGBN
VEXGRN
VEXGBP
VEXGRP
Amount of change
in PSIG output
RGB output/PSIG
black limiter
operation voltage
—
SIG center variable
range
—
—
—
—
—
—
—
—
VLIMMN
PSIGMX
PSIGMN
—
—
—
VLIMMX
VORNG
—
RGB/PSIG output
∆VOUT
DC voltage difference
RGB/PSIG output
DC voltage
G-Y matrix
characteristics
(PAL)
G-Y matrix
characteristics
(NTSC)
—
—
—
Y/color
difference
GEXBMX
VOUT
—
—
Y/color
difference
GEXRMN
Color difference
input balance
adjustment B
—
Y/color
difference
GEXRMX
ALL ON
ALL ON
ALL ON
ALL ON
—
—
—
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
ALL ON
—
—
—
—
—
—
—
—
128 128 128 128
128 128 128 128
128
128
128
255 128
255 128
80
80
128 128
128 128 128 255 128
128 128 128 255 128
128
128
128
128
128
128
128
128
128
128
128
128 128
128 128 ADJ 128 128
128 128 ADJ 128 128
128 128 ADJ 128 128
128 128 128 128 128
128 128 128 128 128
128 128 128 128 128
128 128 128 128 128
0
255 128 128 128 128
0
128
BRBRT BRT
255 128 128 128 128
System Panel S/H FRP HUE COL BRT CNT
Color difference
input balance
adjustment R
Input
Mode settings
Symbol
Item
VCO must be reset when the panel mode is changed.
RGB signal output block
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
Serial bus
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ2
0
255
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
128 128
0
0
128 128
128 128
255 128 128
0
0
0
0
0
0
0
0
0
0
0
0
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
ADJ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BLK
USER
WHITE DA
PSIG RBPIC
VCO
-BRT
LIM OUT
BRT CNT CNT LIM
DAC settings
CXA3017R
– 25 –
—
Amount of change
in sub-contrast
—
—
—
—
V γ 1MN
V γ 1MX
V γ 2MN
V γ 2MX
—
—
Gγ3
PSIG transition time tPSIG
γ 2 adjustment
variable range
γ 1 adjustment
variable range
—
—
Gγ1
Gγ2
—
Difference in black
level potential
∆VBL
between RGB signals
γ gain
—
Difference in RGB
inverted/non-inverted ∆GINV
gain
SBCNT
—
—
—
BRTMN
Difference in gain
∆GRGB
between RGB signals
—
—
BRTMX
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UBRTMN
—
—
128
ALL ON 128 128
—
—
—
—
—
—
—
—
—
—
—
—
—
—
128
ALL ON 128 128 255 255 128
—
80
80
80
80
60
60
60
60
128
128
128
128
ALL ON 128 128 128 128 128
ALL ON 128 128
ALL ON 128 128
ALL ON 128 128
ALL ON 128 128
ALL ON 128 128 ADJ ADJ 128
ALL ON 128 128 ADJ ADJ 128
ALL ON 128 128 ADJ ADJ 128
ALL ON 128 128 128 128 128
ALL ON 128 128 128 128 128
ALL ON 128 128 128 128 128
ALL ON 128 128 128 128 128
0
0
0
0
0
0
0
0
0
γ1
0
0
0
0
0
0
0
0
0
γ2
128
128
0
0
128
128
128
255 128
0
0
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128
128 255 ADJ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128 128 128 SET 128
128
128
128 255
0
128 140 230 128
128 140 230 128
128
128
128
128
128
128
128
128 SET SET
128
128
128
128
128
128
USER
WHITE DA
BLK
PSIG RBPIC -BRT VCO LIM
BRT CNT CNT LIM
OUT
DAC settings
128 140 230 128
128
128
128
128
ALL ON 128 128 160 128 SET SET
255 128
128
ALL ON 128 128 128 255 128
—
0
128
ALL ON 128 128 128 255 128
BRBRT BRT
—
System Panel S/H FRP HUE COL BRT CNT
—
Input
Mode settings
UBRTMX
Symbol
SBBRT
Amount of change
in sub brightness
Amount of change
in brightness
Amount of change
in user brightness
Item
VCO must be reset when the panel mode is changed.
RGB signal output block
Serial bus
CXA3017R
– 26 –
RGB signal output block
Filter characteristics
RGB output range
when FRP polarity
VDROFF
inversion is stopped
Output transition
time
Horizontal pull-in
range
SPAL
COMP NTSC
—
HPLLP
NTSC
tTHL
—
HPLLN
—
—
—
—
NTSC 009
COMP NTSC
—
TDSY2
—
—
—
—
—
—
—
—
—
—
NTSC 009
—
—
NTSC
SPAL
NTSC
SET
—
—
—
—
0
128
1
1
ON 128 128 128 128
ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 150 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL OFF 128 128 SET 128
ALL ON 128 128 255 128
ALL ON 128 128
ALL ON 128 128 128 128
System Panel S/H FRP HUE COL BRT CNT
Mode settings
tTLH
—
—
—
TDSY1
VSSEP
Sync separation
input sensitivity
HD output delay
time
WSSEP
Input sync signal
width sensitivity
Y/C
SET
ATRAPP
DEMLPF
SET
COMP
—
ATRAPN
R-Y and B-Y LPF
characteristics
Amount of TRAP
attenuation
ATBPF
—
∆VWLIM
White limiter DC
voltage difference
Amount of BPF
attenuation
—
∆VBLIM
Black limiter DC
voltage difference
—
VWLIM
RGB output white
limiter operation
voltage
Input
Symbol
Item
VCO must be reset when the panel mode is changed.
Sync, TG block
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
BRBRT BRT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
γ1
Serial bus
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
128
0
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128
128 128 ADJ
3
3
3
3
3
3
3
3
3
3
3
3
3
0
0
ADJ SET
128 ADJ 128 128 ADJ
128
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
WHITE DA
USER
BBLK
PSIG RPIC
VCO LIM
-BRT
BRT CNT CNT LIM
OUT
255 128
γ2
DAC settings
CXA3017R
Sync, TG block
– 27 –
—
—
—
—
VTEXTW
Propagation delay
TD1EXT
time between external
RGB input and output TD2EXT
—
—
EXTBK
EXTWT
External RGB input
blanking level
External RGB input
output white level
External RGB input
TEXMIN
minimum pulse width
—
—
—
VTEXTB
External RGB input
threshold voltage
—
—
—
—
—
—
—
VBKLTL
DA OUT output
voltage
—
COMP NTSC
—
DTYHC
HCK duty
—
—
—
—
—
—
—
—
—
—
ON 128 128 128 128
ON 128 128 128 128
—
—
ALL ON 128 128 128 128
ALL ON 128 128 100 128
ALL ON 128 128 128 128
128
128
128
128
ALL ON 128 128 128 128
—
—
128
128
128
—
—
128
128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
ALL ON 128 128 128 128
—
—
1
1
128
128
128
128
128
128
128
—
—
128
128
BRBRT BRT
—
—
—
—
—
—
—
System Panel S/H FRP HUE COL BRT CNT
COMP NTSC
Input
Mode settings
VBKLTH
∆T
Symbol
Cross-point time
difference
Item
VCO must be reset when the panel mode is changed.
External I/O characteristics
0
0
0
0
0
0
0
—
—
0
0
γ1
Serial bus
0
0
0
0
0
0
0
—
—
0
0
γ2
128
128
128
128
128
128
128
—
—
128
128
128
128
128
128
128
128
128
—
—
128
128
0
0
0
0
0
0
0
—
—
0
0
—
—
—
—
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
128 128 ADJ
—
—
128 128 ADJ
128 128 ADJ
3
3
3
3
3
3
3
—
—
3
3
—
—
—
—
—
—
—
0
7
—
—
(—: don't care, ADJ: adjustment, SET: setting)
128
128
128
128
128
128
128
—
—
128
128
USER
WHITE DA
BLK
PSIG RBPIC
VCO
-BRT
LIM OUT
BRT CNT CNT LIM
DAC settings
CXA3017R
CXA3017R
Electrical Characteristic Measurement Method Diagrams
3V
SIG6
0V
100%
TP40, 43, 45
non-inverted output
50%
TD1EXT
TD2EXT
Fig. 2. Conditions for measuring the delay between external RGB input and output
∆T
90%
50%
10%
tTLH
∆T
tTHL
Fig. 3. Output transition time measurement
conditions
Fig. 4. Cross-point time difference measurement
conditions
White
Non-inverted output
VG3
VG2
3.5V
VG1
Black
1.5V
Input
Fig. 5. γ characteristics measurement conditions
– 28 –
CXA3017R
DATA
D15 D14 D13 D12 D11 D10 D9
ts1
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
th1
SCLK
50%
tw1H
tw1L
50%
LOAD
ts0
th0
Fig. 6. Serial transfer block measurement conditions
– 29 –
tw2
CXA3017R
Input Waveforms
SG No.
Waveform
Sine wave video signal: With/without burst
Amplitude and frequency variable
SIG1
150mV
← Value noted
on left: 0 dB
150mV
143mV
Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz)
Chroma phase and burst frequency variable
SIG2
150mV
← Value noted
on left: 0 dB
143mV
Ramp waveform
357mV
SIG3
143mV
1H
5-step staircase waveform
150mV
SIG4
143mV
1H
VL amplitude variable
VS variable: 143mV unless otherwise specified
WS variable: 4.7µs unless otherwise specified
fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL)
unless otherwise specified
VL
SIG5
VS
fH
WS
– 30 –
CXA3017R
SG No.
Waveform
30µs
5µs
VL amplitude variable
VL
SIG6
Horizontal sync signal
75mV
Frequency variable
SIG7
175mV
143mV
10-step staircase waveform
357mV
SIG8
143mV
1H
SIN2 2T pulse waveform
357mV
SIG9
143mV
1H
– 31 –
CXA3017R
Electrical Characteristics Measurement Circuit
+12V
SW48
ICC2 A
V48
TP45
0.01µ
400p
20000p
400p
400p
+15.5V
TP38
TP40
TP43
100k
100k
47µ
+3V
0.1µ
0.1µ
0.1µ
0.01µ
IDD4 A
0.1µ
0.22µ 10k
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R OUT
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT1
DWN
VDD2
0.01µ
DA OUT 32
TP32
VD 31
TP31
51 VXO IN
EN2 30
TP30
52 APC
EN1 29
TP29
53 B-Y IN
XEN1 28
TP28
54 R-Y IN
VCK1 27
TP27
55 C OUT
VCK2 26
TP26
56 V REG
VCK3 25
TP25
57 C IN
VCK4 24
TP24
VST 23
TP23
XVST 22
TP22
HD 21
TP21
61 SYNC IN
PCG 20
TP20
62 VSEP TC
XPCG 19
TP19
63 F0 ADJ
HCK1 18
TP18
64 GND1
HCK2 17
TP17
49 VCC1
∗1
47
FB R
47µ
48
VCC2
47µ
0.01µ
SIG.CENTER
ICC1 A
+3V
TP35
TP34
50 VXO OUT
16p
0.033µ
0.1µ
(D)
0.1µ
(E)
A
SW53
B
A
B SW54 TP55
3.9k 1µ
(B)
A
B
SW57
SW58
58 RESET
V58
1µ
59 Y IN
TP60
60 TEST2
0.01µ
(A)
0.33µ
EXT G
EXT B
TRAP
VDD1
LOAD
DATA
SCLK
RPD
TEST1
BLK
CLR
HST2
HST1
XHST1
VSS
∗2
EXT R
15k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SW1 SW2 SW3
B A B A B A
TP6
TP7 TP8
∗3
10k
3.3µ
TP10 TP11 TP12 TP13 TP14 TP15
TP9
6800p
(C)
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm,
load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz
∗2 Resistance value tolerance: ±2%,
temperature coefficient: ±200ppm or less
∗3 Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
– 32 –
+3V
IDD3 A
47µ
0.01µ
CXA3017R
Description of Operation
The CXA3017R incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using Bi-CMOS technology.
1) RGB decoder block
• Input mode switching
The input mode (composite input, Y/C input, Y/color difference input) can be switched by the serial bus settings.
During composite input:
The composite signal is input to Pins 57, 59 and 61.
During Y/C input:
The Y signal is input to Pins 59 and 61, and the C signal to Pin 57.
During Y/color difference input: The Y signal is input to Pins 59 and 61, the B-Y signal to Pin 53, and the R-Y
signal to Pin 54.
• System switching
The input system (NTSC, SPAL, DPAL) can be switched by the serial bus settings. (DPAL uses external
delay lines.)
• Trap, BPF
The center frequency of the built-in trap and BPF can be switched to 3.58MHz during NTSC and 4.43MHz
during PAL.
During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do
not pass through the trap or BPF during Y/C input and Y/color difference input.
• ACC detection, ACC amplifier
The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is controlled
to maintain the burst signal amplitude at a constant level.
• VXO, APC detection
The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the
VXO oscillator output are compared in the APC detection block, and the detective output is used to form a
PLL that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated.
• External inputs
These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold
Vth1 (≈ 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 (≈ 2.0V) is exceeded, the
output for only the signal in question goes to white level, while the other outputs remain at black level.
– 33 –
CXA3017R
2) RGB driver block
• γ correction
In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The γ gain
transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register γ1, and the transition
point B voltage changes as shown in Fig. 3 by adjusting γ2.
Output
Output
Output
B
A
A
Input
B'
B
A'
A
Input
Input
Fig. 1
B
Fig. 2
Fig. 3
• Sample-and-hold circuit
As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA3017R must be
sampled-and-held in sync with the LCD panel drive pulses.
R
S/H1
S/H4
G
S/H2
HCK1
A
S/H4
B
B
S/H3
S/H4
C
SH1 SH2 SH3 SH4
RGT = H (normal)
RGT = L (right/left inversion)
SHS1
SHS2
SHS3
SH1
B
A
C
SH2 Through Through Through
SH2
A
C
B
SH3
A
C
B
SH3 Through Through Through
SH4
C
B
A
SH4
SH1
SHS1
SHS2
SHS3
B
A
C
C
B
SH1: R signal SH pulse
SH2: G signal SH pulse
SH3: B signal SH pulse
SH4: RGB signal SH pulse
A
SHS1,2,3: Serial data settings
The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG
block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must
be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation
timing is also generated by the TG block. The sample-and-hold timing changes according to the phase
relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual
board.
– 34 –
CXA3017R
• RGB output
RGB outputs (Pins 40, 43 and 45) are inverted each horizontal line by the FRP pulse (internal pulse) supplied
from the TG block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center)
of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER
(Pin 48)). In addition, the white level output is clipped at the limiter operation point that is set by the serial bus
register WHITE LIM, and the black level output is clipped at the limiter operation point that is set by the serial
bus register BLKLIM.
Video IN
FRP
Black level limiter
White level limiter
Vsig center
White level limiter
RGB OUT
Black level limiter
3) TG block
• PLL and AFC circuits
The TG block contains a PLL circuit phase comparator and frequency division counter and a VCO circuit, and
comprises a PLL circuit.
The PLL error detection signal is generated by the HSYNC block, and the integral value of the phase comparison
output of the entire bottom of HSYNC and the internal frequency division counter becomes RPD (Pin 9).
The CXA3017R controls the internal VCO with the RPD output to stabilize the oscillation frequency at 690fH
(NTSC) or 716fH (PAL) for the LCX005BK/BKB and LCX024AK/AKB, and 1034fH (NTSC) or 1072fH (PAL) for
the LCX009AK/AKB, LCX027AK/AKB and DCX501BK. The PLL of this system is adjusted by adjusting the
serial bus register VCO so that the RPD output waveform is constant near VSYNC as shown in the figure
Video signal
RPD (Pin 9)
Adjust to a horizontal waveform.
Horizontal AFC adjustment
• H position
The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings. Note
that the delay difference between the RGB signal and the drive pulse differs according to the board, so adjust
the serial bus register H position so that the picture center matches the center of the LCD panel.
– 35 –
CXA3017R
• Right/left inversion
The LCD panel is arranged in a delta arrangement, where identical signal lines are offset by 1.5 dots from
adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd
lines and even lines. HCK and S/H are also 1.5-bit offset. Therefore, when the panel is driven by left scan
(Reverse scan), this offset relationship is inverted for even and odd lines.
Moreover, since the dot arrangement is asymmetrical, the HST position is also changed.
RGT = H: Right scan mode
RGT = L: Left scan mode
(H and L are the LCD panel input levels.)
Left scan
(Reverse scan)
Right scan
(Normal scan)
V SCANNER
H SCANNER
Active area
LCD panel
• Wide mode
Wide mode can be selected by setting wide mode with the serial bus aspect switching register. In this mode,
aspect ratio conversion is performed by pulse elimination processing to enable 16:9 quasi-WIDE display.
Vertical pulse elimination scanning of 1/4 for NTSC and 10/28 for PAL is performed and the video signal is
compressed in order to achieve a 16:9 aspect ratio during the wide mode period. In addition, high-speed
scan is performed in areas outside of the active area to display black in the upper 28 lines and the lower 28
(27) lines. Black display is performed by limiting the video signal input during the V blanking period and
writing a black level signal in its place.
Vertical high-speed scan
225 LINES
(218 LINES)
Black active area
28 LINES
(28 LINES)
Active area
169 LINES
(163 LINES)
Black active area
28 LINES
(27 LINES)
Active area
4:3 display
Vertical pulse elimination scan
16:9 display
Numbers inside parentheses are for the LCX005BK/BKB and LCX024AK/AKB; other numbers are for the
LCX009AK/AKB, LCX027AK/AKB and DCX501BK.
– 36 –
CXA3017R
• AC driving of LCD panels during no signal
HST, XHST, HCK1, HCK2, VST, XVST, VCK1, VCK2, PCG, XPCG, EN, XEN, HD, VD, and FRP (internal
pulse) are made to run freely so that the LCD panel is AC driven even when there is no composite sync from
the SYNCIN pin.
During this time, the HSYNC separation circuit stops and the PLL counter is made to run freely. In addition,
the VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse
for generating VD, VST and XVST. The cycle of this V counter is designed to be 525/2H for NTSC and
625/2H for PAL. However, when there is no vertical sync signal for 5 fields, the no signal state is assumed
and the free running VD, VST and XVST pulses are generated from the next field. In addition, RPD is kept at
high impedance when there is no signal in order to prevent the AFC circuit from causing errors due to phase
comparison.
– 37 –
CXA3017R
Description of Serial Control Operation
1) Control method
Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This
loading operation starts from the falling edge of LOAD and is completed at the next rising edge.
Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for
the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator)
block control data becomes valid each time the LOAD signal is input.
D15 D14 D13 D12 D11 D10 D9
DATA
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
LOAD
Serial transfer timing
2) Serial data map
The serial data map is as follows.
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
PLL
adjustment 2
PLL
adjustment 1
0
0
0
0
0
0
1
0
1
∗
∗
∗
H-POSITION
0
0
0
0
0
1
1
0
∗
∗
∗
HD-POSITION
1
0
0
0
0
0
0
0
HUE
1
0
0
0
0
0
0
1
COLOR
1
0
0
0
0
0
1
0
BRIGHT
1
0
0
0
0
0
1
1
CONTRAST
1
0
0
0
0
1
0
0
R-BRIGHT
1
0
0
0
0
1
0
1
B-BRIGHT
1
0
0
0
0
1
1
0
γ-1
1
0
0
0
0
1
1
1
γ-2
D7
D6
D5
S/H phase Aspect
0
0
D3
External
VSYNC
D2
System
Panel 2 TEST1
DWN RGT2 RGT1
– 38 –
D4
D0
Input
switching
Supported panels
SYNC
TEST2
GEN
P-FRP
D1
Y/color VD
HD
difference
polarity
polarity
clamp
FRP
FRP
FRP4096
TEST5 inversion inversion inversion inversion TEST4 TEST3
stop
stop
0
0
POWER
SAVE
0
SYNC
detection
∗: don't care
CXA3017R
Serial data map (cont.)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
1
0
0
0
1
0
0
0
PSIG-BRIGHT
1
0
0
0
1
0
0
1
R-CONTRAST
1
0
0
0
1
0
1
0
B-CONTRAST
1
0
0
0
1
0
1
1
BLK LIM
1
0
0
0
1
1
0
0
PICTURE
1
0
0
0
1
1
0
1
USER-BRIGHT
1
0
0
0
1
1
1
0
VCO
1
0
0
0
1
1
1
1
∗
∗
∗
∗
∗
1
0
0
1
0
0
0
0
∗
∗
∗
∗
∗
1
1
1
0
0
0
0
0
D2
∗
D1
D0
WHITE LIM
DA OUT
TEST6
∗: don't care
3) Serial data mode settings
(X: don't care)
• Input switching
This switches the input signal format.
D1
D0
0
X
Composite input (default)
1
0
Y/C input
1
1
Y/color difference input
• System switching
This switches the input video signal system.
D3
D2
0
0
NTSC (default)
0
1
TEST
1
0
D-PAL
1
1
S-PAL
• External VSYNC
Internal VSYNC separation is not performed and an externally input VSYNC is used.
D4
0
OFF (internal separation) (default)
1
ON (external input)
• Aspect switching
This switches the video display aspect.
D5
0
4:3 (normal) (default)
1
16:9 (letterbox, pulse elimination display)
– 39 –
CXA3017R
• Sample-and-hold phase
This switches the sample-and-hold timing.
D7
D6
0
0
SHS1 (default)
0
1
SHS2
1
0
SHS3
1
1
Through (sample-and-hold not performed)
• Supported panels
This switches the supported panels.
D3 D2 D1 D0
Supported panels
0
0
0
0
LCX005BK/BKB single
0
0
0
1
LCX024AK/AKB single
0
0
1
0
LCX009AK/AKB single
0
0
1
1
LCX027AK/AKB single
0
1
0
0
LCX005BK/BKB + (DCX501BK)
0
1
0
1
LCX024AK/AKB + (DCX501BK) (default)
0
1
1
0
LCX009AK/AKB + (DCX501BK)
0
1
1
1
LCX027AK/AKB + (DCX501BK)
1
0
0
0
1
0
0
1
1
0
1
0
—
1
0
1
1
—
1
1
0
0
DCX501BK
+ (LCX005BK/BKB)
1
1
0
1
DCX501BK
+ (LCX024AK/AKB)
1
1
1
0
DCX501BK
+ (LCX009AK/AKB)
1
1
1
1
DCX501BK
+ (LCX027AK/AKB)
—
DCX501BK
single
Two-panel simultaneous drive mode
The supported panels are the main
panel and the sub panel (the panel
noted inside the parentheses).
The video is not displayed correctly on
the sub panel for combinations of the
LCX005BK (BKB)/024AK (AKB) and
the DCX501BK. Therefore, the sub
panel back light should be turned off.
Two-panel simultaneous display is
possible with combinations of the
LCX009AK (AKB)/027AK (AKB) and the
DCX501BK (only when RGT1 = RGT2).
However, when the right/left inversion
directions of the main and sub panels
differ (RGT1 ≠ RGT2), the picture is not
displayed correctly due to the line offset.
Therefore, use Panel 2 mode in these
cases.
• TEST1
This is the test mode. Set to normal mode.
D4
0
Normal mode (default)
1
TEST mode
• Panel 2
Set this when the right/left inversion direction of the two panels differs (RGT1 ≠ RGT2) during two-panel
simultaneous drive using the LCX009AK (AKB)/027AK (AKB)and the DCX501BK.
D5
0
OFF (default)
1
ON
Notes) 1. The VST connection changes in this mode, so an external inverter is required.
2. Set sample and hold to OFF (through) in this mode.
3. When the right/left inversion direction of the two panels differs (RGT1 ≠ RGT2), the video display
start position of the sub panel is advanced by 1H.
4. RGT1 and RGT2 can also be set the same in this mode.
– 40 –
CXA3017R
• HD polarity
This switches the HD output (Pin 21) polarity.
D0
0
Positive polarity (default)
1
Negative polarity
• VD polarity
This switches the VD output (Pin 31) polarity.
D1
0
Positive polarity (default)
1
Negative polarity
• Y/color difference clamp
This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input
mode.
D2
0
Pedestal position (default)
1
SYNC position
• TEST2
This is the test mode. Set to normal mode.
D3
0
Normal mode (default)
1
TEST mode
• SYNC GEN
This sets the sync generator function. Outputs other than VD and HD of the TG block are stopped.
D4
0
OFF (default)
1
ON
• RGT1 (right/left inversion 1)
This switches the DCX501BK right/left inverted display timing and the RGT1 output (Pin 34).
D5
0
OFF (normal display) (default)
1
ON (right/left inverted display)
• RGT2 (right/left inversion 2)
This switches the LCX005BK (BKB)/009AK (AKB)/024AK (AKB)/027AK (AKB)right/left inverted display
timing.
D6
0
OFF (normal display) (default)
1
ON (right/left inverted display)
• DWN (up/down inversion)
This switches the DCX501BK up/down inverted display timing and the DWN output (Pin 35).
D7
0
OFF (normal display) (default)
– 41 –
CXA3017R
• TEST3
This is the test mode. Set to normal mode.
D0
0
Normal mode (default)
1
TEST mode
• TEST4
This is the test mode. Set to normal mode.
D1
0
Normal mode (default)
1
TEST mode
• FRP4096 inversion
This further inverts the polarity of the RGB output that is inverted every 1H for 4096 fields.
D2
0
OFF (default)
1
ON
• FRP inversion stop
This stops R, G and B output polarity inversion.
D3
0
OFF (1H inversion) (default)
1
ON (polarity not inverted)
• P-FRP inversion stop
This stops PSIG output polarity inversion.
D4
0
OFF (1H inversion) (default)
1
ON (polarity not inverted)
• FRP inversion
This switches the FRP output inversion cycle.
D5
0
1H inversion (default)
1
1 field inversion
• TEST5
This is the test mode. Set to normal mode.
D6
0
Normal mode (default)
1
TEST mode
• Sync detection
This prevents (as much as possible) the vertical sync from being lost during weak magnetic field signal input.
Set to ON (0).
D0
0
ON (default)
1
OFF
– 42 –
CXA3017R
• POWER SAVE
This stops HST1/XHST1 in order to reduce the DCX501BK current consumption.
Set to OFF (0).
D2
0
OFF (default)
1
ON (HST1/XHST1 stopped)
• PLL adjustment 1, 2
These set the PLL adjustment.
D7
D6
0
0
(default)
0
1
Set D7 = 0, D6 = 1.
1
0
1
1
• H position setting
This sets the horizontal display start position. (2fH intervals in 32 different ways)
D4
D3
D2
D1
D0
0
0
0
0
0
:
:
:
:
:
1
0
0
0
0 (default)
:
:
:
:
:
1
1
1
1
1
Variable in 2fH (= 1 bit) increments
CLK (internal)
10001
10000
HST
01111
1 step 1 step
• HD phase setting
This sets the HD output (Pin 21) phase. (4fH intervals in 32 different ways)
D4
D3
D2
D1
D0
0
0
0
0
0 (default)
:
:
:
:
:
1
1
1
1
1
Variable in 4fH (= 1 bit) increments
HSYNC
00000
HD
11111
31 steps
– 43 –
CXA3017R
4) Serial data electronic attenuator (D/A converter) settings
• HUE
• COLOR
• BRIGHT
• CONTRAST
• R-BRT
• B-BRT
• γ-1
• γ-2
• PSIG-BRT
• R-CONT
• B-CONT
• BLK LIM
• PICTURE
• USER-BRIGHT
• VCO
• WHITE LIM
D7
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
—
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
D3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
D2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
(default)
5) DA OUT
This controls the DC level (0 to 3V, 8 steps) of the DA OUT (Pin 32) DAC output.
DA OUT
D7
—
D6
—
D5
—
D4
—
D3
—
D2
0
D1
0
D0
0
(default)
6) TEST6
TEST6 is a test mode which results automatically if data is sent to these addresses, regardless of the data
contents. For this reason, do not perform data transfer using these addresses.
D15
1
D14 D13
1
1
D12
0
D11
0
D10
0
D9
0
D8
0
D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X X X
– 44 –
CXA3017R
DCX501BK Color Coding Diagram
The CXA3017R supports LCD panels which perform color coding in a delta arrangement.
The shaded areas in the figure are not displayed.
DCX501BK Pixel Arrangement
R
G
Vline2
R
B
Vline1
R
B
G
G
B
R
B
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
HSW266
B
R
G
R
G
B
B
G
B
R
R
G
HSW267
B
R
G
G
B
R
B
R
G
B
R
G
HSW268
Photo-shielding
area
B
R
G
R
G
B
G
B
R
B
G
R
G
R
B
R
225
Vline3
R
HSW3
R
G
B
B
R
R
G
G
B
B
R
R
G
G
B
B
R
G
R
G
B
B
R
R
G
G
B
B
R
G
R
G
B
R
Active area
B
Vline225
dummy2
G
R
B
R
G
R
G
B
G
B
R
B
R
G
R
G
B
G
B
R
B
R
G
R
G
B
G
B
R
B
R
G
R
G
B
G
B
R
B
R
G
G
B
G
R
B
R
R
G
1
Vline224
R
Precharge SW
2
800
803
– 45 –
1
227
dummy1
HSW2
1
HSW1
CXA3017R
LCX027AK/AKB Pixel Arrangement
R
B
Vline1
Vline2
G
R
B
R
G
B
Vline3
R
G
G
R
B
R
B
G
B
B
G
R
G
R
B
R
R
B
G
B
G
R
G
G
R
B
R
B
G
B
B
G
B
R
R
G
R
R
B
G
G
B
G
R
HSW266
G
R
B
R
B
G
B
B
R
G
B
R
R
G
R
B
R
G
G
B
G
G
R
B
B
R
B
G
dummy5 to 8
HSW268
B
G
R
G
R
B
R
R
G
B
R
G
G
B
R
Photo-shielding
area
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
R
G
B
R
Active area
R
B
Vline225
dummy3
G
R
B
R
G
R
G
B
G
B
R
B
R
G
R
G
B
G
B
R
B
R
G
R
G
B
14
B
R
800
827
– 46 –
G
B
R
G
R
G
B
G
B
R
B
R
G
R
G
B
G
B
R
13
R
G
1
Vline224
228
dummy2
R
HSW3
2
B
dummy1
HSW1
225
dummy1 to 4
CXA3017R
LCX024AK/AKB Pixel Arrangement
B
G
Vline1
Vline2
R
B
R
B
B
R
G
B
R
B
R
G
B
R
G
B
B
G
B
B
R
R
G
B
R
B
G
G
R
B
B
G
R
G
G
R
B
R
B
G
R
G
R
B
R
B
G
R
B
R
G
R
B
G
B
R
B
G
R
G
R
HSW179
R
G
B
Photo-shielding
area
B
G
R
B
R
B
G
B
G
R
B
G
B
G
R
G
R
B
G
R
G
R
B
R
B
G
R
B
R
B
G
B
G
R
B
G
B
G
R
G
R
B
R area
G
Active
G
G
R
B
R
HSW178
R
G
B
R
G
R
G
B
R
2
G
B
G
R
G
R
B
G
R
G
R
B
R
B
G
R
B
R
B
G
B
G
R
B
G
dummy3
B
G
R
G
R
B
G
Vline218
G
B
G
Vline3
R
HSW176
dummy4
B
R
3
G
B
R
G
B
R
G
B
521
R
G
B
R
G
B
R
13
537
– 47 –
G
228
dummy2
B
HSW3
2
G
dummy1
HSW2
218
HSW1
CXA3017R
LCX009AK/AKB Pixel Arrangement
dummy1 to 4
B
R
G
B
HSW2
R
G
B
HSW267
R
G
B
dummy5 to 8
HSW268
R
G
B
R
G
B
R
2
dummy1
HSW1
Vline2
B
R
R
G
B
Vline3
R
dummy3
R
R
B
G
G
G
R
G
B
R
G
B
R
800
827
– 48 –
R
G
B
R
G
B
G
R
B
R
B
G
R
G
R
B
G
B
G
R
B
R
B
G
R
G
R
B
G
B
G
R
B
R
B
G
R
G
R
B
G
G
B
G
R
B
R
G
R
B
R
B
G
R
B
14
G
R
G
B
R
B
G
R
G
B
G
R
G
R
B
G
B
R
Active area
R
G
B
B
B
B
R
B
G
R
G
R
B
G
G
B
G
R
B
R
B
G
R
R
G
R
B
G
B
G
R
B
B
R
B
G
R
G
B
G
R
B
Vline225
B
G
R
R
G
R
B
Vline224
B
R
G
B
R
13
R
G
228
Vline1
G
225
R
1
dummy2
Photo-shielding
area
B
R
G
CXA3017R
LCX005BK/BKB Pixel Arrangement
dummy2
B
R
G
Vline1
Vline2
B
B
R
G
B
R
R
B
G
B
G
R
B
B
G
B
B
R
G
R
B
B
B
G
R
R
R
B
G
G
G
R
B
G
R
B
B
G
R
R
G
R
B
R
G
B
R
Photo-shielding
area
G
B
R
G
B
R
B
G
B
R
B
G
R
G
B
G
R
B
R
G
R
B
G
B
R
B
G
R
G
B
G
R
G
R
B
R
G
Active
area
G
G
R
B
R
dummy2 to 5
HSW175
R
B
G
B
G
R
G
G
R
B
R
B
G
B
B
G
R
G
R
B
R
R
G
B
R
G
R
G
B
R
2
G
B
G
R
G
R
B
G
R
G
R
B
R
B
G
R
B
R
B
G
B
G
R
B
G
dummy3
B
G
R
G
R
B
G
Vline217
G
R
B
R
B
G
Vline3
Vline218
B
HSW174
HSW3
dummy4
B
R
3
G
B
R
G
B
R
G
B
521
R
G
B
R
G
B
R
13
537
– 49 –
G
222
G
dummy1
HSW2
2
HSW1
218
dummy1
– 50 –
VST/VD
VCK4
VCK3
CLR
EN2 (PAL)
EN1 (PAL)
EN1
PCG
VCK2
VCK1
FRP (Internal)
SH4 (Internal)
SH3 (Internal)
SH2 (Internal)
SH1 (Internal)
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
5.0µs (56fH)
3.0µs (34fH)
0.5µs (6fH)
6.5µs (73fH)
3.0µs (34fH)
5.0µs (56.5fH)
6.0µs (67.5fH)
4.5µs (50fH)
4.7µs (53fH)
ODD LINE
3.0µs (34fH)
2.0µs (22fH)
4.7µs (53fH)
22.5fH
13fH
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000
Cycle value NTSC: 690 ck, PAL: 716 ck
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4, VST(EN2 is high during NTSC.)
DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
Horizontal Direction Timing Chart — NTSC/PAL
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 51 –
VST/VD
VCK4
VCK3
CLR
EN2 (PAL)
EN1 (PAL)
EN1
PCG
VCK2
VCK1
FRP (Internal)
SH4 (Internal)
SH3 (Internal)
SH2 (Internal)
SH1 (Internal)
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
3.0µs (34fH)
3.0µs (34fH)
0.5µs (6fH)
6.5µs (73fH)
5.0µs (55fH)
6.0µs (66fH)
4.5µs (50fH)
4.7µs (53fH)
EVEN LINE
3.0µs (34fH)
2.0µs (22fH)
5.0µs (56fH)
4.7µs (53fH)
AAA
21fH
13fH
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000
Cycle value NTSC: 690 ck, PAL: 716 ck
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4 and VST (EN2 is high during NTSC.)
DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
Horizontal Direction Timing Chart — NTSC/PAL
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 52 –
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
ODD LINE
EVEN LINE
ODD LINE
2.0µs (22fH)
4.7µs (53fH)
4.5µs (50fH)
4.7µs (53fH)
HST1 and HST2 during right/left inversion
23.5fH
22fH
21fH
22.5fH
13fH
13fH
13fH
13fH
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output)
HST2: LCX005/024 horizontal display start pulse
RGT1 = 0 or 1, RGT2 = 1
RGT1 = 0 or 1, RGT2 = 1
RGT1 = 0 or 1, RGT2 = 0
RGT1 = 0 or 1, RGT2 = 0
Horizontal Direction Timing Chart — NTSC/PAL
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 53 –
VST/VD
VCK4, (3)
VCK3, (4)
CLR
EN2 (PAL)
EN1 (PAL)
EN1
PCG
VCK2
VCK1
FRP (Internal)
SH4 (Internal)
SH3 (Internal)
SH2 (Internal)
SH1 (Internal)
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
ODD LINE
0.5µs (8fH)
6.5µs (109fH)
3.0µs (50fH)
5.0µs (84.5fH)
6.0µs (101.5fH)
4.5µs (75fH)
4.7µs (79fH)
20.5fH
12fH
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000
Cycle value NTSC: 1034 ck, PAL: 1072 ck
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4))
LCX009/027, 005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4 and VST (EN2 is high during NTSC.)
DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
5.0µs (84fH)
3.0µs (50fH)
2.0µs (34fH)
3.0µs (50fH)
4.7µs (79fH)
Horizontal Direction Timing Chart — NTSC/PAL
LCX009 + (DCX501), LCX027 + (DCX501)
DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
CXA3017R
– 54 –
VST/VD
VCK4, (3)
VCK3, (4)
CLR
EN2 (PAL)
EN1 (PAL)
EN1
PCG
VCK2
VCK1
FRP (Internal)
SH4 (Internal)
SH3 (Internal)
SH2 (Internal)
SH1 (Internal)
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
0.5µs (8fH)
6.5µs (109fH)
3.0µs (50fH)
5.0µs (83fH)
6.0µs (100fH)
4.5µs (75fH)
19fH
12fH
AA
AA
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4))
LCX009/027, 005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4 and VST (EN2 is high during NTSC.)
DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
5.0µs (84fH)
AAA
3.0µs (50fH)
3.0µs (50fH)
2.0µs (34fH)
AAA
4.7µs (79fH)
AAA
AAA
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000
Cycle value NTSC: 1034 ck, PAL: 1072 ck
AAA
AAA
AAA
AAAA
AAA
AAA
AAA
AAA
AAA
AAA
4.7µs (79fH)
AAA
Horizontal Direction Timing Chart — NTSC/PAL
LCX009 + (DCX501), LCX027 + (DCX501)
DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
CXA3017R
– 55 –
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
ODD LINE
EVEN LINE
ODD LINE
4.7µs (79fH)
2.0µs (34fH)
4.5µs (75fH)
4.7µs (79fH)
HST1 and HST2 during right/left inversion, RGT2 = 0
19fH
22fH
20.5fH
23.5fH
19fH
20.5fH
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output)
HST2: LCX009/027 horizontal display start pulse
RGT1 = 1, RGT2 = 0
RGT1 = 1, RGT2 = 0
RGT1 = 0, RGT2 = 0
RGT1 = 0, RGT2 = 0
Horizontal Direction Timing Chart — NTSC/PAL
LCX009 + (DCX501), LCX027 + (DCX501)
12fH
12fH
12fH
12fH
12fH
12fH
CXA3017R
– 56 –
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
ODD LINE
EVEN LINE
ODD LINE
2.0µs (34fH)
4.5µs (75fH)
4.7µs (79fH)
HST1 and HST2 during right/left inversion, RGT2 = 1
21.5fH
20fH
21.5fH
24.5fH
20fH
23fH
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output)
HST2: LCX009/027 horizontal display start pulse
RGT1 = 1, RGT2 = 1
RGT1 = 1, RGT2 = 1
RGT1 = 0, RGT2 = 1
RGT1 = 0, RGT2 = 1
4.7µs (79fH)
Horizontal Direction Timing Chart — NTSC/PAL
LCX009 + (DCX501), LCX027 + (DCX501)
12fH
12fH
12fH
12fH
12fH
12fH
CXA3017R
– 57 –
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
ODD LINE
EVEN LINE
ODD LINE
4.5µs (75fH)
4.7µs (79fH)
22fH
19fH
23.5fH
20.5fH
19fH
20.5fH
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output)
HST2: LCX009/027 horizontal display start pulse
RGT1 = 0, RGT2 = 1
RGT1 = 0, RGT2 = 1
RGT1 = 0, RGT2 = 0
RGT1 = 0, RGT2 = 0
2.0µs (34fH)
HST1 and HST2 during right/left inversion, RGT1 = 0
4.7µs (79fH)
Horizontal Direction Timing Chart — NTSC/PAL
DCX501 + (LCX009), DCX501 + (LCX027)
12fH
12fH
12fH
12fH
12fH
12fH
CXA3017R
– 58 –
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
ODD LINE
EVEN LINE
ODD LINE
4.5µs (75fH)
21.5fH
20fH
24.5fH
21.5fH
23fH
20fH
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output)
HST2: LCX009/027 horizontal display start pulse
RGT1 = 1, RGT2 = 1
RGT1 = 1, RGT2 = 1
RGT1 = 1, RGT2 = 0
RGT1 = 1, RGT2 = 0
2.0µs (34fH)
4.7µs (79fH)
HST1 and HST2 during right/left inversion, RGT1 = 1
4.7µs (79fH)
Horizontal Direction Timing Chart — NTSC/PAL
DCX501 + (LCX009), DCX501 + (LCX027)
12fH
12fH
12fH
12fH
12fH
12fH
CXA3017R
– 59 –
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HCK2
HCK1
HST2
HST1
HD
(BLK)
(SYNC)
(MCK)
EVEN LINE
ODD LINE
EVEN LINE
ODD LINE
4.5µs (75fH)
24.5fH
21.5fH
23fH
20fH
19fH
20.5fH
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output)
HST2: LCX005/024 horizontal display start pulse
RGT1 = 1, RGT2 = 0 or 1
RGT1 = 1, RGT2 = 0 or 1
RGT1 = 0, RGT2 = 0 or1
RGT1 = 0, RGT2 = 0 or 1
2.0µs (34fH)
4.7µs (79fH)
HST1 and HST2 during right/left inversion
4.7µs (79fH)
Horizontal Direction Timing Chart — NTSC/PAL
DCX501 + (LCX005), DCX501 + (LCX024)
12fH
12fH
12fH
12fH
12fH
12fH
CXA3017R
– 60 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK1, 4
VCK2, 3
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
AA
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 61 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK1, 4
VCK2, 3
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
AA
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 62 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK1, 4
VCK2, 3
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
AA
AA
Vertical Direction Timing Chart — PAL
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 63 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK1, 4
VCK2, 3
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
AA
AA
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
AA
AA
Vertical Direction Timing Chart — PAL
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 64 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK2, 3, (4)
VCK1, 4, (3)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4))
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC
LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027),
DCX501 + (LCX005), DCX501 + (LCX024)
CXA3017R
– 65 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK2, 3, (4)
VCK1, 4, (3)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
A
A
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4))
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC
LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027),
DCX501 + (LCX005), DCX501 + (LCX024)
CXA3017R
– 66 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal)
VCK2, 3, (4)
VCK1, 4, (3)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4))
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — PAL
LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027),
DCX501 + (LCX005), DCX501 + (LCX024)
CXA3017R
– 67 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
AA
AA
EVEN FIELD
AA
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4))
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
FRP (Internal)
VCK2, 3, (4)
VCK1, 4, (3)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
Vertical Direction Timing Chart — PAL
LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027),
DCX501 + (LCX005), DCX501 + (LCX024)
: Display end line
: Display start line
AA
CXA3017R
– 68 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK1, 4 (B)
VCK2, 3 (B)
FRP (Internal) (A)
VCK1, 4 (A)
VCK2, 3 (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
AA
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005 + (DCX501) mode: VCK(A) output
LCX024 + (DCX501) mode: VCK(B) output
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC-WIDE
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 69 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK1, 4 (B)
VCK2, 3 (B)
FRP (Internal) (A)
VCK1, 4 (A)
VCK2, 3 (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005 + (DCX501) mode: VCK(A) output
LCX024 + (DCX501) mode: VCK(B) output
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC-WIDE
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 70 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK1, 4 (B)
VCK2, 3 (B)
FRP (Internal) (A)
VCK1, 4 (A)
VCK2, 3 (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005 + (DCX501) mode: VCK(A) output
LCX024 + (DCX501) mode: VCK(B) output
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — PAL-WIDE
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 71 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK1, 4 (B)
VCK2, 3 (B)
FRP (Internal) (A)
VCK1, 4 (A)
VCK2, 3 (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX005 + (DCX501) mode: VCK(A) output
LCX024 + (DCX501) mode: VCK(B) output
LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
AA
AA
Vertical Direction Timing Chart — PAL-WIDE
LCX005 + (DCX501), LCX024 + (DCX501)
CXA3017R
– 72 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK2, 3 (B)
VCK1, 4 (B)
FRP (Internal) (A)
VCK2, 4, (3) (A)
VCK1, 3, (4) (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output
(In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A)))
LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC-WIDE
LCX009 + (DCX501), LCX027 + (DCX501),
DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
CXA3017R
– 73 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK2, 3 (B)
VCK1, 4 (B)
FRP (Internal) (A)
VCK2, 4, (3) (A)
VCK1, 3, (4) (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output
(In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A)))
LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — NTSC-WIDE
LCX009 + (DCX501), LCX027 + (DCX501),
DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
CXA3017R
– 74 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK2, 3 (B)
VCK1, 4 (B)
FRP (Internal) (A)
VCK2, 4, (3) (A)
VCK1, 3, (4) (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
ODD FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output
(In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A)))
LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — PAL-WIDE
LCX009 + (DCX501), LCX027 + (DCX501),
DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
CXA3017R
– 75 –
SBLK
(Internal)
BLK
CLR
EN2
EN1
PCG
FRP (Internal)
1F inversion
FRP (Internal) (B)
VCK2, 3 (B)
VCK1, 4 (B)
FRP (Internal) (A)
VCK2, 4, (3) (A)
VCK1, 3, (4) (A)
HST2
HST1
HD
VST
VD
(BLK)
(SYNC)
EVEN FIELD
A
A
: Display end line
: Display start line
A
A
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output
(In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A)))
LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output
LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK
DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
A
A
Vertical Direction Timing Chart — PAL-WIDE
LCX009 + (DCX501), LCX027 + (DCX501),
DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
CXA3017R
CXA3017R
Application Circuit (NTSC/PAL, COMP input)
VDD of connected LCD panel
+15.5V
To LCD panel
+12V
0.01µ
100k
100k
47µ
0.01µ
0.47µ
0.47µ
0.47µ
0.47µ
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FB R
R OUT
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT1
DWN
VDD2
49 VCC1
∗1
48
VCC2
0.01µ
47µ
SIG.CENTER
+3V
DA OUT 32
50 VXO OUT
VD 31
16p
51 VXO IN
EN2 30
52 APC
EN1 29
0.22µ 10k
0.033µ
53 B-Y IN
XEN1 28
54 R-Y IN
VCK1 27
55 C OUT
VCK2 26
56 V REG
VCK3 25
57 C IN
VCK4 24
To LCD panel
1µ
0.1µ
VST 23
58 RESET
59 Y IN
XVST 22
1µ
60 TEST2
HD 21
0.01µ
COMP IN
61 SYNC IN
PCG 20
62 VSEP TC
XPCG 19
63 F0 ADJ
HCK1 18
64 GND1
HCK2 17
0.33µ
EXT G
EXT B
TRAP
VDD1
LOAD
DATA
SCLK
RPD
TEST1
BLK
CLR
HST2
HST1
XHST1
VSS
∗2
EXT R
15k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+3V
To LCD panel
From serial controller
47µ
10k
∗3
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm,
load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz
3.3µ
0.01µ
6800p
∗2 Resistance value variation: ±2%,
temperature coefficient: ±200ppm or less
∗3 Trap (TDK)
NTSC: NLT4532-S3R6B
PAL: NLT4532-S4R4
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 76 –
CXA3017R
Application Circuit (NTSC/PAL, Y/C input)
VDD of connected LCD panel
+15.5V
To LCD panel
+12V
0.01µ
100k
100k
47µ
0.01µ
0.47µ
0.47µ
0.47µ
0.47µ
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R OUT
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT1
DWN
VDD2
49 VCC1
∗1
48
FB R
47µ
VCC2
0.01µ
SIG.CENTER
+3V
DA OUT 32
50 VXO OUT
VD 31
16p
51 VXO IN
EN2 30
52 APC
EN1 29
0.22µ 10k
0.033µ
53 B-Y IN
XEN1 28
54 R-Y IN
VCK1 27
55 C OUT
VCK2 26
56 V REG
VCK3 25
57 C IN
VCK4 24
To LCD panel
1µ
C IN
0.1µ
VST 23
58 RESET
59 Y IN
XVST 22
1µ
60 TEST2
HD 21
0.01µ
61 SYNC IN
PCG 20
62 VSEP TC
XPCG 19
63 F0 ADJ
HCK1 18
64 GND1
HCK2 17
Y IN
EXT R
EXT G
EXT B
TRAP
VDD1
LOAD
DATA
SCLK
RPD
TEST1
BLK
CLR
HST2
HST1
XHST1
VSS
0.33µ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+3V
To LCD panel
From serial controller
47µ
10k
3.3µ
0.01µ
6800p
∗1 Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm,
load capacity: 16pF
NTSC: 3.579545MHz
PAL: 4.433619MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 77 –
CXA3017R
Application Circuit (NTSC/PAL, Y/color difference input)
VDD of connected LCD panel
+15.5V
To LCD panel
+12V
0.01µ
0.47µ
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R OUT
FB G
G OUT
GND2
FB B
B OUT
VCC3
PSIG
GND3
FB PSIG
RGT1
DWN
VDD2
0.47µ
FB R
49 VCC1
47µ
0.47µ
VCC2
+3V
0.47µ
SIG.CENTER
0.01µ
0.01µ
100k
100k
47µ
DA OUT 32
50 VXO OUT
VD 31
51 VXO IN
EN2 30
52 APC
EN1 29
0.1µ
B-Y IN
53 B-Y IN
XEN1 28
54 R-Y IN
VCK1 27
55 C OUT
VCK2 26
56 V REG
VCK3 25
57 C IN
VCK4 24
0.1µ
R-Y IN
To LCD panel
1µ
0.1µ
VST 23
58 RESET
59 Y IN
XVST 22
1µ
60 TEST2
HD 21
0.01µ
61 SYNC IN
PCG 20
62 VSEP TC
XPCG 19
63 F0 ADJ
HCK1 18
64 GND1
HCK2 17
COMP/Y IN
EXT R
EXT G
EXT B
TRAP
VDD1
LOAD
DATA
SCLK
RPD
TEST1
BLK
CLR
HST2
HST1
XHST1
VSS
0.33µ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+3V
To LCD panel
From serial controller
47µ
10k
3.3µ
0.01µ
6800p
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 78 –
CXA3017R
Example of Representative Characteristics
HUE adjustment characteristics
COLOR adjustment characteristics
10.00
45
0.00
15
Gain [dB]
HUE adjustment angle [deg]
30
0
–15
–10.00
–20.00
–30
–30.00
–45
–60
0
32
64
96 128 160
DAC value
192
–40.00
224 256
0
7
13
6
12
5
11
4
10
3
9
2
8
1
7
6
Non-inverted black
Inverted black
–1
–2
0
32
64
96 128 160
DAC value
192
192
224 256
5
4
224 256
5.00
0.00
–5.00
–10.00
–15.00
–20.00
–25.00
0
SUB-BRIGHT adjustment characteristics
32
64
96 128 160
DAC value
192
224 256
Black limiter control characteristics
2
11
1.5
10
1
Limiter voltage [Vp-p]
Voltage change with respect to G output [V]
96 128 160
DAC value
10.00
Output gain [dB]
14
0
64
CONTRAST adjustment characteristics
8
Inverted output black level [V]
Non-inverted output black level [V]
BRIGHT adjustment characteristics
32
0.5
0
–0.5
9
8
–1
7
–1.5
–2
0
32
64
96 128 160
DAC value
192
6
224 256
– 79 –
0
32
64
96 128 160
DAC value
192
224 256
CXA3017R
Color difference balance adjustment
5.00
PSIG adjustment characteristics
10
B-Y output [dB]
R-Y output [dB]
8
Output amplitude [Vp-p]
1.00
–1.00
–3.00
–5.00
6
4
2
0
32
64
96 128 160 192
DAC value
224
0
256
SUB-CONTRAST adjustment characteristics (γ1 = γ2 = 0)
Non-inverted output black level [V]
2.00
Gain [dB]
1.00
0.00
–1.00
–2.00
–3.00
–4.00
0
32
64
96 128 160 192
DAC value
224
2.5
2
1.5
1
0.5
0
1
2
3
4
DAC value
5
6
7
– 80 –
96 128 160 192
DAC value
224
256
8
14
7
13
6
12
5
11
4
10
3
9
2
8
1
7
0
–2
256
DA OUT output adjustment characteristics
Output voltage [V]
64
6
Non-inverted black
Inverted black
–1
3
0
32
USER-BRIGHT adjustment characteristics
4.00
3.00
0
0
32
64
96 128 160 192
DAC value
224
5
4
256
Inverted output black level [V]
Gain [dB]
3.00
CXA3017R
Sharpness characteristics (γ1 = γ2 = 0)
Sharpness characteristics (γ1 = γ2 = 0)
10.00
20.00
(COMP, PAL, 009AK/AKB)
5.00
15.00
DAC = 0
DAC = 128
DAC = 255
0.00
DAC = 0
DAC = 128
DAC = 255
10.00
–5.00
Gain [dB]
Gain [dB]
(Y/C, 009AK/AKB)
–10.00
5.00
0.00
–15.00
–5.00
–20.00
–10.00
–25.00
–30.00
0
2
4
6
8
Frequency [MHz]
10
–15.00
12
0
Sharpness characteristics (γ1 = γ2 = 0)
4
6
8
Frequency [MHz]
10
12
Sharpness characteristics (γ1 = γ2 = 0)
15.00
15.00
(Y/C, 005BK/BKB)
10.00
(COMP, PAL, 005BK/BKB)
10.00
DAC = 0
DAC = 128
DAC = 0
DAC = 128
DAC = 255
5.00
DAC = 255
0.00
Gain [dB]
5.00
Gain [dB]
2
0.00
–5.00
–5.00
–10.00
–15.00
–20.00
–10.00
–25.00
–15.00
0
2
4
6
8
Frequency [MHz]
10
–30.00
12
0
Sharpness characteristics (γ1 = γ2 = 0)
10
12
10.00
(COMP, NTSC, 005BK/BKB)
10.00
(COMP, NTSC, 009AK/AKB)
5.00
DAC = 0
DAC = 128
DAC = 255
5.00
DAC = 0
DAC = 128
DAC = 255
0.00
Gain [dB]
0.00
Gain [dB]
4
6
8
Frequency [MHz]
Sharpness characteristics (γ1 = γ2 = 0)
15.00
–5.00
–10.00
–5.00
–10.00
–15.00
–15.00
–20.00
–20.00
–25.00
–25.00
–30.00
2
0
2
4
6
8
Frequency [MHz]
10
–30.00
12
– 81 –
0
2
4
6
8
Frequency [MHz]
10
12
CXA3017R
Notes on Operation
The CXA3017R contains digital circuits, so the set board pattern must be designed in consideration of undesired
radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing
the pattern.
• Make the IC power supply and GND patterns as plain as possible. In particular, GND and Vss should not
be separated and should be connected to the same GND pattern as close to the pins as possible.
• Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible.
• The trap connected to Pin 4 should be located as close to the pin as possible. Also, do not pass other
signal lines close to this pin or the connected trap.
• The wiring for the crystal and capacitor connected to Pins 50 and 51 should be as short as possible in
order to prevent floating capacitance. Do not pass other signal lines close to these pins and wiring in order
to prevent interference such as color unevenness. In addition, the APC pull-in characteristics vary
significantly according to the characteristics of the used crystal and the wiring pattern, so be sure to
thoroughly investigate these items before using the set.
• The resistor connected to Pin 63 should be located as close to the pin as possible. Also, do not pass other
signal lines close to this pin.
The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors
connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is
received by the internal capacitor, so this signal should be input at low impedance after applying an
appropriate external DC bias.
The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current
with a small absolute value and variance.
A thorough study of the external buffer for PSIG output should be made before deciding on a circuit to
ascertain that it sufficiently brings out the characteristics of the LCD panel.
If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction
depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of using
this IC with other circuits before deciding on its use.
Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than
the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the
order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up.
Do not apply a voltage higher than VDD or lower than Vss to I/O pins.
Do not use this IC under operating conditions other than those given.
Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage
the device, leading to eventual breakdown.
This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.
– 82 –
CXA3017R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.2
0.15 ± 0.05
48
0.1
33
49
32
A
64
17
1
1.25
16
+ 0.08
0.18 – 0.03
0.5
1.7 MAX
0.1
M
0° to 10°
0.5 ± 0.2
(0.5)
0.1 ± 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-64P-L061
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP064-P-1010-AY
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 83 –