CXA3026AQ 8-bit 140MSPS Flash A/D Converter Description The CXA3026AQ is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 140MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. 48 pin QFP (Plastic) LEAD TREATMENT: PALLADIUM PLATING Structure Bipolar silicon monolithic IC 5 4 DVEE3 6 AGND 7 VRB VIN 8 AVCC VRM2 9 VRM1 VRM3 Applications • Magnetic recording (PRML) • Communications (QPSK, QAM) • LCDs • Digital oscilloscopes AVCC AGND 12 11 10 VRT Pin Configuration (Top View) DGND3 Features • Differential linearity error: ±0.5LSB or less • Integral linearity error: ±0.5LSB or less • High-speed operation with a maximum conversion rate of 140MSPS • Low input capacitance: 21 pF • Wide analog input bandwidth: 150 MHz • Low power consumption: 790 mW • Low error rate • Excellent temperature characteristics • 1: 2 demultiplexed output • 1/2 frequency divided clock output (with reset function) • Compatible with ECL, PECL and TTL digital input levels • Single +5 V power supply operation available • Surface mounting package 3 2 1 CLK/E 13 48 RESETN/E CLKN/E 14 47 RESET/E 46 RESETN/T CLK/T 15 N.C. 16 45 SELECT N.C. 17 44 INV N.C. 18 43 CLKOUT DVCC2 19 42 DVCC2 DGND2 20 41 DGND2 P2D0 21 40 P1D7 P2D1 22 39 P1D6 P2D2 23 38 P1D5 P2D3 24 37 P1D4 P1D3 P1D1 P1D2 P1D0 DVCC2 DGND2 DVCC1 DGND1 P2D7 P2D6 P2D5 P2D4 25 26 27 28 29 30 31 32 33 34 35 36 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96304C92 CXA3026AQ Absolute Maximum Ratings (Ta = 25 °C) Unit AVCC, DVCC1, DVCC2 –0.5 to +7.0 V DGND3 –0.5 to +7.0 V DVEE3 –7.0 to +0.5 V DGND3 – DVEE3 –0.5 to +7.0 V Analog input voltage VIN VRT – 2.7 to AVCC V Reference input voltage VRT 2.7 to AVCC V VRB VIN – 2.7 to AVCC V |VRT – VRB| 2.5 V Digital input voltage ECL (∗∗∗/E∗1) DVEE3 to +0.5 V PECL (∗∗∗/E) –0.5 to DGND3 V TTL (∗∗∗/T, INV) –0.5 to DVCC1 V other (SELECT) –0.5 to DVCC1 V VID∗2 (|∗∗∗/E – ∗∗∗N/E|) 2.7 V Storage temperature Tstg –65 to +150 °C Allowable power dissipation PD 2 W (when mounted on a glass fabric base epoxy board with 50mm x 50mm, 1.6mm thick) • Supply voltage • • • • • Recommended Operating Conditions • • • • • • With a single power supply With dual power supplies Unit Min. Typ. Max. Min. Typ. Max. +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V Supply voltage DVCC1, DVCC2, AVCC DGND1, DGND2, AGND –0.05 0 +0.05 –0.05 0 +0.05 V DGND3 +4.75 +5.0 +5.25 –0.05 0 +0.05 V DVEE3 –0.05 0 +0.05 –5.5 –5.0 –4.75 V Analog input voltage VIN VRB VRT VRB VRT V Reference input voltage VRT +2.9 +4.1 +2.9 +4.1 V VRB +1.4 +2.6 +1.4 +2.6 V |VRT – VRB| 1.5 2.1 1.5 2.1 V Digital input voltage ECL (∗∗∗/E) : VIH DGND3 – 1.05 DGND3 – 0.5 V : VIL DGND3 – 3.2 DGND3 – 1.4 V PECL (∗∗∗/E) : VIH DGND3 – 1.05 DGND3 – 0.5 V : VIL DGND3 – 3.2 DGND3 – 1.4 V TTL (∗∗∗/T, INV) : VIH 2.0 2.0 V : VIL 0.8 0.8 V other (SELECT) : VIH DVCC1 DVCC1 V : VIL DGND1 DGND1 V VID∗2 (|∗∗∗/E – ∗∗∗N/E|) 0.4 0.8 0.4 0.8 V Maximum conversion rate Fc (Straight mode) 100 100 MSPS (DMUX mode) 140 140 MSPS Ambient temperature Ta –20 +75 –20 +75 °C ∗1 ∗∗∗/E and ∗∗∗/T indicate CLK/E and CLK/T, etc. for the pin name. ∗2 VID: Input Voltage Differential ECL and PECL switching level DGND3 VIH (max.) VIL VTH (DGND3–1.2V) VID VIH VIL (min.) —2— CXA3026AQ Block Diagram AVCC 5 8 INV DVCC1 44 30 DVCC2 DGND3 19 31 42 12 VRT 11 r1 r/2 (MSB) r 40 P1D7 1 r 39 P1D6 2 6bits 38 P1D5 63 VRM3 9 8bits r 64 TTL OUT • • • LATCH A r 37 P1D4 36 P1D3 r 35 P1D2 65 6bits • • • 126 127 r 128 VIN 6 r ENCODER r VRM2 7 129 r • • • 34 P1D1 6-bit LATCH+ENCODER r 33 P1D0 (LSB) 8bits (MSB) 28 P2D7 6bits 27 P2D6 191 VRM1 4 26 P2D5 r 193 r • • • TTL OUT LATCH B 192 r 25 P2D4 24 P2D3 6bits 23 P2D2 254 r 22 P2D1 255 r2 VRB 2 21 P2D0 (LSB) r/2 16 CLK/T 15 17 Delay CLK/E 13 N. C. 18 CLKN/E 14 D Q Select 43 CLKOUT Q RESETN/T 46 RESETN/E 48 RESET/E 47 3 10 AGND 45 29 SELECT DGND1 —3— 20 32 41 DGND2 1 DVEE3 CXA3026AQ Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol I/O Standard voltage level Equivalent circuit Description 3, 10 AGND GND Analog ground. Separated from the digital ground. 5, 8 AVCC +5 V (typ.) Analog power supply. Separated from the digital power supply. 20, 29 DGND1 32, 41 DGND2 GND Digital ground. 19, 30 DVCC1 31, 42 DVCC2 +5 V (typ.) Digital power supply. 12 +5 V (Typ.) (With a single power supply) DGND3 Digital power supply. Ground for ECL input. +5 V for PECL and TTL input. GND (With dual power supplies) 1 GND (With a single power supply) DVEE3 Digital power supply. –5 V for ECL input. Ground for PECL and TTL input. –5 V (Typ.) (With dual power supplies) No connected pin. Not connected with the internal circuits. 16, 17 N.C. 18 13 CLK/E I Clock input. I CLK/E complementary input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. DGND3 14 CLKN/E r r 13 48 ECL/ PECL RESETN/E I 1.2V 48 14 47 DVEE3 47 RESET/E r r Reset input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E complementary input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. I —4— CXA3026AQ Pin No. Symbol I/O Standard voltage level Equivalent circuit Description DVCC1 r/2 15 CLK/T I Clock input. TTL 15 46 1.5V r 46 RESETN/T I DGND1 DVEE3 Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. DVCC1 44 INV I Data output polarity inversion input. When left open, this input goes to high level. (See Table 1. I/O Correspondence Table.) TTL 44 DGND1 DVEE3 DVCC1 45 SELECT VCC or GND Data output mode selection. (See Table 2. Operating Mode Table.) 45 DGND1 DVEE3 —5— CXA3026AQ Pin No. 11 Symbol VRT I/O I Standard voltage level 4.0 V (typ.) Equivalent circuit Description Top reference voltage. By-pass to AGND with a 1 µF tantal capacitor and a 0.1 µF chip capacitor. r1 11 r/2 r 9 7 4 VRB + 3 (VRT – VRB) 4 VRM3 VRB + 2 (VRT – VRB) 4 VRM2 VRB + 1 (VRT – VRB) 4 VRM1 Reference voltage mid point. By-pass to AGND with a 0.1 µF chip capacitor. Comparator 1 r Comparator 63 r 9 Comparator 64 Comparator 127 7 r 4 r Comparator 128 Comparator 191 Comparator 192 Reference voltage mid point. By-pass to AGND with a 0.1 µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1 µF chip capacitor. r Comparator 255 2 VRB I 2.0 V (typ.) r/2 2 AVCC r2 Bottom reference voltage. By-pass to AGND with a 1 µF tantal capacitor and a 0.1 µF chip capacitor. Comparator AVCC 6 VIN I VRT to VRB Analog input. DVEE3 33 to 40 P1D0 to P1D7 Vref 6 AGND O Port 1 side data output. DVCC1 P2D0 to P2D7 O TTL 21 to 28 43 CLKOUT Port 2 side data output. 33 to 40 100K 21 to 28 DVCC2 O DGND1 —6— 43 DGND2 DVEE3 Clock output. (See Table 2. Operating Mode Table.) CXA3026AQ Electrical Characteristics (DVCC1, 2, AVCC, DGND3 = +5 V, DGND1, 2, AGND, DVEE3 = 0 V, VRT = 4 V, VRB = 2 V, Ta = 25 °C) Item Symbol Conditions Min. Resolution EIL EDL Analog input Analog input capacitance Analog input resistance Analog input current CIN RIN IIN Reference input Reference resistance Reference current Offset voltage VRT side VRB side Rref∗3 Iref∗4 EOT EOB Digital input (ECL, PECL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance VIH VIL VTH IIH IIL Digital input (TTL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance VIH VIL VTH IIH IIL VIH = 3.5 V VIL = 0.2 V –50 –500 VOH VOL IOH = –2 mA IOL = 1 mA 2.4 Fc Taj Tds Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2 Tr Tf DMUX mode 140 Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock low pulse width RESET Signal setup time RESET Signal hold time CLKOUT output delay Data output delay Output rise time Output fall time Max. 8 DC characteristics Integral linearity error Differential linearity error Digital output (TTL) Digital output voltage : High : Low Typ. VIN = 2 Vp-p, Fc = 5MSPS VIN = +3.0 V + 0.07 Vrms bits ±0.5 ±0.5 LSB LSB 50 500 pF kΩ µA 155 28 15 10 Ω mA mV mV DGND3 – 0.5 DGND3 – 1.4 V V V µA µA pF 21 4 0 75 9.7 2 2 115 17.4 DGND3 – 1.05 DGND3 – 3.2 DGND3 – 1.2 VIH = DGND3 – 0.8 V VIL = DGND3 – 1.6 V –50 –75 +50 0 5 0 0 5 V V V µA µA pF 0.5 V V 2.0 0.8 1.5 CLK CLK RESETN – CLK RESETN – CLK DMUX mode 0.8 to 2.0 V 0.8 to 2.0 V (CL = 5 pF) (CL = 5 pF) (CL = 5 pF) (CL = 5 pF) (CL = 5 pF) ∗These characteristics are for PECL input,unless otherwise specified. —7— 3 3.0 3.0 3.5 0 4.5 T∗5 6.5 10 4.5 7 T+1 8 2 2 Unit 6 8 T+2 10 MSPS ps ns ns ns ns ns ns ns ns ns ns CXA3026AQ Item Symbol Conditions Dynamic characteristics Input bandwidth S/N ratio Min. VIN = 2 Vp-p, –3 dB Fc = 140MSPS, fin = 1 kHz Fs DMUX mode Fc = 140MSPS, fin = 34.999 MHz Fs DMUX mode Fc = 140MSPS, fin = 1 kHz Fs DMUX mode Error>16LSB Fc = 140MSPS, fin = 34.999 MHz Fs DMUX mode Error>16LSB Fc = 100MSPS, fin = 24.999 MHz Fs Straight mode Error>16LSB Error rate Power supply Supply current Supply current Power consumption ICC IEE Pd∗7 INV Step 1 D7 128 127 … VRM2 VRB 1 0 D0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 … … 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 D0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 … 255 254 … VRT 0 … VIN 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Table 1. I/O Correspondence Table —8— Max. 150 110 0.4 570 ∗3 Rref: Resistance value between VRT and VRB ∗4 Iref = VRT – VRB Rref ∗5 T = 1 Fc ∗6 TPS: Times Per Sample 2 ∗7 Pd = (ICC + IEE) VCC + (VRT – VRB) Rref Typ. Unit 46 MHz dB 40 dB 150 0.6 790 10–12 TPS∗6 10–9 TPS 10–9 TPS 180 0.8 960 mA mA mW CXA3026AQ Electrical Characteristics Measurement Circuit Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit Current Consumption Measurement Circuit 100MHz 4V VRT 5V 5V A Icc A IEE AVCC DVCC1 DVCC2 Amp OSC1 φ: Variable DGND3 VIN fr 8 CXA3026AQ Logic Analizer CLK 1.95V VIN 5MHz PECL CLK/E 1024 samples OSC2 VRB 2V ECL Buffer DGND2 DGND1 AGND 100MHz DVEE3 Aperture Jitter Measurement Method Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit VRT +V VIN VRM2 VRB S2 S1 : ON when A<B S2: ON when A>B S1 CLK 129 128 127 126 125 ∆υ ∆t –V VIN A<B A>B Comparator VIN CXA3026AQ 8 "0" A8 to A1 B8 to B1 8 A0 B0 "1" Buffer CLK DVM 000…00 to 111…10 Controller Sampling timing fluctuation (= aperture jitter) Where σ(LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Taj is: Taj = σ / Error Rate Measurement Circuit Signal Source VIN Fc 4 –1kHz CXA3026AQ 8 CLK + 2Vp-p Sin Wave 16LSB Signal Source Fc ∆υ ∆t = σ/ ( 256 2 × 2 πf ) A Latch B CLK σ (LSB) 1/8 —9— Latch Comparator A>B Pulse Counter CXA3026AQ Description of Operating Modes The CXA3026AQ has two types of operating modes which are selected with Pin 45 (SELECT). Operating mode SELECT Maximum conversion rate Data output Clock output DMUX mode VCC 140MSPS Demultiplexed output 70 Mbps The input clock is 1/2 frequency divided and output. 70 MHz Straight mode GND 100MSPS Straight output 100 Mbps The input clock is inverted and output. 100 MHz Table 2. Operating Mode Table 1. DMUX mode (See Application Circuit 1– (1), (2) and (3).) Set the SELECT pin to VCC for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the RESETN pin (Pin 46 or 48). The RESET signal requires the setup time (T_rs ≥ 3.5 ns) and hold time (T_rh ≥ 0 ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET signal to low for T_rs (min.) + T_rh (min.) = 3.5 ns or longer to the clock rising edge. The reset period can be extended by making the low level period of the RESET signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is regarded as not important, the timing where the RESET signal is set from high to low is not so consequence. However, when the reset is released this timing must become significant because the timing is used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary. See the timing chart for detail. (This chart shows the example of reset for 2T). The A/D converter can operate at FC (min.) = 140MSPS in this mode. —10— CXA3026AQ When the RESET signal is not used. AAA AAA AAA AAA AAA CLK CXA3026AQ CLK CLK A CLKOUT 8bit DATA RESETN CXA3026AQ CLK B CLKOUT 8bit DATA RESETN When the RESET signal is used. CLK AAA AAA AAA AAA AAA RESET signal CXA3026AQ CLK A CLK CLKOUT DATA RESETN CXA3026AQ B CLK RESET signal RESETN (Reset period) 8bit CLKOUT (Reset period) 8bit DATA 2. Straight mode (See Application Circuits1- (4), (5) and (6).) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3026AQ supports ECL, PECL and TTL levels. The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. Digital input level DVEE3 DGND3 ECL PECL TTL –5 V 0V 0V 0V +5 V +5 V Supply voltage Application circuits ±5 V +5 V +5 V Table 3. Logic Input Level and Power Supply Settings —11— (1) (2) (3) (4) (5) (6) CXA3026AQ Application Circuit 1 (1) DMUX ECL input –5V (D) DG ECL RESET signal 4V DG AG AG 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 P1D0 to P1D7 8-bit Digital Data 8-bit Digital Data Latch DG DG +5V (D) +5V(A) 2V +5V(A) –5V(D) AG AG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 8-bit Digital Data P2D0 to P2D7 8-bit Digital Data Latch 13 14 15 16 17 18 19 20 21 22 23 24 ECL-CLK DG +5V(D) (2) DMUX PECL input +5V (D) DG 48 47 46 45 44 43 42 41 40 39 38 37 35 3 34 33 5 32 6 31 7 30 8 10 27 11 26 12 25 4V +5V(A) 4 29 9 28 P1D0 to P1D7 8-bit Digital Data 8-bit Digital Data Latch DG DG +5V (D) 36 2 2V 1 +5V(D) AG AG +5V(A) AG AG DG AG PECL RESET signal P2D0 to P2D7 8-bit Digital Data 8-bit Digital Data Latch 13 14 15 16 17 18 19 20 21 22 23 24 PECL-CLK DG +5V(D) (3) DMUX TTL input –5V (D) DG 4V +5V(D) +5V(A) AG AG 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 TTL-CLK DG +5V(D) —12— P1D0 to P1D7 8-bit Digital Data 8-bit Digital Data Latch DG DG +5V (D) 2V 48 47 46 45 44 43 42 41 40 39 38 37 +5V(A) AG AG AG DG TTL RESET signal 8-bit Digital Data P2D0 to P2D7 8-bit Digital Data Latch CXA3026AQ (4) Straight ECL input –5V (D) DG 5 32 6 31 7 30 4V 34 33 DG AG AG 3 4 8 29 9 28 10 27 11 26 12 P1D0 to P1D7 8-bit Digital Data 8-bit Digital Data Latch DG +5V (D) 35 DG 36 2 +5V(A) AG 2V 48 47 46 45 44 43 42 41 40 39 38 37 1 +5V(A) –5V(D) AG AG DG 25 13 14 15 16 17 18 19 20 21 22 23 24 ECL-CLK ECL→TTL DG +5V(D) (5) Straight PECL input +5V (D) DG 35 3 34 4 33 5 32 6 31 7 30 10 27 11 26 4V 8 29 9 28 12 P1D0 to P1D7 8-bit Digital Data 8-bit Digital Data Latch DG DG +5V (D) 36 2 +5V(A) 2V 48 47 46 45 44 43 42 41 40 39 38 37 1 +5V(D) AG AG +5V(A) AG AG DG AG DG 25 13 14 15 16 17 18 19 20 21 22 23 24 PECL-CLK PECL→TTL DG +5V(D) (6) Straight TTL input +5V (D) DG 35 3 34 4 33 5 32 6 31 7 30 10 27 11 26 4V 8 29 9 28 12 25 13 14 15 16 17 18 19 20 21 22 23 24 TTL-CLK DG +5V(D) —13— P1D0 to P1D7 8-bit Digital Data DG DG +5V (D) 36 2 +5V(A) 2V 48 47 46 45 44 43 42 41 40 39 38 37 1 +5V(D) AG AG +5V(A) AG AG DG AG DG 8-bit Digital Data Latch CXA3026AQ Application Circuit 2 Straight Mode TTL I/O (When a single power supply is used) AA AG Analog input AG 4V +5V (A) AG +5V (D) DG 2V 1µF 1µF AG A G 10µF 12 11 10 9 8 7 6 5 4 3 2 DGND3 VRT AGND VRM3 AVCC VRM2 VIN AVCC VRM1 AGND VRB short 13 CLK/E RESETN/E 48 14 CLKN/E 15 1 DVEE3 short 10µF RESET/E 47 CLK/T RESETN/T 46 TTL CLK 16 N.C. SELECT 45 17 N.C. INV 44 18 N.C. CLKOUT 43 19 DVCC2 DVCC2 42 33 34 35 36 P1D6 (MSB) P1D7 P1D3 32 P1D3 31 P1D2 30 P1D2 29 P1D1 28 P1D1 DVCC2 27 P1D0 DVCC1 26 (LSB) P1D0 DGND1 25 DGND2 P2D7 P1D4 37 (MSB) P2D7 24 P2D3 P2D6 P1D5 38 P2D6 23 P2D2 P2D5 P1D6 39 P2D5 22 P2D1 P2D4 P1D7 40 P2D4 P2D2 P2D3 (LSB) P2D0 P2D1 21 P2D0 P1D4 P1D5 DGND2 41 20 DGND2 Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —14— CXA3026AQ DMUX Mode Timing Chart (Select = VCC) Tds N-1 N+6 4.5ns (typ.) N+5 N+7 VIN N+3 N T N+4 N+2 N+1 CLK Tpw1 Tpw0 Tdo2;8ns (typ.) 6.5ns (min.) 10ns (max.) P1D0 to D7 N+1 P2D0 to D7 N 2.0V 0.8V 2.0V 0.8V N+3 N+2 ≈T Td_clk;7ns (typ.) ≈T Tdo1 8ns (max.) T+1ns (typ.) 4.5ns (min.) (Reset period) CLK OUT 2.0V 2.0V 2.0V 0.8V 0.8V 0.8V 4.5ns (min.) T_rh T_rs 8ns (max.) Td_clk T_rs T_rh RESET signal Straight Mode Timing Chart (Select = GND) N+2 N–1 N+3 N+1 VIN Tds 4.5ns (typ.) N T CLK Tpw1 Tpw0 Tdo2;8ns (typ.) 6.5ns (min.) 10ns (max.) P1D to D7 N–4 P2D0 to D7 N–5 2.0V 0.8V 2.0V 0.8V N–3 N–2 N–1 N N–4 N–3 N–2 N–1 Td_clk;7ns (typ.) 4.5ns (min.) 8ns (max.) CLK OUT (CLK is inverted and output.) 2.0V 0.8V RESET signal —15— CXA3026AQ A/D Converter and Peripheral Circuit Timing In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLKOUT in same phase is described in detail as below. For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data delay are showed in the following specification, i,e. Td_clk 4.5 nS (min.) --- 8.0 nS (max.) Tdo2 6.5 nS (min.) --- 10 nS (max.) These values are considered in all the temperature change and power supply variation. When the maximum clock rate 140MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the 3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be changed in same trend at the same condition of the temperature change and power supply variation. As a result, 0.5 ns of the delay will be faster, when the highest temperature and highest power supply is used. Also, 0.5 ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay can be omitted in this case. When Ta=25 °C, VCC=+5 V, the clock delay and data delay are Td_clk 5.0 nS (min.) --- 7.5 nS (max.) Tdo2 7.0 nS (min.) --- 9.5 nS (max.) The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the set-up time for the data latching can be obtained as ts (min.)=2.5 nS. The output delay change of the DATA OUT and CLK OUT due to the temperature change and the power supply variation should have the same trend of the delay change, the minimum ts=2.5 ns can be guaranteed at any temperature change and power supply variation. A A A A A Analog input R Analog input G Analog input B CLK RESET AAA AAAA AA AAA AAAA AA AAA AAAA AA AAA AAAA AA AA AAA AAAA AAA AAAA AA AA AAA AAAA AAA AAAA A AA A A AA AA CXA3026AQ Gate Array 8bit Vin P1D/out CLK P2D/out Latch 8bit RESET CLKOUT CXA3026AQ 8bit Vin P1D/out CLK P2D/out 8bit RESET CLKOUT CXA3026AQ 8bit Vin P1D/out CLK P2D/out 8bit RESET CLKOUT 7ns (=1/140MSPS) CLK th-reset RESET signal Td-clk (min) 5.0ns (4.5ns) Td-clk (max) CLKOUT 7.5ns (8.0ns) Tdo2 (min) 7.0ns (6.5ns) Tdo2 (max) 9.5ns (10ns) P1D/out P2D/out AA AAA A ts (min) 2.5ns Remark : In the timing chart, the values in the brackets ( ) are included all the temperature change and the power supply variation. —16— th (min) 6.5ns 14ns CXA3026AQ Notes on Operation • The CXA3026AQ is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows. — The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. — To prevent interference between AGND and DGND and between AV CC and DV CC, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVCC and DVCC lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. — Ground the power supply pins (AVCC, DVCC1, DVCC2, DVEE3) as close to each pin as possible with a 0.1 µF or larger ceramic chip capacitor. (Connect the AVcc pin to the AGND pattern and the DVCC1, DVCC2 and DVEE3 pins to the DGND pattern.) — The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21 pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them to AGND with approximately 1 µF tantal capacitor and, 0.1 µF chip capacitor as short as possible. • If the CLK/E pin is not used, by-pass this pin to DGND with an approximately 0.1 µF capacitor. At this time, approximately DGND3 – 1.2 V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. • When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open. • The CXA3026AQ uses the package with low thermal resistance, but the resistance varies according to the board used. Therefore, cool the package by air cooling and others referring to the right graph. Ta-Allowable ambient temperature (°C) Allowable ambient temperature vs. Wind velocity 90 Four-layer board 80 Double-layer board 70 Single layer board 60 Board conditions; 76mm × 114mm, 1.6t when glass epoxy board mounted 0 1 2 Wind velocity (m/s) —17— 3 CXA3026AQ Example of Representative Characteristics Current consumption vs. Ambient temperature characteristics Current consumption vs. Conversion rate characteristics response 170 Current consumption [mA] Current consumption [mA] 170 160 150 140 130 160 fin= 150 fCLK 4 –1kHz DMUX mode CL=5pF 140 130 25 –25 75 70 0 Ta—Ambient temperature [°C] Fc – Conversion rate [MSPS] Analog input current vs. Analog input voltage characteristics Reference current vs. Ambient temperature characteristics 140 20 Reference current [mA] Analog input current [µA] 200 VRT=4V VRB=2V 100 15 10 0 2 3 4 –25 Analog input voltage [V] 25 Ta—Ambient temperature [°C] —18— 75 CXA3026AQ SNR vs. Input frequency response Error rate vs. Conversion rate characteristics 50 10 –6 Error Rate [TPS] SNR [dB] 40 30 Fc=140MSPS 20 10 –7 10 –8 10 –9 10 1 3 10 5 30 –10 140 50 Input frequency [MHz] Fc–Maximum conversion rate [MSPS] 180 fCLK –1kHz 4 Error>16LSB Error rate: 10–9 TPS fin= 160 150 140 –25 25 160 Fc–Conversion rate [MSPS] Maximum conversion rate vs. Ambient temperature characteristics 170 fCLK –1kHz 4 Error>16LSB fin= 75 Ta—Ambient temperature [°C] —19— 180 CXA3026AQ CXA3026AQ Evaluation Board Description The CXA3026AQ Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3026AQ. After latching the CXA3026AQ output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector. Features • Resolution: • Maximum conversion rate: • Supply voltage: • Dual analog input pins: 8 bits 140MSPS (min.) ±5.0 V DIR.IN: AC coupling input pin AMP.IN: Operational amplifier input pin • Clock frequency division: 1/1 to 1/16 Absolute Maximum Ratings • Supply voltage VCC VEE +AMP –AMP –0.5 to +7.0 –7.0 to +0.5 –0.5 to +7.0 –7.0 to +0.5 Recommended Operating Conditions • Supply voltage VCC GND VEE +AMP –AMP | (+AMP) – (–AMP) | • Analog input AMP. IN DIR. IN • Clock input CLK. IN V V V V Min. +4.75 –5.50 +3 –7 9 –0.75 1.5 0.8 —20— Typ. +5.0 0 –5.0 +5 –5 10 0 2.0 1.0 Max. +5.25 –4.75 +7 –3 11 +1.05 2.2 1.2 V V V V V V V Vp-p Vp-p CLK IN AMP IN DIR IN 51Ω +AMP DGND 51Ω AGND 82Ω AGND –AMP DGND CON3 AGND CON1 AGND CON2 CON6 VEE 0.1µF 1kΩ VCC VBB × (–2) 1kΩ 390Ω AGND GND 130Ω 270Ω Vrt Vrb Vrb Vrt B S1 A (PECL) 4 (PECL) OFFSET OFFSET. R3 VRB VIN VRT S2 CLKOUT P2D0 to D7 (TTL) 4 INV P1D0 to D7 SW2 SW3 A/D D/A INV INV NORM CXA3026AQ SW1 CLK Straight SELECT DMUX 8 P1 side DATA CON7 (TTL) (TTL) 8 (TTL) LATCH LATCH VRT. R2 Counter 8 P2 side DATA CON8 (TTL) 8 (TTL) TTL / ECL TTL / ECL VRB. R1 PECL / TTL —21— TTL / ECL 8 (ECL) (ECL) 8 (ECL) AGND CON5 AGND CON4 D / A OUT (–1.0V) P2 side OUT P1 side OUT D / A OUT (–1.0V) FULL SCALE. R4 FULL SCALE. R5 DAC DAC Block Diagram CXA3026AQ CXA3026AQ Pin Description and I/O Level Pin No. Symbol I/O Standard I/O level Current Description CON1 AMP. IN I 0.95 Vp-p Doubles the analog input signal amplitude using the operational amplifier. The input impedance is 50 Ω. CON2 DIR. IN I 2.0 Vp-p AC coupling input. Suitable for sine waves and other repeating waveforms. The input impedance is 50 Ω. CON3 CLK. IN I 1.0 Vp-p The CXA3026AQ operates at the PECL level clock using the sine wave-to-PECL conversion circuit. The input impedance is 50 Ω. CON4 P1 side OUT O 0 to –1 V Allows the D/A converted waveform of the CXA3026AQ port 1 side data to be observed. The output impedance is 50 Ω. CON5 P2 side OUT O 0 to –1 V Allows the D/A converted waveform of the CXA3026AQ port 2 side data to be observed. The output impedance is 50 Ω. VCC I +5.0 V GND I 0V VEE I –5.0 V –0.6A +AMP I +5.0 V 40 mA + side power supply for the operation amplifier. –AMP I –5.0 V –40 mA – side power supply for the operation amplifier. CON7 P1 side DATA O TTL The CXA3026AQ port 1 side data output is latched at the frequency divided clock and then output. CON8 P2 side DATA O TTL The CXA3026AQ port 2 side data output is latched at the frequency divided clock and then output. CON6 0.8A The inside of the board is divided into analog and digital systems. Board Adjustments and Settings 1. VRB.R1: CXA3026AQ VRB voltage adjusting volume. 2. VRT.R2: CXA3026AQ VRT voltage adjusting volume. 3. OFFSET.R3: Adjusting volume for matching the AMP.IN input and DIR.IN input signal ranges to the CXA3026AQ input range. 4. FULL SCALE.R4: Full-scale adjusting volume for the port 1 D/A output. (–1 V: Typ.) 5. FULL SCALE.R5: Full-scale adjusting volume for the port 2 D/A output. (–1 V: Typ.) 6. S1: Switching junction for the dual analog input pins. Set as follows according to the input pins used. Junction A B AMP.IN OPEN SHORT DIR.IN 0.1 µF 10 kΩ Symbol 7. S2: 8. SW1 SELECT: 9. SW2 A/D INV: 10. SW3 D/A INV: Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3026AQ clock output. CXA3026AQ output mode selector switch. CXA3026AQ output polarity inversion switch. D/A converter output polarity inversion switch. —22— CXA3026AQ Notes on Board Operation 1. The factory settings for the CXA3026AQ Evaluation Board are as follows. VRB.R1 = 1.5 V VRT.R2 = 3.0 V OFFSET.R3 = 2.25 V FULL SCALE.R4 = –1 V FULL SCALE.R5 = –1 V S1 A … OPEN, B…SHORT S2 8 … SHORT (1/8 frequency division) When using the board in this condition, the input signals should be input at the amplitudes shown below. (The frequency is set as desired.) 0V center, 800mVp-p or less Analog input signal: CON1 (AMP.IN) Clock input signal: CON3 (CLK.IN) 0V center, 1.0Vp-p 2. When the analog signal is input from the CON1 (AMP.IN) pin, IC2:CLC404 limits the input dynamic range of the A/D converter’s analog input signal according to the +AMP and –AMP supply voltages. The power supply for the operational amplifier can also be shifted to +AMP = +7.0 V and –AMP = –3.0 V to allow use with a wider input dynamic range. 3. When the analog input signal is a sine wave or other repeating waveform, the signal can be input from the CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited by the +AMP and –AMP supply voltages, but the VRT level may be limited by IC3:NJM3403A. Therefore, the power supply for the operational amplifier should be shifted in the same manner as in 2. above. 4. In the evaluation board of the CXA3026AQ,CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though,CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case. —23— CXA3026AQ CXA3026AQ Evaluation Board Timing Chart N N+3 N+1 CON2 DIR IN 2Vp-p 0V N+2 CON3 CLK IN CXA3026AQ CLK CXA3026AQ P1 side DATA 1Vp-p 0V (PECL) (TTL) N–4 N–3 N–2 N–1 Approximately 6.0ns CON7 P1 side DATA CLK (TTL) CON7 P1 side DATA DATA (TTL) Approximately 9.0ns N–6 N–4 N–2 N–6 CON4 P1 side OUT N–4 N–2 (Analog regeneration waveform) 0 to –1V Operating Conditions CXA3026AQ operating mode : Straight mode : DIR IN pin input Anaiong : 1/2 frequency divided clock S2 setting —24— CXA3026AQ Circuit Diagram CON6 –AMP +AMP VEE L1 C1 33µF –AMP C2 33µF +AMP GND L2 L3 C3 33µF VCC L4 L5 C4 33µF AVEE DVEE C5 33µF AGND DGND L6 C6 33µF AVCC DVCC SW3 DGND D / A INV SW2 C28 0.1µF A / D INV SW1 DVCC DGND DVCC SELECT AGND –AMP AGND C29 0.1µF –AMP D / A INV CLKOUT C7 1µF C16 0.1µF C8 1µF C17 0.1µF P1D7 P1D6 P1D5 AGND P1D4 P1D3 4 AGND R14 130 AGND AGND IC2 7 CLC404 AGND C24 0.1µF C26 0.1µF C21 0.1µF DVCC C18 0.1µF C10 1µF P1D4 P1D5 P1D6 P1D7 DVCC2 DGND2 INV CLKOUT 9 VRM3 P2D7 28 10 AGND P2D6 27 11 VRT P2D5 26 DGND C9 1µF SELECT DGND1 29 C19 0.1µF DGND C34 0.1µF P2D4 25 P2D7 P2D6 P2D5 13 14 15 16 17 18 19 20 21 22 23 24 AGND +AMP AGND P2D4 +AMP P2D3 C30 0.1µF DVCC P2D2 DVCC R28 R29 82 82 CON3 CLK IN DGND IC4B 10H116 (PECL) C15 0.1µF R19 51 DGND 7 6 10 9 R20 1k R21 390 R23 82 R22 1k IC4A 10H116 (PECL) 5 4 3 2 R30 82 15 14 P2D1 P2D0 DGND R27 130 R24 130 DGND 11 IC4D 10H116(PECL) IC4C 10H116 (PECL) 13 12 DGND DVCC DVCC1 30 8 AVCC 12 DGND3 C27 0.1µF C33 0.1µF DVCC2 31 IC1 CXA3026AQ 7 VRM2 C22 0.1µF C12 1µF IC3C NJM3403A 10 8 9 DGND2 32 6 VIN AVCC S1 P1D0 33 5 AVCC P2D3 R13 82 2 3 R17 43 P1D1 34 4 VRM1 P2D2 CON1 AMP IN R16 4 270 6 P1D2 35 3 AGND P2D1 AVCC P1D3 36 P2D0 B P1D0 2 VRB DGND2 AGND C23 C25 0.1µF 0.1µF AGND P1D1 1 DVEE3 DVCC2 A C20 0.1µF N.C. R15 270 C11 1µF R18 51 CON2 DIR IN N.C. R6 51 AGND N.C. IC3A NJM3403A AGND RESET / E 1 DGND RESETN / T 11 2 3 R11 200k IC3B NJM3403A 6 7 5 CLK / T R10 22k R12 390k RESETN / E R8 510 R2 1k R3 10k P1D2 48 47 46 45 44 43 42 41 40 39 38 37 CLKN / E D1 TL431CP R9 7.5k CLK / E R7 510 R1 2k R25 R26 130 130 13 CLK Cout 4 DGND DVCC 9 S1 7 S2 IC5 10H136 (PECL) 12 D0 Q3 3 11 D1 Q2 2 6 D2 Q1 15 5 D3 Q0 14 1 / 16 1/8 1/4 1/2 CLK CLKN —25— CXA3026AQ DGND DVcc 1 2 C35 0.1µF IC14 74ALS34 3 4 P1D7 P1D6 5 6 P1D5 9 8 P1D4 11 10 P1D3 13 12 P1D2 P1D1 1 3 2 4 P1D0 5 6 IC14 74ALS34 1 2 CON7 P1 side DATA IC15 74ALS34 25 26 DGND DGND C43 0.1µF DGND R47 620 1 OC AGND 16 S 11 CLK DVEE P1D7 P1D6 P1D5 2 1D 1Q 19 3 2D 2Q 18 4 3D P1D4 P1D3 P1D2 P1D1 P1D0 IC6 74AS574 3Q 17 5 4D 4Q 16 6 5D 5Q 15 7 6D 6Q 14 8 7D 7Q 13 9 8D 8Q 12 P1D7 P1D6 P1D5 11 IN8 OUT8 10 1 MSB AGND 28 12 IN7 OUT7 9 2 D2 VREF 27 OUT6 8 3 D3 AVEE 26 OUT5 7 4 D4 NC 25 17 IN4 OUT4 4 5 D5 NC 24 13 IN6 P1D4 IC9 MB767 14 IN5 P1D3 P1D2 P1D1 P1D0 18 IN3 OUT3 3 6 D6 19 IN2 OUT2 2 7 D7 20 IN1 OUT1 1 8 D8 R37 82 R43 270 C13 1µF AVEE C52 0.1µF NC 22 NC 21 CON4 P1 side OUT AGND OUT 20 NC 19 10 LSB R48 620 C44 0.1µF R42 1k R4 2k D2 TL431CP NC 23 IC12 CX20201-1 9 D9 DVEE C51 0.1µF 11 NC AGND 18 12 NC DGND 17 AGND DGND C53 0.1µF INV 16 13 CLKN DVEE 15 14 CLK DVEE DGND R38 82 R49 620 C45 0.1µF DGND 1 OC 16 S 11 CLK DVEE P2D7 P2D6 P2D5 2 1D 1Q 19 3 2D 2Q 18 4 3D P2D4 P2D3 P2D2 P2D1 P2D0 IC7 74AS574 P2D7 P2D6 P2D5 3Q 17 5 4D 4Q 16 6 5D 5Q 15 7 6D 6Q 14 8 7D 7Q 13 9 8D 8Q 12 11 IN8 OUT8 10 1 MSB AGND 28 OUT7 9 2 D2 VREF 27 OUT6 8 3 D3 AVEE 26 OUT5 7 4 D4 NC 25 17 IN4 OUT4 4 5 D5 NC 24 IC10 MB767 14 IN5 P2D3 P2D2 P2D1 P2D0 18 IN3 OUT3 3 6 D6 19 IN2 OUT2 2 7 D7 20 IN1 OUT1 1 8 D8 DVEE D / A INV CLKOUT R50 620 C46 0.1µF 19 OE CLKOUT 1 D0N 1 / 16 21 D2 20 D2N 1/4 16 D3 IC8 100390 14 D4 10 LSB NC 19 11 NC AGND 18 12 NC DGND 17 AGND CON5 P2 side OUT AGND DGND C56 0.1µF INV 16 DVEE 15 DVEE 12 D5 CLKN 11 D5N DVCC 1/8 7 A2 1/4 10 A3 R32 82 R35 130 R36 130 DGND Y2 1 IC11 10H124 Y2 3 C50 0.1µF Y3 15 Y3 12 DGND R41 620 Y4 14 11 A4 1/2 Y4 13 Q4 9 DVEE 1/1 DVCC Q5 10 1 2 S2 P2D7 IC15 74ALS34 8 9 P2D6 11 10 P2D5 13 12 P2D4 1 2 P2D3 3 4 P2D2 5 6 P2D1 9 8 P2D0 11 10 R34 130 R33 82 Y1 4 Q3 8 13 D4N CLK 5 A1 Q2 4 15 D3N 1/2 DGND NC 21 Y1 2 1 / 16 Q1 3 23 D1 22 D1N 1/8 C32 0.1µF C14 1µF AVEE 6 B Q0 2 24 D0 DGND R31 82 D3 TL431CP C55 0.1µF 17 VBB R46 620 C39 0.1µF CON8 P2 side DATA IC16 74ALS34 25 26 DGND —26— R45 270 NC 22 OUT 20 14 CLK R5 R44 2k 1k C54 0.1µF NC 23 IC13 CX20201-1 9 D9 13 CLKN DGND DGND AGND 12 IN7 13 IN6 P2D4 R39 130 R40 130 DVEE CXA3026AQ Component List No. Product name IC1 CXA3026AQ IC2 CLC404AJE IC3 NJM3403AM IC4 MC10H116L IC5 MC10H136L IC6, 7 74AS574N IC8 100390 IC9, 10 MB767P IC11 MC10H124L IC12, 13 CXA20201A-1 IC14 to 16 74ALS34 D1 to 3 TL431CP SW1 to 3 ATE1D-2F3-10 S1, 2 JX-1 CON1 to 5 01K0315 CON6 TJ-563 CON7, 8 (FAP-2601-1202) L1 to 6 ZBF503D-00 C1 to 6 Tantal capacitor C7 to 12 Tantal capacitor C15 Ceramic capacitor All parts other than those listed above Chip capacitor Function 8-bit A/D converter OP-AMP OP-AMP ECL Buffer ECL Countor TTL Latch PECL→TTL conversion TTL→ECL conversion TTL→ECL conversion 10-bit D/A converter TTL Buffer Shunt regulator Toggle switch Short pin BNC connector Power supply connector Flat cable connector Ferrite-bead filter 33µF 1µF 0.1µF No. R2 R1, 4, 5 R3 R46 to 50 Product name RJ-5W-1K RJ-5W-2K RJ-5W-10K RGLD4X621J Function 1kΩ volume resistor 2kΩ volume resistor 10kΩ volume resistor 620Ω network resistor R6, 18, 19 R7.8 R9 R10 R11 R12 R13, 23, 28 to 33, 37, 38 R14, 24 to 27, 34 to 36, 39, 40 R15, 16, 43, 45 R17 R20, 22, 42, 44 R21 R41 FRD-25SR (0.25W) 51Ω FRD-25SR (0.25W) 510Ω FRD-25SR (0.25W) 7.5kΩ FRD-25SR (0.25W) 22kΩ FRD-25SR (0.25W) 200kΩ FRD-25SR (0.25W) 390kΩ FRD-25SR (0.25W) 82Ω FRD-25SR (0.25W) 130Ω FRD-25SR (0.25W) 270Ω FRD-25SR (0.25W) 43Ω FRD-25SR (0.25W) 1kΩ FRD-25SR (0.25W) 390Ω FRD-25SR (0.25W) 620Ω 0.1µF Component side silk diagram —27— 74ALS34 74ALS34 74ALS34 ∗ CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.) CXA3026AQ Component side pattern diagram Solder side pattern diagram —28— CXA3026AQ Package Outline Unit : mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 12.0 – 0.1 36 25 0.15 24 48 13 13.5 37 12 0.8 + 0.15 0.3 – 0.1 ± 0.12 M 0.9 ± 0.2 1 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 PACKAGE STRUCTURE SONY CODE QFP-48P-L04 EIAJ CODE ∗QFP048-P-1212-B JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER / PALLADIUM PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —29—